JPH10285232A - Quadrature detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a quadrature detection circuit that automatically nullifies a DC offset even when the DC offset is generated in I and Q phase base band signals. SOLUTION: A quadrature detection circuit mixes frequencies of distributed modulation signals RS1, RS2 and local signals whose phase is shifted by 90 deg. from the modulation signals RS1, RS2 and the mixed signals are passed through low pass filters 16, 26. A/D converters 17, 27 A/D-convert outputs of the low pass filters 16, 26 respectively and digital adders 18, 28 add digital correction values DH1, DH2 to outputs of each A/D converter and provide an output of I and Q phase digital base band signals. In this case, an offset detection section 31 calculates mean values of the DC offset of I and Q phase digital base band signals respectively and a control section 30 sets the digital correction value based on the mean value of the DC offset calculated by the offset detection section 31 so that the mean values are respectively zero.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quadrature detection circuit, and more particularly to a distributor for distributing a modulated signal as first and second modulated signals, and a quadrature detector whose phase is shifted by 90.degree. 1, output the second local signal 9
A 0 ° phase shifter, a first mixer for mixing the first modulated signal and the first local signal, and removing a frequency component of the local oscillator included in a mixed output of the first mixer;
A first low-pass filter for outputting a phase baseband signal, a second mixer for mixing a second modulated signal and a second local signal, and the local part included in a mixed output of the second mixer The present invention relates to a quadrature detection circuit having a second low-pass filter that removes a frequency component of an oscillator and outputs a Q-phase baseband signal.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a conventional example of this type of quadrature detection circuit. In the quadrature detection circuit 40, the distributor 41 receives the modulated signal and distributes the modulated signal to the first and second signals SS1 and SS2. The 90 ° phase shifter 43 receives an oscillation output oscillated by the local oscillator 42 and outputs local signals having phases shifted by 90 ° from each other. The frequency mixers 45 and 55 (mixers 45 and 55) mix the signals SS1 and SS2 output from the distributor 41 with the output of the 90 ° phase shifter 43, and respectively output the baseband signals BB1 and BB.
2 is output. Low-pass filters 46 and 56 (LPF4
6, 56) are the outputs BB1, BB2 of the mixers 45, 55.
And removes the frequency component of the local oscillator 42 contained therein.

In this case, a double balance mixer (DBM) is used as the mixers 45 and 55. A diode is used in this circuit, and a DC
An offset voltage occurs. Also, when the LPFs 46 and 56 are configured as active filters by operational amplifiers or the like, a DC offset of the operational amplifier occurs. Therefore, in order to remove the DC offset, a reference power supply 6 using a regulator or a high-precision reference power supply is used.
0, and the voltage from the reference power supply 60 adjusted by the variable resistors 61 and 62 is converted into LP by voltage adders 47 and 57.
By adding to the outputs of F46 and F56, respectively,
It produces I-phase and Q-phase baseband signals with zero DC offset. When a Lissajous waveform is drawn with the I-phase and Q-phase baseband signals, as shown in FIG.
If there is no offset, draw a circle like a thick solid line with the center at the origin, and if there is a DC offset (if there is a DC offset with respect to the Q axis and I axis), the center is shifted from the origin and like a thin solid line Draw.

[0004]

A signal having a DC offset as described above is input to a baseband demodulation unit.
When demodulated, the bit error rate deteriorates and the quality of communication deteriorates. Therefore, in order to remove this DC offset, the conventional quadrature detection circuit uses a high-precision reference power supply 60 and voltage adders 47 and 57, and the variable resistors 61 and 62.
Is mechanically rotated to adjust the resistance value, and an appropriate voltage is supplied to the voltage adders 47 and 57. However, when a temperature change or an impact is applied to the quadrature detection circuit, the characteristics of the variable resistors 61 and 62 change, and a DC offset occurs in the I-phase or Q-phase baseband signal, and the variable resistor 6
There is a problem that 1,62 must be adjusted again.

In order to solve the above problem, the present invention automatically generates a DC offset even if a DC offset occurs in an I-phase and a Q-phase baseband signal due to a temperature change or a shock applied to a quadrature detection circuit. An object of the present invention is to provide a quadrature detection circuit capable of detecting an offset and making the detected DC offset zero.

[0006]

According to a first aspect of the present invention, there is provided a distributor for distributing a modulated signal as first and second modulated signals, and an oscillator output of a local oscillator. A 90 ° phase shifter for outputting first and second local signals whose phases are shifted from each other by 90 °, a first modulation signal and a first
And a first low-pass filter that removes the frequency component of the local oscillator included in the mixed output of the first mixer and outputs an I-phase baseband signal. A second mixer for mixing a second modulated signal and a second local signal, and removing a frequency component of the local oscillator included in a mixed output of the second mixer to output a Q-phase baseband signal. A first analog / digital converter for performing analog / digital conversion of an output of the first low-pass filter, the second low-pass filter comprising: A second analog / digital converter for performing analog / digital conversion on the output of the first analog / digital converter, and adding a first digital correction value to the output of the first analog / digital converter.
A first digital adder for outputting a phase digital baseband signal, and a second digital for adding a second digital correction value to the output of the second analog / digital converter and outputting the result as a Q-phase digital baseband signal An adder,
An offset detection unit that calculates an average value of the DC offsets of the I-phase digital baseband signal and the Q-phase digital baseband signal, based on the average value of the DC offset calculated by the offset detection unit;
A control unit that sets the first and second digital correction values so that the average value of the DC offsets of the I-phase digital baseband signal and the Q-phase digital baseband signal is zero.

According to a second aspect of the present invention, the offset detecting section includes the I-phase digital baseband signal and the Q-phase digital baseband signal.
The average value of the DC offset is calculated by sampling the phase digital baseband signal a predetermined number of times.

According to a third aspect of the present invention, the control unit sets the first digital correction value for the I-phase digital baseband signal in cooperation with the offset detection unit, and then sets the first digital correction value. The second digital correction value is set for the Q-phase digital baseband signal, and the above operation is repeated at appropriate timing thereafter.

In a fourth aspect of the present invention, the control unit cooperates with the offset detection unit to independently control the I-phase digital baseband signal and the Q-phase digital baseband signal with respect to the first phase digital baseband signal. , A second digital correction value.

[0010]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a quadrature detection circuit according to the present invention. In the quadrature detection circuit 10, a distributor 11 receives the modulated signal and distributes the modulated signal to first and second signals RS1 and RS2. 90
The phase shifter 13 receives the oscillation output oscillated by the local oscillator 12 and outputs local signals having phases shifted from each other by 90 °. Frequency mixers 15, 25 (mixers 15, 25)
Are the signals RS1, RS2 and 9 output from the distributor 11
The local signals of the 0 ° phase shifter 13 are mixed to output respective baseband signals BS1 and BS2. The low-pass filters 16 and 26 (LPFs 16 and 26) are
5 and 25 output BS1 and BS2 are input, and the frequency component of the local oscillator 12 included therein is removed.

The analog / digital converters 17 and 27 (A
/ D converters 17, 27) convert the analog output signals of the LPFs 16, 26 into digital signals, respectively. The digital adders 18 and 28 respectively apply digital correction values DH1 and DH2 from the control unit 30 to the input digital signals so that the DC offset of the digital signals input from the A / D converters 17 and 27 becomes zero. The digital adder 18 outputs the corrected result as an I-phase digital baseband signal, and the digital adder 28
Each is output as a phase digital baseband signal to the subsequent demodulation unit.

In this case, the offset detecting section 31 extracts a DC offset component of each output signal from the average value of the output signals of the digital adders 18 and 28, and transfers the result to the control section 30. The control unit 30 sets the digital correction values DH1 and DH so that the offset of the output signals of the digital adders 18 and 28 becomes zero in the addition of the digital adders 18 and 28 from the result extracted by the offset detection unit 31.
2 are output to the digital adders 18 and 28, respectively. As is apparent from such a configuration, this quadrature detection circuit 1
0 indicates A / A for the I-phase and Q-phase baseband signals.
After being converted into digital signals by the D converters 17 and 27,
Since the C offset processing is performed digitally, there is no need to use a variable resistor, and there is no need for readjustment for variations in the characteristics of components such as temperature changes, and a high-precision reference power supply or voltage adder is used. There is no need.

The operation of the quadrature detection circuit 10 shown in FIG. 1 will be described in more detail with reference to the flowchart of FIG. The control unit 30 provides predetermined initial values for the I phase and the Q phase to the digital adders 18 and 28 at the time of initializing (step S1). Next, the control unit 30 samples the I-phase digital baseband signal output from the digital adder 18 by the offset detection unit 31 N times, checks the averaged offset level, and determines whether the average is greater than zero or not. Or is equal to zero (S2).

If the average is greater than zero in step S2, the control unit 30 sets the digital correction value DH1
A negative digital value is set in the adder 18 as (S3),
If the average is smaller than zero, the control unit 30 sets a positive digital value in the adder 18 as the digital correction value DH1 (S4), and returns to step S2 again. When the average becomes equal to zero, the control unit 30 holds the set value for the adder 18 (S5), and the offset detection unit 31 outputs the Q-phase digital baseband signal output from the digital adder 28. Sampling is performed N times, the averaged offset level is checked, and it is determined whether the average is larger or smaller than zero or equal to zero (S6).

In step S6, if the average is larger than zero, the control unit 30 sets the digital correction value DH2
Is set to the adder 28 as a negative digital value (S7).
If the average is smaller than zero, the control unit 30 sets a positive digital value in the adder 28 as the digital correction value DH2 (S8), and returns to step S6 again. When the average becomes equal to zero, the control unit 30 holds the set value for the adder 28 (S9), and thereafter, the control unit 3
If 0, the operation from step S2 is repeated at appropriate timing.

In the above-described example, the control unit 30 alternately controls the I-phase and the Q-phase digital baseband signals because the fluctuation of the DC offset of both signals is based on the temperature change. This is because it is assumed that there is a lot and that there is almost no sudden change.
Therefore, needless to say, if necessary, the I-phase and Q-phase digital baseband signals may be separately and simultaneously controlled.

[0017]

As described above in detail, the quadrature detection circuit according to the first aspect of the present invention includes the first and second modulated signals, which are shifted from each other by 90 ° in phase with each other. In a quadrature detection circuit that mixes the frequency of a local signal with a local signal and passes the first and second low-pass filters to output I-phase and Q-phase baseband signals, the output of the first low-pass filter is A first analog / digital converter for performing analog / digital conversion, a second analog / digital converter for performing analog / digital conversion of the output of the second low-pass filter, and a first analog / digital converter. A first digital adder for adding a first digital correction value to an output and outputting it as an I-phase digital baseband signal; and a second digital correction value for adding an output of the second analog / digital converter to the first digital adder. A second digital adder that outputs a phase digital baseband signal, an offset detector that calculates an average of DC offsets of the I-phase digital baseband signal and the Q-phase digital baseband signal, and the offset detector D calculated above
The first and second digital correction values are set based on the average value of the C offset so that the average values of the DC offsets of the I-phase digital baseband signal and the Q-phase digital baseband signal are each zero. Since a variable resistor is not used, a DC offset due to a change in the characteristics of the variable resistor is less likely to occur, and a DC offset is generated due to a temperature change or an impact applied to the quadrature detection circuit. Even if the first and second digital adders are used, the first and second digital correction values from the control unit are used as the average values of the DC offsets of the I-phase and Q-phase digital baseband signals, respectively. Until the value becomes zero, the sum is added to the output of the first and second analog / digital converters.
The effect is that the C offset is automatically detected and zeroed out. Further, there is an effect that it is not necessary to use a high-precision reference power supply or a voltage adder.

Further, in the second invention, since the average value of the DC offset is calculated by sampling a predetermined number of times, the quadrature detection circuit can be easily realized by using the conventional sampling technique. In the third invention, since the I-phase and the Q-phase digital baseband signals are alternately controlled, both circuits can be controlled by a single circuit. Since the control is performed independently, there is an effect that the quadrature detection circuit can be easily realized even when the control speed is high.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a quadrature detection circuit according to the present invention.

FIG. 2 is a flowchart for explaining the operation of the quadrature detection circuit in FIG. 1;

FIG. 3 is a block diagram showing a conventional quadrature detection circuit.

FIG. 4 is a Lissajous figure drawn by an output of the quadrature detection circuit of FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Quadrature detection circuit 11 Divider 12 Local oscillator 13 90 degree phase shifter 15, 25 Mixer 16, 26 LPF 17, 27 A / D converter 18, 28 Digital adder 30 Control part 31 Offset detection part S1-S9 Step

Claims (4)

[Claims] 1. A distributor for distributing a modulation signal as first and second modulation signals, and an oscillation output of a local oscillator, and first and second local signals having phases shifted by 90 ° from each other. A 90 ° phase shifter, a first mixer for mixing the first modulated signal and the first local signal, and removing a frequency component of the local oscillator included in a mixed output of the first mixer; A first low-pass filter for outputting a phase baseband signal, a second mixer for mixing a second modulated signal and a second local signal, and the local part included in a mixed output of the second mixer A quadrature detection circuit having a second low-pass filter for removing a frequency component of an oscillator and outputting a Q-phase baseband signal, wherein the first low-pass filter performs an analog / digital conversion on an output of the first low-pass filter Analog / digital conversion A second analog / digital converter for performing analog / digital conversion on the output of the second low-pass filter; and adding a first digital correction value to the output of the first analog / digital converter to obtain I A first digital adder for outputting a phase digital baseband signal; a second digital for adding a second digital correction value to an output of the second analog / digital converter and outputting the result as a Q-phase digital baseband signal An adder; an offset detection unit that calculates an average value of DC offsets of the I-phase digital baseband signal and the Q-phase digital baseband signal; and an average value of the DC offset calculated by the offset detection unit. , The average of the DC offsets of the I-phase digital baseband signal and the Q-phase digital baseband signal The first and the first are set so that the respective values become zero.
A controller for setting a second digital correction value. 2. The apparatus according to claim 1, wherein the offset detection unit calculates the average value of the DC offset by sampling the I-phase digital baseband signal and the Q-phase digital baseband signal a predetermined number of times. A quadrature detection circuit as described. 3. The control section, in cooperation with the offset detection section, first sets the first digital correction value for the I-phase digital baseband signal, and then sets the Q correction value.
3. The quadrature detection circuit according to claim 1, wherein the second digital correction value is set for a phase digital baseband signal, and the operation is repeated at appropriate timing thereafter. 4. The control section cooperates with the offset detection section to independently control the first and second digital baseband signals for the I-phase digital baseband signal and the Q-phase digital baseband signal. 3. The quadrature detection circuit according to claim 1, wherein the correction value is set.