JPH10284522A - Flat type semiconductor device - Google Patents

Flat type semiconductor device

Info

Publication number
JPH10284522A
JPH10284522A JP9089540A JP8954097A JPH10284522A JP H10284522 A JPH10284522 A JP H10284522A JP 9089540 A JP9089540 A JP 9089540A JP 8954097 A JP8954097 A JP 8954097A JP H10284522 A JPH10284522 A JP H10284522A
Authority
JP
Japan
Prior art keywords
spring
contact terminal
unit
chip
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9089540A
Other languages
Japanese (ja)
Inventor
Masanori Saotome
全紀 早乙女
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP9089540A priority Critical patent/JPH10284522A/en
Publication of JPH10284522A publication Critical patent/JPH10284522A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/71Means for bonding not being attached to, or not being formed on, the surface to be connected
    • H01L2224/72Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

Abstract

PROBLEM TO BE SOLVED: To make offset of a spring hard to occur during transportation of an element by constituting an integral spring by mutually connecting unit springs which press each contact terminal to each semiconductor chip without pressurizing an upper board and a lower board which hold a semiconductor chip and a contact terminal body from top and bottom. SOLUTION: A unit spring 31 is formed by bending an annular spring material whose outer shape is almost square, and an integral spring 30 is constituted by connecting the unit springs 31 mutually by an outer frame 32. The integral spring 30 is used so that the outer frame 32 and a leg part 35 of the unit spring 31 come into contact with an upper board and a top 33 of the unit spring 31 comes into contact with a contact terminal. The unit spring 31 is a plate spring. According to this constitution, it is possible to reduce the number of parts when compared to a flat type semiconductor device wherein a separate spring is used for each semiconductor chip, thus greatly reducing the number of processes during assembly. Furthermore, offset of spring caused by transportation, etc., can be prevented since the spring is formed to an integral spring.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、絶縁ゲート型バ
イポーラトランジスタやフリーホイールダイオードな
ど、対向する二つの主面にそれぞれ第一、第二の主電極
を有する半導体チップを組み込み、上下に主電極をもつ
平型半導体装置に関する。
BACKGROUND OF THE INVENTION The present invention relates to a semiconductor chip having first and second main electrodes on two opposing main surfaces, such as an insulated gate bipolar transistor and a freewheel diode, and upper and lower main electrodes. The present invention relates to a flat type semiconductor device.

【0002】[0002]

【従来の技術】絶縁ゲート型バイポーラトランジスタ
(以下IGBTと略す)は、電圧駆動型で扱い易く、ま
た少数キャリアの注入による伝導度変調によりオン電圧
が小さい等の特長があり、パワースイッチングデバイス
として、モータのPWM制御インバータなどに幅広く使
われている。そして、最近の市場の要求は、大容量化へ
と向かってきている。このような中で、IGBTの大容
量化のために、一個のチップを大容量化する他に、チッ
プを複数個、同一パッケージ内に集積したモジュール構
造が採用されてきている。
2. Description of the Related Art An insulated gate bipolar transistor (hereinafter abbreviated as IGBT) is a voltage-driven type which is easy to handle, and has a feature that the ON voltage is small due to conductivity modulation by minority carrier injection. It is widely used in PWM control inverters for motors and the like. And recent market demands are toward higher capacity. Under such circumstances, in order to increase the capacity of the IGBT, in addition to increasing the capacity of one chip, a module structure in which a plurality of chips are integrated in the same package has been adopted.

【0003】ところで、IGBTのようなMOS(金属
−酸化膜−半導体)構造の制御電極をもつパワーデバイ
スでは、半導体チップの一主面上にエミッタ電極とゲー
ト電極とが並んで作られている。このために、IGBT
チップをパッケージ容器に組み込む場合に、下面側に作
られたコレクタ電極は、IGBTチップを放熱体兼用の
金属ベース上にマウントして外部に引き出すことができ
るが、エミッタ電極と、ゲート電極とは別々に外部リー
ド端子を介して引き出す必要がある。そこで、従来のパ
ッケージ組立構造では、前記の金属ベースとともにパッ
ケージ容器の上面側にエミッタ、ゲート用の外部リード
端子を装備しエミッタ電極と外部リード端子、およびゲ
ート電極と外部リード端子との間に線径300μm 程度
のアルミニウム導線をワイヤボンディングして、引き出
すようにしていた。ところで、前記した従来の組立構造
では、コレクタ側からの放熱はできるが、エミッタ側か
らの放熱は殆ど行われないために電流容量が大幅に制限
される。また、大電流容量のものではエミッタ電極に接
続したボンディングワイヤの本数も多くなり、特に複数
個のIGBTチップを同一パッケージ内に組み込んでモ
ジュール化した構成では、ワイヤ本数が数百本にもおよ
ぶため、内部配線インダクタンスが増大して、スイッチ
ング動作時に大きなサージが発生するといった問題や、
信頼性的な問題なども発生する。
In a power device having a control electrode of a MOS (metal-oxide-semiconductor) structure such as an IGBT, an emitter electrode and a gate electrode are formed side by side on one main surface of a semiconductor chip. For this, IGBT
When the chip is incorporated in a package container, the collector electrode formed on the lower surface side can be pulled out by mounting the IGBT chip on a metal base that also functions as a radiator, but the emitter electrode and the gate electrode are separated. Must be pulled out via an external lead terminal. Therefore, in the conventional package assembly structure, an emitter and an external lead terminal for a gate are provided on the upper surface side of the package container together with the metal base, and a wire is provided between the emitter electrode and the external lead terminal, and between the gate electrode and the external lead terminal. An aluminum conducting wire having a diameter of about 300 μm was drawn out by wire bonding. By the way, in the above-mentioned conventional assembly structure, heat can be radiated from the collector side, but heat radiation from the emitter side is hardly performed, so that the current capacity is greatly limited. Also, in the case of a large current capacity, the number of bonding wires connected to the emitter electrode also increases. Particularly, in a module configuration in which a plurality of IGBT chips are incorporated in the same package, the number of wires is several hundreds. However, there is a problem that the internal wiring inductance increases and a large surge occurs during the switching operation,
There are also reliability issues.

【0004】そこで、前記のワイヤボンディング構造に
よる放熱性、配線インダクタンスの問題解消を狙って、
平型半導体と同様にIGBTチップを平型パッケージに
組み込み、その主面に形成されたエミッタ電極、コレク
タ電極をそれぞれパッケージの上下面に露出する電極板
に面接触させて引き出すようにすることが考えられる。
しかしながら、IGBTはゲート電極にパッケージ側の
電極板を加圧接触させると、ゲート構造に加圧力が加わ
って、応力の生じる恐れがあり、従来の平型半導体装置
のままでは実用に供し得ない。
In order to solve the problems of heat dissipation and wiring inductance by the wire bonding structure,
It is considered that the IGBT chip is incorporated in a flat package like a flat semiconductor, and the emitter electrode and the collector electrode formed on the main surface are brought into surface contact with the electrode plates exposed on the upper and lower surfaces of the package, respectively, and are drawn out. Can be
However, when an IGBT is brought into contact with a gate electrode by pressing a package-side electrode plate under pressure, a pressing force is applied to the gate structure, which may cause stress, and cannot be put to practical use with a conventional flat semiconductor device.

【0005】このため、MOS構造のデバイスのエミッ
タ側にMOS構造をつくらずに電流通路と放熱を目的と
した、集電極とよばれる部分を設け、その集電極上に、
コンタクト端子体を位置決めガイドによって正確に配置
する方法が取られている。図4は、従来の平型半導体装
置の要部構成図で、同図(a)は断面図、同図(b)は
上部板を除いた平面図である。図4において、上部板7
と下部板8との間に、下から基板9、基板9にはんだ1
0によってはんだ付けされたチップ1、コンタクト端子
体4のそれぞれが位置決めガイド11によって、位置決
めされている。12は上部板7と下部板8とに固着さ
れ、IGBTチップ1を包含する絶縁環である。ばね1
5はコンタクト端子体4の上部凸部14で位置決めさ
れ、このばね15が上部板7とコンタクト端子体4とを
押さえつけている。使用時は、上部板7と下部板8とに
圧力を加えることにより、チップ1とコンタクト端子体
4の間で良好な面接触を得ている。前記のばね15は各
コンタクト端子体4に一個づつ独立して挿入されてい
る。
For this reason, a portion called a collector is provided on the emitter side of a device having a MOS structure for the purpose of providing a current path and heat dissipation without forming a MOS structure.
A method of accurately arranging the contact terminal body by a positioning guide has been adopted. FIGS. 4A and 4B are main part configuration diagrams of a conventional flat semiconductor device. FIG. 4A is a sectional view, and FIG. 4B is a plan view excluding an upper plate. In FIG. 4, the upper plate 7
Between the lower plate 8 and the substrate 9 from below,
Each of the chip 1 and the contact terminal body 4 which are soldered by the reference numeral 0 is positioned by the positioning guide 11. Reference numeral 12 denotes an insulating ring fixed to the upper plate 7 and the lower plate 8 and including the IGBT chip 1. Spring 1
5 is positioned by the upper convex portion 14 of the contact terminal body 4, and the spring 15 presses the upper plate 7 and the contact terminal body 4. During use, good surface contact between the chip 1 and the contact terminal body 4 is obtained by applying pressure to the upper plate 7 and the lower plate 8. The springs 15 are independently inserted into the contact terminal bodies 4 one by one.

【0006】図5はIGBTチップのエミッタ側の平面
図である。エミッタ電極と接続されたMOS構造を持た
ない集電極2が配置され、この集電極2にコンタクト端
子体が加圧接触される構造となっている。他に、ゲート
電極と接続され、ゲートリードを取り出すためのゲート
パッド3が設けられている。図6はコンタクト端子体の
要部構造図で、同図(a)は平面図、同図(b)は断面
図である。図6において、コンタクト端子体4は、IG
BTチップのエミッタ側を加圧するために設けた凸状の
チップ加圧部5と、その対向する面に上部凸部14が設
けられている。本コンタクト端子の構造としては、上部
凸部14がチップ加圧部5の外側を結んだ線を対向する
面に投影した線の範囲内に設けられている。このコンタ
クト端子体4は、電流通路と冷却体とを兼ねている。
FIG. 5 is a plan view of the IGBT chip on the emitter side. A collector electrode 2 having no MOS structure connected to the emitter electrode is arranged, and a contact terminal body is brought into pressure contact with the collector electrode 2. In addition, a gate pad 3 connected to the gate electrode for taking out a gate lead is provided. 6A and 6B are main part structural diagrams of the contact terminal body, wherein FIG. 6A is a plan view and FIG. 6B is a cross-sectional view. In FIG. 6, the contact terminal 4 is an IG
A convex chip pressing portion 5 provided to press the emitter side of the BT chip is provided, and an upper convex portion 14 is provided on a surface facing the chip pressing portion 5. As the structure of the present contact terminal, the upper convex portion 14 is provided within a range of a line obtained by projecting a line connecting the outside of the chip pressing portion 5 to the facing surface. The contact terminal body 4 also serves as a current path and a cooling body.

【0007】図7は従来のばね15の斜視図である。外
形がほぼ正方形の環状のばね材を折り曲げ、ばねとし
た。このばね15をコンタクト端子体4の上部凸部14
に合わせて組み立てられる。この場合頂点33が上部板
7に足部35がコンタクト端子体4に接触する。またア
ーム部34がばね作用をする。
FIG. 7 is a perspective view of a conventional spring 15. An annular spring material having a substantially square outer shape was bent to form a spring. This spring 15 is connected to the upper convex portion 14 of the contact terminal body 4.
Assembled according to. In this case, the apex 33 contacts the upper plate 7 and the foot 35 contacts the contact terminal body 4. Further, the arm portion 34 acts as a spring.

【0008】[0008]

【発明が解決しようとする課題】前記のように、各半導
体チップに独立した一個のばねを装着すると、組立工数
が増大する。また素子輸送時に、振動や衝撃などでばね
が位置ずれを起こして、半導体チップを破損する不具合
を生じる。本発明の目的は、前記の課題を解決して、組
立工数が少なく、且つ、素子輸送時の振動、衝撃などに
対し、位置ずれが起きにくいばねを有する平型半導体装
置を提供することにある。
As described above, when one independent spring is mounted on each semiconductor chip, the number of assembly steps increases. In addition, during element transport, the spring is displaced due to vibration, impact, or the like, causing a problem that the semiconductor chip is damaged. SUMMARY OF THE INVENTION An object of the present invention is to provide a flat semiconductor device having a spring which solves the above-mentioned problems and has a small number of assembling steps and is unlikely to be displaced by vibration, impact, or the like during element transportation. .

【0009】[0009]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明の半導体素子は、二つの主面にそれぞれ第
一、第二の主電極を有する複数個の半導体チップと、そ
の半導体チップの第一の主電極に接触する凸状のチップ
加圧部をもち、コンタクト端子体のチップ加圧部のある
面と対向する面に、チップ加圧部の外周を結んだ線をそ
の面に投影した線より内側に凸部を有し、各コンタクト
端子体の周囲に配置され、各半導体チップにそれぞれ対
応する個別のコンタクト端子体と、それらの半導体チッ
プとコンタクト端子体とを上下から挟む上部板と下部板
と、それら上部板と下部板とに固着され半導体チップを
包含する絶縁環とを備え、上部板と下部板とに加圧しな
い状態で、各コンタクト端子体を各半導体チップに押し
つける単位ばねとを備えるものにおいて、各単位ばねが
互いに接続される一体型ばねである構成とする。
In order to achieve the above object, a semiconductor device of the present invention comprises a plurality of semiconductor chips having first and second main electrodes on two main surfaces, respectively, A line connecting the outer periphery of the chip pressing portion to a surface of the contact terminal body having a convex chip pressing portion that is in contact with the first main electrode of the chip and facing the surface where the chip pressing portion is located. Having a convex portion on the inner side of the line projected to each of the contact terminals, arranged around the respective contact terminals, and individually sandwiches the individual contact terminals corresponding to the respective semiconductor chips and the semiconductor chips and the contact terminals from above and below. An upper plate, a lower plate, and an insulating ring fixed to the upper plate and the lower plate and including the semiconductor chip. Each contact terminal body is attached to each semiconductor chip in a state where the upper plate and the lower plate are not pressed. With the unit spring to press In those comprising, a configuration is integral spring each unit springs are connected to each other.

【0010】前記の単位ばねが互いに接続される一体型
ばねとすることで、組立工数を減じ、製造コストを低減
できる。また、単位ばねが互いに接続されず、独立して
いる場合と比べて、輸送時の振動等で単位ばねが位置ず
れを起こす確率を大幅に低減できる。また前記の単位ば
ねが環状で、且つ、折れ曲がった板ばねで形成されると
よい。
[0010] By forming the unit springs as integral springs connected to each other, the number of assembling steps can be reduced and the manufacturing cost can be reduced. Further, the probability that the unit springs are displaced due to vibration during transportation or the like can be greatly reduced as compared with the case where the unit springs are not connected to each other and are independent. Further, the unit spring may be formed of a ring-shaped and bent leaf spring.

【0011】このように、板ばねとすることで、小さな
ばねの厚みで所定の加圧力が得られる。また、折れ曲が
った板ばねの頂点が所定の幅で切り離されていると効果
的である。このようにすると、加圧力よる板ばねの変形
がスムーズに行われる。
As described above, by using a leaf spring, a predetermined pressing force can be obtained with a small spring thickness. Further, it is effective if the apex of the bent leaf spring is separated at a predetermined width. With this configuration, the leaf spring is smoothly deformed by the pressing force.

【0012】[0012]

【発明の実施の形態】図1はこの発明の一実施例の平型
半導体装置の構成図で、同図(a)はIGBTチップを
実装した平型半導体装置の要部断面図、同図(b)は同
図(a)の平型半導体装置の上部板を除いた状態の要部
平面図である。図1(a)において、セラミック製の絶
縁環12と、それに固着されたベロー部をもつ上部板
7、下部板8からなるパッケージ内に、下から下部板8
と上部板7との間に、基板9、基板9にはんだ10によ
りはんだ付けされたチップ1およびコンタクト端子体4
がそれぞれ位置決めガイド11によって、正確に位置決
めされ、単位ばね31を有する一体型ばね30がコンタ
クト端子体4の上部凸部14の周囲に挿入されて位置決
めされている。基板9は図示されない手段によって、パ
ッケージの下部板7に位置決めされている。16は半田
逃げ部である。位置決めガイド11は基板9に設けられ
た溝13によって位置決めされている。それぞれのコン
タクト端子体4が素子加圧時以外でも、一体型ばね30
によってパッケージ内で予備加圧されている。使用時
は、上部板7と下部板8とに、この予備加圧以上の圧力
を加えることにより、チップ1とコンタクト端子体4と
の間で良好な面接触を得る。なお、IGBTチップ1の
ゲート電極は、コンタクト端子体4と位置決めガイド1
1の穴を通って、基板9上に設けられた図示されていな
い絶縁端子を介して絶縁環12のゲート端子17にワイ
ヤボンディングされている。前述のようにIGBTは電
圧駆動型であり、ゲート信号は僅かな電流ですむので、
ゲートリードはワイヤボンディング方式でも構わない。
FIG. 1 is a structural view of a flat type semiconductor device according to an embodiment of the present invention. FIG. 1 (a) is a sectional view of a main part of a flat type semiconductor device on which an IGBT chip is mounted, and FIG. 2B is a plan view of a main part of the flat type semiconductor device of FIG. In FIG. 1A, a lower plate 8 is placed from below in a package including a ceramic insulating ring 12 and an upper plate 7 and a lower plate 8 having bellows fixed thereto.
A substrate 9, a chip 1 soldered to the substrate 9 with solder 10, and a contact terminal 4 between
Are accurately positioned by the positioning guides 11, and the integrated spring 30 having the unit spring 31 is inserted around the upper convex portion 14 of the contact terminal body 4 and positioned. The substrate 9 is positioned on the lower plate 7 of the package by means not shown. Reference numeral 16 denotes a solder escape portion. The positioning guide 11 is positioned by a groove 13 provided in the substrate 9. Even when each of the contact terminals 4 is not at the time of element pressurization, the integrated spring 30
Pre-pressurized in the package. At the time of use, a good surface contact between the chip 1 and the contact terminal body 4 is obtained by applying a pressure equal to or higher than the preliminary pressurization to the upper plate 7 and the lower plate 8. The gate electrode of the IGBT chip 1 is composed of the contact terminal 4 and the positioning guide 1.
It is wire-bonded to the gate terminal 17 of the insulating ring 12 through one hole through an insulating terminal (not shown) provided on the substrate 9. As described above, the IGBT is of the voltage drive type, and the gate signal requires only a small current.
The gate lead may be of a wire bonding type.

【0013】図1(b)において、絶縁環12内に、基
板9の溝13に置かれた位置決めガイド11、その中に
コンタクト端子体4が装着され、そのコンタクト端子体
の上部凸部14の周囲を取り囲むように単位ばね31が
装着され、各単位ばね31は外枠32に部分的に接続さ
れている。この外枠32で接続された単位ばね31で一
体型ばね30が構成されている。セラミック製の絶縁環
12は、図ではモデル化してコーナー部を直角に描いて
いるが、実際は円弧状をしている。
In FIG. 1B, a positioning guide 11 placed in a groove 13 of a substrate 9 and a contact terminal 4 are mounted in an insulating ring 12, and an upper protrusion 14 of the contact terminal is formed. The unit springs 31 are mounted so as to surround the periphery, and each unit spring 31 is partially connected to the outer frame 32. The unitary spring 31 connected by the outer frame 32 forms the integral spring 30. Although the insulating ring 12 made of ceramic is modeled in the drawing and the corner portion is drawn at a right angle, it is actually in the shape of an arc.

【0014】図2は図1で適用される一体型ばねの一例
で、その斜視図を示す。外形がほぼ正方形の環状のばね
材を折り曲げて単位ばね31とし、この単位ばね31を
外枠32で互いに接続して、一体型ばね30が形成され
る。この一体型ばね30は図1のように、外枠32と単
位ばね31の足部35は上部板7と接触し、単位ばね3
1の頂点33はコンタクト端子体4と接触するようにし
て使用される。丁度、図2と上下を逆にして使用する。
尚、単位ばね31は図で示すような板ばねである。
FIG. 2 is a perspective view showing an example of the integral spring applied to FIG. An annular spring material having a substantially square outer shape is bent to form a unit spring 31, and the unit springs 31 are connected to each other by an outer frame 32 to form an integrated spring 30. As shown in FIG. 1, the integral spring 30 has the outer frame 32 and the foot 35 of the unit spring 31 in contact with the upper plate 7 and the unit spring 3
The vertex 33 of 1 is used in contact with the contact terminal body 4. Just use it upside down from FIG.
The unit spring 31 is a leaf spring as shown in the figure.

【0015】このようにすると、各半導体チップ毎に独
立のばねを使用する従来の平型半導体装置と比べ、部品
点数を減少させることができて、組立時の工数を大幅に
低減できる。また一体型ばねとすることで、輸送等によ
るばねの位置ずれの発生を防止できる。図3は図2の変
形例で、別の一体型ばねの斜視図である。単位ばね31
の頂点33aは所定の幅Wで切り離されている。
In this case, the number of parts can be reduced and the number of steps in assembling can be greatly reduced as compared with a conventional flat type semiconductor device using an independent spring for each semiconductor chip. In addition, the use of the integral spring can prevent the displacement of the spring due to transportation or the like. FIG. 3 is a modified example of FIG. 2 and is a perspective view of another integrated spring. Unit spring 31
Are separated by a predetermined width W.

【0016】このように所定の幅Wだけ切り離すことに
よって、加圧で板ばねが沈んだときにアーム部34の変
形が足部35に及び、足部34が異常に変形することを
防止できる。そのため、板ばねの圧力が半導体チップに
スムーズに伝達され、ばね機能が図2よりも向上する。
尚、所定の幅Wとは板ばねが沈んだときに切り離された
頂点33aが互いに接触しない幅で、1mmから数mm
程度がよい。
By cutting off by a predetermined width W in this manner, it is possible to prevent the deformation of the arm portion 34 from extending to the foot portion 35 when the leaf spring sinks due to pressure, and to prevent the foot portion 34 from being abnormally deformed. Therefore, the pressure of the leaf spring is smoothly transmitted to the semiconductor chip, and the spring function is improved as compared with FIG.
The predetermined width W is a width in which the vertices 33a separated when the leaf spring sinks are not in contact with each other, and 1 mm to several mm.
Good degree.

【0017】前記の単位ばね31の内寸は、コンタクト
端子体4の上部凸部14の形状に合わせてあり、上部凸
部14に各単位ばね31が挿入され一体型ばね30は位
置決めされる。
The internal dimensions of the unit springs 31 are adapted to the shape of the upper projections 14 of the contact terminal body 4. Each unit spring 31 is inserted into the upper projections 14, and the integrated spring 30 is positioned.

【0018】[0018]

【発明の効果】以上述べたように、本発明によれば、単
位ばねを部分的に結合して一体型ばねとすることで、組
立工程における作業の簡略化および組立効率の向上を図
り、組立工数を低減することができる。またばねが一体
化されることで、輸送時の素子無加圧状態においても、
半導体チップおよびコンタクト端子体のそれぞれがフリ
ーな状態となることなく、振動などによるばねの位置ず
れのは発生を防止して、半導体チップが損傷することを
防ぎ、半導体装置の信頼性を高めることができる。
As described above, according to the present invention, the unit springs are partially connected to form an integrated spring, thereby simplifying the work in the assembling process and improving the assembling efficiency. Man-hours can be reduced. In addition, by integrating the spring, even when the element is not pressurized during transportation,
The semiconductor chip and the contact terminal body do not become free, and the displacement of the spring due to vibration or the like is prevented from occurring, the semiconductor chip is prevented from being damaged, and the reliability of the semiconductor device is improved. it can.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の一実施例の平型半導体装置の構成図
で、(a)はIGBTチップを実装した平型半導体装置
の要部断面図、(b)は(a)の平型半導体装置の上部
板を除いた状態の要部平面図
1A and 1B are configuration diagrams of a flat semiconductor device according to an embodiment of the present invention, in which FIG. 1A is a cross-sectional view of a main part of a flat semiconductor device on which an IGBT chip is mounted, and FIG. Main part plan view of the device without the upper plate

【図2】図1で適用される一体型ばねの斜視図FIG. 2 is a perspective view of an integrated spring applied in FIG. 1;

【図3】図2の変形例で、一体型ばねの斜視図FIG. 3 is a perspective view of a modified example of FIG. 2, showing an integrated spring;

【図4】従来の平型半導体装置の要部構成図で、(a)
は断面図、(b)は上部板を除いた状態の平面図
FIGS. 4A and 4B are main part configuration diagrams of a conventional flat semiconductor device, and FIG.
Is a cross-sectional view, and (b) is a plan view without the upper plate.

【図5】IGBTチップのエミッタ側平面図FIG. 5 is a plan view of the IGBT chip on the emitter side.

【図6】コンタクト端子体の要部構造図で、(a)は平
面図、(b)は断面図
6 (a) is a plan view, and FIG. 6 (b) is a cross-sectional view.

【図7】従来のばね15の斜視図FIG. 7 is a perspective view of a conventional spring 15;

【符号の説明】[Explanation of symbols]

1 IGBTチップ 2 エミッタ集電極 3 ゲートパッド 4 コンタクト端子体 5 チップ加圧部 6 上部加圧面 7 上部板 8 下部板 9 金属基板 10 半田 11 位置決めガイド 12 絶縁環 13 溝 14 上部凸部 15 ばね 16 半田逃げ部 17 ゲート端子 30 一体型ばね 31 単位ばね 32 外枠 33 頂点 33a 頂点 34 アーム部 35 足部 W 所定の幅 Reference Signs List 1 IGBT chip 2 Emitter collecting electrode 3 Gate pad 4 Contact terminal body 5 Chip pressing part 6 Upper pressing surface 7 Upper plate 8 Lower plate 9 Metal substrate 10 Solder 11 Positioning guide 12 Insulating ring 13 Groove 14 Upper convex part 15 Spring 16 Solder Relief portion 17 Gate terminal 30 Integrated spring 31 Unit spring 32 Outer frame 33 Apex 33a Apex 34 Arm 35 Foot W Predetermined width

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】二つの主面にそれぞれ第一、第二の主電極
を有する複数個の半導体チップと、その半導体チップの
第一の主電極に接触する凸状のチップ加圧部をもち、コ
ンタクト端子体のチップ加圧部のある面と対向する面
に、チップ加圧部の外周を結んだ線をその面に投影した
線より内側に凸部を有し、各コンタクト端子体の周囲に
配置され、各半導体チップにそれぞれ対応する個別のコ
ンタクト端子体と、それらの半導体チップとコンタクト
端子体とを上下から挟む上部板と下部板と、それら上部
板と下部板とに固着され半導体チップを包含する絶縁環
とを備え、上部板と下部板とに加圧しない状態で、各コ
ンタクト端子体を各半導体チップに押しつける単位ばね
とを備えるものにおいて、各単位ばねが互いに接続され
る一体型ばねであることを特徴とする平型半導体装置。
1. A semiconductor device comprising: a plurality of semiconductor chips having first and second main electrodes on two main surfaces thereof; and a convex chip pressing portion in contact with the first main electrode of the semiconductor chip. On the surface of the contact terminal body opposite to the surface where the chip pressing portion is located, a projection connecting the line connecting the outer periphery of the chip pressing portion to the surface is provided on the inner side, and the periphery of each contact terminal body is provided. Arranged and individually contact terminal bodies corresponding to each semiconductor chip, an upper plate and a lower plate sandwiching the semiconductor chip and the contact terminal body from above and below, and a semiconductor chip fixed to the upper plate and the lower plate. A unit spring that presses each contact terminal body against each semiconductor chip without applying pressure to the upper plate and the lower plate, wherein the unit springs are connected to each other. Is Flat and wherein a and.
【請求項2】単位ばねが環状で、且つ、折れ曲がった板
ばねで形成されることを特徴とする請求項1記載の平型
半導体装置。
2. The flat semiconductor device according to claim 1, wherein the unit spring is formed of a ring-shaped and bent leaf spring.
【請求項3】折れ曲がった板ばねの頂点が所定の幅で切
り離されていることを特徴とする請求項2記載の平型半
導体装置。
3. The flat semiconductor device according to claim 2, wherein the apex of the bent leaf spring is cut off at a predetermined width.
JP9089540A 1997-04-08 1997-04-08 Flat type semiconductor device Pending JPH10284522A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9089540A JPH10284522A (en) 1997-04-08 1997-04-08 Flat type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9089540A JPH10284522A (en) 1997-04-08 1997-04-08 Flat type semiconductor device

Publications (1)

Publication Number Publication Date
JPH10284522A true JPH10284522A (en) 1998-10-23

Family

ID=13973656

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9089540A Pending JPH10284522A (en) 1997-04-08 1997-04-08 Flat type semiconductor device

Country Status (1)

Country Link
JP (1) JPH10284522A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6108026B1 (en) * 2016-12-16 2017-04-05 富士電機株式会社 Pressure contact type semiconductor module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6108026B1 (en) * 2016-12-16 2017-04-05 富士電機株式会社 Pressure contact type semiconductor module

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