JPH10283796A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can shorten the blowing-out time of a fuse during redundant processing, can improve the versatility of a program for redundancy, and can be manufactured at an improved productivity. SOLUTION: In an ASIC 10a composed of a logic circuit 20 and memory cores 30a and 40a, the blowing-out time of a fuse is shortened during redundant work and the versatility of a program for redundancy is improved, and then, program making and verifying time is reduced by arranging the common fuse circuit 50 of the redundancy circuits of the memory cores 30a and 40a at a specific position on a board separately from the memory cores 30a and 40a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a memory device including a redundant memory, for example, an ASIC.

[0002]

2. Description of the Related Art ASIC (Application Specific Integ
A rated circuit is an integrated circuit that has both an arithmetic circuit that performs logical operations and a memory circuit that stores data.It is an integrated circuit that has been developed for specific uses and can perform complex processing with a simple circuit configuration. Is the feature. In the design of an ASIC, the memory cells are arranged with priority given to the characteristics of the circuit and the chip area.

As the capacity of a memory core built in an ASIC increases, the possibility of defective memory cells in the memory core increases, and the production yield tends to decrease. In order to solve this, a method of replacing the defective memory cell of the memory core with another memory cell, that is, performing a so-called redundant operation, and accessing a substitute memory cell instead of the defective memory cell at the time of memory access is generally adopted. Have been. A memory cell that replaces a defective memory cell is called a redundant memory cell. Before shipping, if the memory core is inspected and a defective memory cell is detected, for example,
An operation such as addressing of a redundant memory is performed by a method such as a fuse blown by a laser or an overcurrent. This is usually referred to as redundant memory programming. Defective memory cells can be relieved by the redundant operation, and the production yield of semiconductor devices can be improved.

[0004]

In the above-described conventional ASIC, the location of the memory core is arbitrarily specified, and the redundancy fuse is determined according to the type of LSI or the capacity of the ASIC memory to be used. Since the arrangement locations are different, there is a disadvantage in that when performing a redundant operation, it is necessary to extract the coordinates of the fuses on the substrate one by one. As a production process before shipment of a semiconductor device, there are inspection of a memory core and creation and operation verification of a redundant program when a defective memory cell is detected. From the viewpoint of the efficiency of these operations, when the laser device is moved in accordance with the coordinates of the redundant fuses of a plurality of memory cores,
For example, in the direction perpendicular to the semiconductor device substrate,
/ Y coordinate axes are defined and redundant devices such as lasers are
Moving only to either X or Y requires less processing time than moving both.

FIG. 8 shows an example of a layout on a conventional ASIC board. As shown, the ASIC 10
Is, for example, a logic circuit 20 that performs a process such as a logical operation.
And memory cores 30 and 40 for storing data. Further, redundant fuses 31 and 32 are provided in the memory core 30, and redundant fuses 41 and 32 are provided in the memory core 40.
42 and 43 are arranged respectively.

As shown in the figure, the locations of the redundant fuses are set at arbitrary positions on the substrate, and all the coordinates of these fuses are extracted during the redundancy operation, and the laser device is adjusted in accordance with the extracted coordinates. Go and program. For this reason, it is necessary to control the extraction and programming of coordinates for each ASIC.
And the Y-axis must be moved, which leads to a reduction in work efficiency. Further, the access time may be deteriorated or malfunction may occur depending on the layout arrangement of the redundant circuit.

FIG. 9 is a circuit diagram showing a configuration of a memory circuit including a redundant circuit. As shown in FIG. 9, address data A0, A1,..., An (n is a positive integer) input to the memory core are respectively addressed to address buffers ADRBUF0, ADRBUF.
, ADRBUFn are input to predecoders PRDEC0, PRDEC1,..., PRDECn. .., DECm (m is a positive integer) and redundant circuits RDC0, RDC1,.
Is input to For example, output signals of the decoders DEC0 to DEC3 are output to the drivers DRV0 to DRV3, respectively, and output signals of the redundant circuit RDC0 are output to the drivers DRV0 to DRV3 and the redundant driver RDRV0, respectively. Driver DRV0-RDV
3 drives the word lines WL0 to WL3, and the redundant driver RDRV0 drives the redundant word lines RW.
L0 is driven.

The decoders DEC4 to DEC7, the redundant circuit RDC1, the drivers DRV4 to RDV7, and the redundant driver RDRV1 also have the same configuration.

Address data A0, A1,
…, An is the address buffer ADRBUF0, ADRB
., ADRBUFn and output to the pre-decoder and the decoder. The decoder circuit outputs a word line selection signal according to the input address data A0, A1,..., An, and the word line is selected by the driver. In the redundant circuit, the address information input from the pre-decoder is collated based on fuse cutting information and the like, and if the addresses match, redundancy processing is performed, a predetermined word line driver is stopped, and the redundant driver is operated. Thereby, the redundant memory cell selected by the redundant word line is accessed instead of the defective memory cell.

The number of redundant circuits including redundant fuses is determined by the number of memory cell blocks of the memory core and the number of prepared redundant memory blocks. For example, in the circuit example shown in FIG. 9, redundancy is performed for each word line, and one redundant word line is provided for every four word lines.

FIG. 10 shows an example of the redundant circuit RDC. The redundant circuit RDC includes a preset pMOS transistor PTR, an output buffer BUF1, and an inverter INV.
1, fuses H0, H1, H2, H3 and nMOS transistors NT0, NT1, NT2, NT3. The source of the pMOS transistor PTR is connected to the supply line of the power supply voltage V _CC, the drain node ND
a, and the gate is connected to the input terminal of the reset signal RESET. The input terminals of the buffer BUF1 and the inverter INV1 are connected to the node NDa, and the output terminals are the output signal OUT and the inverted output signal O, respectively.
It is connected to the terminal of UTB.

One terminal of fuses H0, H1, H2, H3 is connected to node NDa, and the other terminal is connected to nMOS transistors NT0, NT1, NT2, NT3, respectively.
Connected to the drain of nMOS transistor N
The gates of T0, NT1, NT2, and NT3 are connected to input terminals of address signals IN0, IN1, IN2, and IN3, respectively, and the sources are grounded.

At the time of reset, the reset signal RESET is temporarily held at a low level. In response, pMOS transistor PTR is turned on, and node NDa is at power supply voltage V
Precharged to _CC level. During operation, address information IN0, IN1, IN2, IN3 from the predecoder is input. When the redundancy programming is performed, the fuse is blown in accordance with the redundancy address, and when the address is input, the node NDa is held at the precharged level (V _CC level), and the node NDa is set to the high level from the output terminal of the buffer BUF1. A level signal is output, a redundant driver operates in response to this, a redundant word line is selected, and a driver that selects a normal word line according to the output signal of the redundant circuit RDC is held in a stopped state. A normal memory cell row including a defective memory cell is deselected,
Instead, a redundant memory cell row is selected.

FIG. 11 shows the operation timing of the memory circuit shown in FIG. As shown, the input address A
The output signal of the predecoder is set according to 0, A1,..., An. At the time of reset, the output of the redundant circuit is preset according to the reset signal RESET. Then, during operation, the operating states of the driver and the redundant driver are controlled in accordance with the information of cutting the fuse in the redundant circuit and the address signal from the predecoder. When the memory cell is normal, the normal memory cell is accessed, and when the memory cell is defective and the address information is registered by blowing the fuse, the redundant memory cell is accessed.

In the example of the ASIC shown in FIGS. 9 and 10, the redundant circuit of the memory core can be arranged at an arbitrary position on the substrate. For this reason, the programming in the redundant operation includes complicated operations such as the extraction of the coordinates of the fuses of the redundant circuit and the movement of the laser device when the fuses are blown by the extracted coordinates, which hinders the efficiency of the production process. Also,
Depending on the position of the redundant circuit, there is a possibility that the memory access time may be deteriorated or malfunction may occur.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to separate a fuse portion of a redundant circuit from a memory circuit and arrange it at a specific position on a substrate so that coordinate extraction and fuse extraction can be performed. Cutting time can be shortened,
It is an object of the present invention to provide a semiconductor device capable of improving the versatility of a redundancy program and realizing an improvement in productivity.

[0017]

To achieve the above object, the present invention relates to a semiconductor device having at least one memory cell, wherein the redundant memory circuit has a redundant memory cell for replacing a defective memory cell in the memory circuit. And switching control means for switching access to the defective memory cell to the redundant memory cell. The switching control means is arranged in a predetermined area on the substrate separately from the memory circuit.

Further, in the present invention, the memory circuit is arranged on the substrate with priority given to circuit characteristics and chip area, and the switching control means is constituted by a fuse, and is used for the defective memory cell to be replaced by address registration. The address is specified.

Further, in the present invention, the address registration is performed, for example, by blowing the fuse by irradiating a laser beam.

According to the present invention, a semiconductor device comprising a memory circuit and a logic circuit other than the memory circuit,
For example, in an ASIC, a fuse portion of a redundant circuit is separated from a memory circuit and arranged in a predetermined region on a substrate. This allows the laser device to move only in a predetermined direction in operations such as fuse blowing in the redundancy processing.
Processing time can be reduced.

[0021]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor device according to the present invention. As shown in FIG. 1, a semiconductor device according to the present embodiment, for example, an ASIC 10a includes a logic circuit 20 that performs a process such as a logical operation, memory cores 30a and 40a that store data, and memory cores 30a and 4a.
0a is constituted by a common fuse circuit 50.
The common fuse 50 of the memory cores 30a and 40a is arranged at a specific position on the substrate separately from these memory cores. The fuse circuit 50 is provided with a fuse for registering an address, and the fuse is cut by a programming process for a redundant operation to register a redundant address.

The present embodiment is characterized in that the common fuse circuit 50 of the memory cores 30a and 40a is arranged separately from the memory cores 30a and 40a in a specific area on the substrate. By doing so, it is easy to extract the coordinates of the fuse during the redundant operation, and since the coordinates of the fuse are fixed, in the operation of blowing the fuse with the laser, the laser device needs to move only one of the X or Y axis, The programming processing time can be reduced and the production efficiency can be improved.

FIG. 2 is a circuit diagram of a memory circuit including a redundant circuit in this embodiment. The memory circuit of this example includes address buffers ADRBUF0, ADRBUF1,.
RBUFn, predecoders PRDEC0, PRDEC
1,..., PRDECn, redundant comparison circuit RDCM0, RD
CM1,..., RDCMn, decoders DEC0, DEC
1, ..., DECm and drivers DRV0, DRV
1, ..., DRVm and redundant driver RDRV0, RDR
, RDRVn.

Address data A0, A1,..., An are address buffers ADRBUF0, ADRBUF, respectively.
1,..., Predecoder PRDE via ADRBUFn
C0, PRDEC1,..., PRDECn.
Output signals from these predecoders are output to each decoder DE.
, DECm. The output signals of the decoders DEC0 to DECm are respectively
Output to RV0 to DRVm. Redundancy comparison circuit RDCM
, RDCMn, address data A0, A1,..., An and redundant address data A0R, A1R,. These redundant comparison circuits compare the address data with the redundant address data, and control the operating states of the driver and the redundant driver according to the comparison result.

For example, as shown in FIG. 2, the output signals of the redundancy comparison circuit RDCM0 are output from drivers DRV0 to DRV0, respectively.
Input to DRV3 and redundant driver DRRV0. When the address data input to the redundancy comparison circuit RDCM0 and the redundancy address data do not match, the drivers DRV0 to DRV3 are set to the operation state, and the redundancy driver RDRV0 is set to the non-operation state. On the other hand, when the address data input to the redundancy comparison circuit RDCM0 matches the redundancy address data, the driver DRV
0 to DRV3 are set to the non-operation state, and the redundant driver RDRV0 is set to the operation state.

Word lines WL0 to WLm are driven by drivers DRV0 to RDVm, respectively, and redundant word lines RW are driven by redundant drivers RDRV0 to RDRVn.
L0 to RWLn are respectively driven. As a result, for example, when there is a defective memory cell in the memory cells connected to the word lines WL0 to WL3, address information corresponding to the defective memory cell is registered in the fuse circuit 50 by redundant programming. At the time of access, the redundancy comparison circuit R
DCM0 detects a match between the input address data and the redundant address data.
Drivers DRV0 to RDV3 are set to a non-operation state, and redundant driver RDRV0 is set to an operation state. At the time of memory access, the word line connected to the defective memory cell is not driven, and instead, the redundant word line RW
Since L0 is driven, a redundant memory cell is accessed instead of a defective memory cell.

FIG. 3 shows an address buffer ADRBUFx.
(X = 1, 2,..., N) and a circuit diagram showing a configuration of a predecoder PRDECx. FIG. 3A is a circuit diagram of the address buffer. As shown, the address buffer includes an input buffer BUFIN1, an inverter INVL1, and an inverter INVL1.
NVL2, inverter INVO1, and output buffer B
It is composed of UFO1.

The input terminal of the buffer BUFIN1 is connected to the input terminal of the address data Ax, and the output terminal is connected to the node ND1. The input terminal of the inverter INVL1 is connected to the node ND1, and the output terminal is the node ND.
2 are connected. The input terminal of the inverter INVL2 is connected to the node ND2, and the output terminal is connected to the node ND1. That is, the inverters INVL1 and INV
L2 constitutes a latch circuit. Address data A
The address data input to the input terminal of x is latched by the latch circuit, and the node ND1 holds the signal of the same logic level as Ax, and the node ND2 holds the signal of Ax and the logic inversion level.

The input terminals of the output buffer BUFO1 and the inverter INVO1 are connected to the node ND2, the output terminal of the inverter INVO1 is connected to the address AAx terminal, and the output terminal of the buffer BUFO1 is the inverted address AB.
x terminal.

FIG. 3B is a circuit diagram of the predecoder PRDECx. The predecoder PRDECx includes an AND gate AND1 and inverters INVP1 and INVP2. The input terminal of the AND gate AND1 is
Addresses AAx, AAy (y =
1, 2,..., N) are input. AND gate AND1
Is connected to the input terminal of the inverter INVP1, and the output terminal of the inverter INVP1 is connected to the inverter INVP1.
The output terminal of the inverter INVP2 is connected to the output terminal POUT of the predecoder.

In the circuit example of FIG. 3B, a situation where two address signals are input to the AND gate AND1 is illustrated. However, in an actual predecoder circuit, the number of bits of address data depends on the number of address data bits. In some cases, a plurality of address signals are input. The output signal of each predecoder is input to the decoder, and the decoder outputs a driver control signal. A predetermined word line is driven by the driver according to the control signal. As a result, the word line specified by the address data is driven according to the input address data A, A1,..., An.

FIG. 4 is a circuit diagram of the redundancy comparison circuit RDCMx and the driver DRVx or the redundancy driver RDRVx. FIG. 4A is a circuit diagram of the redundant comparison circuit RDCMx. As shown in the figure, the redundancy comparison circuit RDCMx includes exclusive OR gates EXOR0 and EXOR1, an AND gate AND2, and an inverter INVO2. Exclusive OR gate EXOR
Address data A0 and redundant address data A0R are respectively input to input terminals of 0, and address data A1 and redundant address data A1R are input to input terminals of an exclusive OR gate EXOR1.

Exclusive OR gate EXOR0,
The output signal of EXOR1 is input to AND gate AND2. Further, the redundancy enable signal RENB is also input to the AND gate AND2. The output terminal of the AND gate AND2 is connected to the output terminal of the redundant signal ROUT, and further connected to the input terminal of the inverter INVO2.
The output terminal of the inverter INVO2 is a redundant inversion signal ROU.
It is connected to the output terminal of TB.

FIG. 4B is a circuit diagram of the driver and the redundant driver. The driver for the normal word line and the driver for the redundant word line have the same configuration, and both are shown in FIG. 4B. Note that a normal driver, for example, the drivers DRV0 to DRVD shown in FIG.
In RV3, one input terminal is connected to the output terminal of the decoder, and the other input terminal is connected to, for example, the output terminal of the inverted signal ROUTB of the redundant comparison circuit RDCM0. On the other hand, in the case of a redundant driver, for example, FIG.
In the redundant driver RDRV0 shown in FIG. 7, the input terminal receives the output signal ROUT and the redundant enable signal RENB of the redundant comparison circuit RDCM0.

The redundancy comparators RDCM0 to RDCMn compare the input address data A0 to An with the redundancy address data RA0 to RAn from the fuse circuit 50. If both address data match, the redundancy comparators RDCMx Thus, for example, a high-level redundant signal ROUT is output, and the output terminal of the inverted signal ROUTB is kept at a low level. In response, the driver controlled by the output signal of the redundancy comparison circuit RDCMx holds the output signal at a low level, and the normal word line driven thereby is also held at a low level. In the redundancy driver controlled by the output signal of the redundancy comparison circuit RDCMx, the output signal is held at a high level, so that the redundancy word line is driven to a high level. That is, when the input address signal matches the redundant address signal from the fuse circuit 50, the access to the normal memory cell is stopped, and the access to the redundant memory cell specified by the address registration is performed instead.

FIG. 5 is a circuit diagram showing a configuration example of the fuse circuit 50. Note that, as described above, the fuse circuit 50
Are arranged separately from the memory core, and specify a redundant address by address registration. As shown, the fuse circuit 50 of the present example includes address data A0,
A1 and redundant address data A0R and A1R are specified. In the actual fuse circuit 50, a plurality of fuses are arranged according to the number of bits of the address of the memory core.

One terminal of the fuse H0 is connected to the power supply voltage V _CC.
And the other terminal is connected to the node NDH0. The drain of the nMOS transistor NT0 is connected to the node NDH0, and the gate of the nMOS transistor NT0 is a reset signal R.
It is connected to the input terminal of ESET, and the source is grounded. The input terminal of the inverter INVL4 is connected to the node NDH0.
, The output terminal is connected to the input terminal of the inverter INVL3, and the output terminal of the inverter INVL3 is connected to the node NDH0. That is, the inverter INV
L3 and INVL4 form a latch circuit, the potential of the node NDH0 is latched by this latch circuit, and a latch signal is output as address data A0.

One terminal of the fuse HOR is connected to the power supply voltage V
Connected to the _CC supply line and the other terminal is connected to the node NDH0R
It is connected to the. The drain of the nMOS transistor NT0R is connected to the node NDH0R, the gate is connected to the input terminal of the reset signal RESET, and the source is grounded. The input terminal of the inverter INVL6 is connected to the node NDH0R, and the output terminal is connected to the inverter INVL.
5, and the output terminal of the inverter INVL5 is connected to the node NDH0R. That is, a latch circuit is formed by the inverters INVL5 and INVL6, and the potential of the node NDH0R is latched by the latch circuit. The latch signal is output as address data A0R, for example, to a redundancy comparison circuit.

As in the above-described portion, the fuses H1, H
1R, nMOS transistors NT1 and NT1R and inverters INVL7, INVL8, INVL9, INV
The address data A1,
An A1R generation circuit is configured.

At the time of circuit reset, a reset signal RESE
T is held at a high level for a short time. Accordingly, nMOS transistors NT0, NT0R, N
T1, NT1R and the like are kept conductive, and the node ND
H0, NDH0R, NDH1, NDH1R and the like are set to low level. After reset operation, reset signal RE
SET is switched to the low level, and the nMOS transistors NT0, NT0R, NT1, NT1R and the like are kept in a non-conductive state. The states of the fuses H0, H0R, H1, and H1R are set by programming with a laser or the like. When the fuse is blown, the potential of the corresponding node is latched by the latch circuit, and the low level at the time of reset is maintained. On the other hand, if the fuse is not blown, the potential of the node corresponding thereto are held at the power supply voltage V _CC level, its level is latched by the latch circuit. As described above, the address registration is performed by programming, and the registered address is output from the fuse circuit 50. Since the address registration is performed in accordance with the position of the detected defective memory cell, after the address registration, when the access to the defective memory cell is specified by the input address, the access to the redundant memory cell instead of the defective memory cell is performed. Then, relief of the defective memory cell is performed.

FIG. 6 shows a plurality of bits of address data A0,
A1,..., An and redundant address data A0R, A1R,
FIG. 9 is a circuit diagram showing a configuration example of a redundancy comparison circuit for comparing with .AnR. The redundancy comparison circuit of FIG. 6 is obtained by extending the number of bits to the redundancy comparison circuit RDCMx shown in FIG. As shown, the address comparison circuit includes exclusive OR gates EXOR0, EXOR1,.
ORn, AND gate AND4, inverter INV
It is composed of O3. Address data A0 and redundant address data A0R are respectively input to the input terminals of the exclusive OR gate EXOR0, and address data A1 and redundant address data A1R are respectively input to the input terminals of the exclusive OR gate EXOR1.
Further, address data An and redundant address data AnR are input to input terminals of the exclusive OR gate EXORn. The output signals of the exclusive OR gates EXOR0, EXOR1,..., EXORn are input to the AND gate AND4. Further, the redundancy enable signal RENB is also input to the AND gate AND4. The output terminal of the AND gate AND4 is connected to the redundant signal ROU.
T is connected to the output terminal of the
And the output terminal of the inverter INVO3 is connected to the output terminal of the redundant inversion signal ROUTB.

The input address data A0, A1,..., An and the redundant address data A0R, A1R,..., AnR are compared by the redundancy comparison circuit shown in FIG. For example, a high-level redundant signal ROUT is output, and its inverted signal RO is output.
The output terminal of UTB is held at low level. On the other hand, if they do not match, the redundancy comparison circuit outputs, for example, a low-level redundancy signal ROUT, and the output terminal of the inverted signal ROUTB is kept at a high level. According to the comparison result of the redundancy comparison circuit, either the driver or the redundancy driver is set to the operation state, and the normal memory cell or the redundant memory cell is accessed.

FIG. 7 is a timing chart showing the operation of the memory circuit of this embodiment. As shown, the output of the buffer is set according to the input address data A0, A1,..., An, and the output signal of the predecoder is set. The output of the redundant comparison circuit is determined according to the comparison between the input address data and the registered address data output by the fuse circuit 50, and the output signal of the driver or the redundant driver is determined accordingly.

As described above, according to this embodiment,
AS composed of a logic circuit 20 and memory cores 30a and 40a
In the IC 10a, by disposing the common fuse circuit 50 of the memory cores 30a and 40a at a specific position on the substrate separately from the memory core, it is possible to reduce the time for blowing the fuse in the redundant operation, and to make the redundancy program versatile. And the time required to create and verify the program can be reduced.

[0045]

As described above, according to the semiconductor device of the present invention, the fuse for the memory redundancy processing is separated from the memory core and arranged at a specific position, so that the time required to blow the fuse in the redundancy operation is reduced. This has the advantage that the versatility of the redundancy program can be improved, the time for creating and verifying the program can be shortened, and the productivity can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor device according to the present invention.

FIG. 2 is a circuit diagram of a memory circuit including a redundant circuit.

FIG. 3 is a circuit diagram of an address buffer and a predecoder.

FIG. 4 is a circuit diagram of a redundant comparison circuit, a driver, or a redundant driver.

FIG. 5 is a circuit diagram of a fuse circuit.

FIG. 6 is a circuit diagram of a redundant comparison circuit.

FIG. 7 is an operation timing chart of the memory circuit;

FIG. 8 is a layout diagram of a conventional semiconductor device.

FIG. 9 is a circuit diagram of a memory circuit in a conventional semiconductor device.

FIG. 10 is a circuit diagram of a conventional redundant circuit.

FIG. 11 is an operation timing chart of a conventional memory circuit.

[Description of Signs] 10 ... ASIC, 20 ... Logic circuit, 30, 30a, 4
0, 40a: memory core, 50: fuse circuit, ADR
BUF0, ADRBUF1,..., ADRBUFn... Address buffer, PRDEC0, PRDEC1,.
DECn... Predecoder, DEC0, DEC1,.
ECm: decoder, RDC0, RDC1,..., RDCn
... redundant circuit, DRV0, DRV1, ..., DRVm ... driver, RDRV0, RDRV1, ..., RDRVn ... redundant driver, RDCM0, RDCM1, ..., RDCM
n ... redundant comparison circuit, V _CC ... power supply voltage, GND ... ground potential.

Claims (5)

[Claims] 1. A semiconductor device having at least one memory cell, comprising: a redundant memory circuit having a redundant memory cell replacing a defective memory cell in the memory circuit; and accessing the defective memory cell by the redundant memory cell. Switching control means for switching to the memory circuit, wherein the switching control means is separated from the memory circuit,
A semiconductor device arranged in a predetermined area on a substrate. 2. The semiconductor device according to claim 1, wherein said memory circuit is disposed on a substrate with priority given to circuit characteristics and chip area. 3. The semiconductor device according to claim 1, wherein said switching control means comprises a fuse, and an address of said defective memory cell to be replaced is specified by address registration. 4. The semiconductor device according to claim 3, wherein said address registration is performed by blowing said fuse. 5. The semiconductor device according to claim 4, wherein the fuse is blown by irradiating a laser beam.