JPH1028112A - Clock selection type synchronizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock selection type synchronizing circuit in which fluctu ation of the cycle of a synchronizing clock can be compensated by a simple means in operating synchronization by selecting any one of plural different synchronizing clocks in a synchronizing circuit formed on an integrated circuit. SOLUTION: A first synchronizing clock (c) is introduced and frequency- divided, and a second synchronizing clock is prepared and transmitted. A selection signal (s) for designating the selection of either the first synchronizing clock (c) or the second synchronizing clock is introduced, and any one is transmitted by operating a switch. Also, a synchronizing circuit 100 operates two frequency-division by a two stage shift register circuit constituted of ore- and post-stages, and a frequency-divider circuit 1 operates it by a binary counter. Also, the selection signal (s) is prepared by selective connection with a ground circuit or a power source circuit by wiring on a substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization circuit formed on an integrated circuit, and more particularly to a clock selection type synchronization circuit for selecting one of a plurality of different synchronization clocks for synchronization. In particular, the present invention relates to a clock-selection type synchronization circuit that can compensate for a change in the period of a synchronous clock even if the change occurs by an easy means.

[0002]

2. Description of the Related Art Conventionally, a synchronizing circuit formed by printed wiring on an integrated circuit (IC), which introduces an asynchronous signal, synchronizes with a synchronous clock, and sends it out, generally includes a flip-flop circuit (hereinafter abbreviated as "abbreviated"). FF). Since the FF has a plurality of circuit elements internally in multiple stages, it needs a setup / hold period for maintaining its state when performing its own set operation by inputting an asynchronous signal.

[0003] Therefore, when the length of the asynchronous signal is less than the setup hold period, a metastable state, which is an unstable transition period, is generated in the FF, and the setup / hold period is reduced.
Compared to the case where the hold period is satisfied, the output is logic 1
Alternatively, it takes a long time to determine the logic 0 (hereinafter, abbreviated to “H” or “L”, respectively). Therefore, it is important to satisfy the setup and hold period and eliminate the metastable state, and various clock selection type synchronization circuits for this purpose have been proposed.

FIG. 4 shows a first example of a shift register circuit.
FIG. 9 is a diagram illustrating a configuration of a conventional example. In the first conventional example shown in FIG. 4, the synchronization circuit 100 is configured by a shift register circuit having two stages of FF1 and FF2 including a front stage and a rear stage. That is, the asynchronous signal D is introduced into the preceding FF1, the output signal Q1 is set by the synchronous clock C, the output signal Q1 is subsequently introduced into the subsequent FF2, and the output signal Q2 synchronized by the next synchronous clock C is outputted. Is sent out.

Accordingly, the frequency of the synchronous clock is increased to increase the speed of the synchronous circuit 100, thereby improving the related system performance. But,
The period of the synchronous clock C is limited due to restrictions on the setup and hold periods of the FF1 and FF2.

FIG. 5 is a diagram for explaining the operation of the first conventional example in FIG. The first synchronous clock C shown in FIG.
However, if the setup / hold period in the preceding stage FF1 cannot be satisfied, the output signal Q1 is in a metastable state, and the period until the determination is significantly longer than the normal delay period. However, if the asynchronous signal D continues to exist in the next synchronous clock C and the predetermined necessary conditions can be sufficiently satisfied, the FF in the subsequent stage
2 can be determined in a stable state (T1).
The duty of the synchronous clock C is assumed to be 50%.

[0007] The predetermined necessary condition is that the period up to determination sufficiently satisfies the setup / hold period in the subsequent FF2 after the lapse, and both periods fall within one cycle of the synchronous clock. . In other words, in order for the entire synchronizing circuit 100 to operate normally, it is necessary that the setup-hold period and the period up to determination satisfy the following expression in the FF2 at the subsequent stage. One cycle of synchronous clock ≥ period until confirmation + setup and hold period ... formula

In actuality, not only the period of the synchronous clock is limited as described above, but the speed of the synchronous clock is unavoidably increased due to factors such as a case where the speed is inevitably increased to the limit and an operation mode due to the system configuration. Characteristics may fluctuate. If the pulse width is shortened for some reason, the period until the determination in the subsequent FF2 may exceed the pulse width.

Therefore, in that case, the output signal Q1 is transmitted to the subsequent FF2 in the metastable state. That is, since the output signal Q2 cannot be determined to be in a stable state because the input signal cannot be a normal input signal in the subsequent FF2 (T2), the entire synchronization circuit 100 cannot operate normally and stable synchronization can be performed. It cannot be done and some improvement is required.

[0010] As an improvement measure against such a variation in the characteristics of the synchronous clock, for example, the FF 1 in the preceding stage may be replaced with a high-speed one so that the meta-stable state can be recovered in a short time.

[0011] Alternatively, two types of different synchronous clocks can be used together, and one of them is selectively supplied externally, as disclosed in Japanese Patent Application Laid-Open No. Sho 59-153225. Japanese Patent Application Laid-Open No. 63-64426 discloses a circuit in which a circuit for changing the response characteristic of the synchronization circuit 100 according to the operating state is added.

[0012]

However, when the conventional clock-selection type synchronizing circuit is used to cope with the fluctuation of the period of the synchronous clock, there are the following problems. First, in a synchronization circuit integrated on an IC, replacing the FF itself, which is a basic circuit element, often involves a drastic change in working steps in the manufacturing process of this IC. Absent.

Second, it is no longer an internal operation of the synchronization circuit on the IC substrate to make a change to separately introduce a clock different from the supplied synchronization clock from the outside. The purpose is different.

Third, additional circuits for detecting the operating state and changing the response characteristics of the synchronization circuit are sufficiently complicated, and precious space on the IC substrate is largely wasted.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a synchronization circuit formed on an integrated circuit performs synchronization by selecting one of a plurality of different synchronization clocks. In this case, it is an object of the present invention to provide a clock selection type synchronization circuit which can compensate for the fluctuation by a simple means even if the fluctuation of the period of the synchronous clock occurs.

[0016]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a clock-selection type synchronizing circuit according to the present invention comprises a synchronizing circuit for introducing an asynchronous signal, synchronizing with a synchronous clock, and transmitting the same. Any one of the clocks
In a clock selection type synchronization circuit for selecting and introducing two synchronization clocks and performing synchronization, a first synchronization clock is introduced and frequency division is performed, and a second synchronization clock is formed from the first synchronization clock. The dividing circuit to be transmitted and these first
A selection signal for designating the selection of the synchronous clock or the second synchronous clock is introduced, and a switching circuit is provided which switches according to the selection signal and sends one of them to the synchronization circuit.

According to this synchronizing circuit, the first synchronizing clock is derived and divided by the frequency dividing circuit, and the second synchronizing clock is formed and transmitted from the first synchronizing clock. , A first synchronizing clock, a second synchronizing clock and a selection signal are introduced, and switching is performed by this selection signal, and one of them is sent to the synchronization circuit.

According to a second aspect of the present invention, in the clock selection type synchronization circuit, the synchronization circuit is constituted by a two-stage shift register circuit including a preceding stage and a following stage. According to this synchronization circuit, the selected synchronization clock is introduced into the synchronization circuit including the two-stage shift register circuit.

In a third aspect of the present invention, the clock selection type synchronization circuit is configured so that the frequency division circuit divides the frequency by two using a binary counter. According to this synchronization circuit, the frequency of the synchronization clock is divided by two by the frequency division circuit including the binary counter.

A clock-selectable synchronization circuit according to a fourth aspect of the present invention has a configuration in which the selection signal is selectively connected to a ground circuit or a power supply circuit by wiring on a substrate. According to this synchronization circuit, the selection signal is selectively connected to the ground circuit or the power supply circuit by the wiring on the substrate and formed.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. In addition, each part denoted by the same reference numeral as the conventional example is a part having the same function, and detailed description is omitted. FIG. 1 is a diagram schematically illustrating a configuration of an embodiment of the present invention. This embodiment is the same as the conventional example in FIG. 4 except that a frequency dividing circuit 1 for dividing the frequency of a synchronous clock and a switching circuit 2 for switching a plurality of synchronous clocks are provided at the synchronous clock input of the synchronous circuit 100. It is.

The frequency dividing circuit 1 performs frequency division by introducing a first synchronous clock, and forms and transmits a second synchronous clock from the first synchronous clock. The switching circuit 2 switches between the first synchronous clock and the second synchronous clock and sends either one to the synchronization circuit 100.

FIG. 2 is a diagram specifically explaining each part in FIG. The frequency dividing circuit 1 shown in FIG. 2 uses an FF having a negative output NotQ, and uses this negative output NotQ.
Q is connected to an asynchronous input D, and a binary counter is formed to divide the synchronous clock C by two. Also, this F
F includes two FF1 and FF in the synchronization circuit 100.
The use of the same type as that of No. 2 can limit the types of circuit elements and avoid unnecessary overhead in design and manufacturing. It should be noted that the synchronization circuit 100 has a 2
This is a stage shift register circuit, which is the same as the conventional example in FIG.

The switching circuit 2 is a selector having two inputs and one output. The switching circuit 2 introduces the first synchronous clock C to the A input and the second synchronous clock C 'to the B input. A selection signal S for specifying the selection of the synchronous clock C ′ is introduced to the S input, and the first or second synchronous clock C, C ′ is switched by the selection signal S. First
The synchronous clock C is the original synchronous clock C introduced from the outside into the frequency dividing circuit 1, and the second synchronous clock C 'is obtained by dividing the synchronous clock C by 2 and the selection signal S Is "L", the first synchronous clock C
In the case of “H”, the second synchronous clock C ′ is selected and sent out from the Y output of the switching circuit 2.

Next, the operation of this embodiment will be described. FIG. 3 is a diagram for explaining the operation of each part in FIG. The first synchronous clock C shown in FIG. 3 is divided by 2 by the frequency divider 1 to obtain a second synchronous clock C ′. Since the selection signal S is “L” in the initial state, the first synchronization clock C is supplied to the synchronization circuit 100. When the asynchronous signal D is introduced into the synchronization circuit 100, the synchronization is performed by the first synchronization clock C.
If the setup and hold period is not satisfied, normal synchronization is not performed as in the conventional example in FIG. 4 (T2).

Next, when the selection signal S is set to "H", the synchronization circuit 100 is supplied with the second synchronization clock C ', and the period up to the determination and the setup / hold period are the first second synchronization clock C'. ′, The setup and hold period in the preceding FF1 is satisfied, and the metastable state can be sufficiently recovered from the metastable state to a stable state (T3). Normally performed by the synchronous clock C ′ (T
4).

Here, the selection signal S may be supplied at any time, for example, by a software command through an input / output port, or by an external hardware designation through a lead terminal on the IC. . In addition, if the ground circuit or the power supply circuit is selectively connected and formed by the wiring on the substrate so as to be supplied, for example, as adjustment of the synchronization circuit 100 based on the inspection result in the shipment inspection at the factory, The first synchronous clock C of the same cycle,
Alternatively, the second synchronous clock C 'having a double period can be selected and created as needed.

It should be noted that the present invention is not limited only to the above-described embodiment, and it goes without saying that various changes can be made without departing from the spirit of the present invention.

[0029]

As described above, the clock selection type synchronization circuit according to the present invention has the following effects. First, since a frequency dividing circuit and a switching circuit previously integrated on an IC are provided and the period of the synchronous clock can be arbitrarily specified by a selection signal, the synchronous circuit is a basic circuit element. There is no need to replace the FF itself, and there is no difficult change in the working steps in the manufacturing process of this IC.

Second, the frequency dividing circuit is a binary counter composed of one flip-flop, and the switching circuit is a simple selector, and the consumption of valuable space on the IC substrate by providing an additional circuit is minimized. Can be minimized.

Third, since the period of the synchronous clock is only extended by two clocks by using a frequency dividing circuit of divide-by-2,
It is the same as operating in the next cycle of the original synchronous clock, and the most efficient alternative synchronous clock can be used.

Fourth, since the designation function of the selection signal is built on the IC substrate and can be designated by software or hardware, it is optimized by an internally completed operation without any external change in the system. A simple synchronization circuit can be realized.

Therefore, in a synchronization circuit formed on an integrated circuit, any one of a plurality of different synchronization clocks is used.
It is possible to provide a clock-selection type synchronization circuit that can compensate for the variation by a simple means even if the period of the synchronization clock fluctuates when performing synchronization by selecting one.

[Brief description of the drawings]

FIG. 1 is a diagram schematically illustrating a configuration of an embodiment according to the present invention.

FIG. 2 is a diagram specifically explaining each part in FIG. 1;

FIG. 3 is a diagram for explaining the operation of each part in FIG. 2;

FIG. 4 is a diagram illustrating a configuration of a first conventional example including a shift register circuit.

FIG. 5 is a diagram for explaining the operation of the first conventional example in FIG. 4;

[Explanation of symbols]

 1 frequency dividing circuit 2 switching circuit 100 synchronization circuit C 1st synchronous clock C '2nd synchronous clock D asynchronous signal S selection signal

Claims (4)

[Claims] 1. A clock selector for selecting and introducing any one of a plurality of different synchronous clocks to a synchronization circuit for introducing an asynchronous signal, synchronizing with a synchronous clock and transmitting the synchronized signal, and performing synchronization. A first synchronizing clock, a first synchronizing clock, a frequency dividing circuit for generating a second synchronizing clock from the first synchronizing clock, and transmitting the second synchronizing clock; A clock-selection type synchronization circuit, comprising: a switching circuit that introduces a selection signal designating clock selection, performs switching based on the selection signal, and sends one of them to a synchronization circuit. 2. The clock selection type synchronization circuit according to claim 1, wherein said synchronization circuit is a two-stage shift register circuit comprising a preceding stage and a following stage. 3. The dividing circuit according to claim 1, wherein the dividing circuit comprises a binary counter.
2. The clock-selection-type synchronization circuit according to claim 1, which performs frequency division. 4. The clock selection type synchronization circuit according to claim 1, wherein the selection signal is formed by selectively connecting a ground circuit or a power supply circuit with a wiring on a substrate.