JPH10275477A - Static ram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a static RAM in which high speed and continuous access operation can be performed. SOLUTION: This RAM has plural memory mats MAT0-MAT3 in which plural static type memory cells are arranged in a matrix state at intersecting points of plural word lines and plural complementary data line, receives an address signal taken in an address register, selects a memory cell of a specific memory mat out of plural memory mats by an address selecting circuit, connects it to sense amplifiers SA0-SA3 or a write-amplifier provided corresponding to each memory mat, while generates an address signal corresponding to an address signal selecting a specific memory mat by an address counter. And when a burst mode is specified by a control signal, a memory cell of a memory mat of 1 is selected by an address signal taken in an address register and connected to a corresponding sense amplifier or a write-amplifier, successively, a memory cell of the other memory mat is selected conforming to an address signal formed by an address counter, and connected to a corresponding sense amplifier or a write-amplifier.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory, and more particularly to a static RAM (random access memory), and more particularly to a technique effective for a burst memory access technique synchronized with a clock signal.

[0002]

2. Description of the Related Art In a RAM having a memory array in which a plurality of memory cells are arranged in a matrix form at intersections of a plurality of word lines and a plurality of data lines, when one word line is selected, the word line is selected. Are selected, and the selected memory cells are connected to the corresponding data lines. Thereby, stored information from a plurality of memory cells corresponding to the selected word line is obtained for the plurality of data lines. By utilizing this, stored information can be continuously read from a plurality of memory cells by simply switching the data lines among the plurality of data lines. As described above, there is a static RAM in which continuous reading or continuous writing from a plurality of memory cells is performed by switching data lines, in other words, by switching column switches.

[0003]

The above static type R
In the AM, it has been found that when the speed of continuous reading or continuous writing is further increased, the following problem occurs. In other words, it is conceivable that the speed can be increased by switching the column switches as described above. However, at the time of switching, multiple selection of the column switches (Y switches) occurs, and for example, after reading 0 data, the opposite 1 When data is read, it is necessary to change the potential of the common data line to the opposite level (from the potential representing 0 data to the potential representing 1 data), which takes a longer time, and the sense amplifier starts an amplification operation. Sometimes, the previous 0 data is amplified or an input signal level required for the sensing operation cannot be obtained, resulting in erroneous reading.

An object of the present invention is to provide a static RAM capable of performing a high-speed continuous access operation. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. The static RAM includes a plurality of memory mats, a plurality of common data line pairs provided corresponding to each memory mat, and a plurality of sense circuits connected to each common data line pair in a one-to-one relationship. And a plurality of common data line pair precharge circuits connected to each common data line pair, and data lines are continuously output from different memory mats.

Each has a plurality of memory mats each having a plurality of word lines and a plurality of data lines, and a plurality of static memory cells connected to the word lines and the data lines. Upon receiving the signal, a memory cell of a specific memory mat among the plurality of memory mats is selected by an address selection circuit and connected to a sense amplifier or a write amplifier provided corresponding to each memory mat. An address signal corresponding to an address signal for selecting a specific memory mat among the memory mats is generated by an address counter, and when a burst mode is designated by a control signal, 1 is determined by the address signal taken into the address register. Select a memory cell of a memory mat and select a corresponding sense amplifier or Connected to Itoanpu, then it is connected to a sense amplifier or write amplifier corresponding to selected memory cells of another memory mat in accordance with the address signal generated by the address counter.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing a main part of an embodiment of a static RAM according to the present invention. Each circuit block shown in the figure is formed on one semiconductor substrate by a known semiconductor integrated circuit technology. In this embodiment, although not particularly limited, in order to realize a burst mode of up to four cycles, one memory array is
It is divided into two memory mats MAT0 to MAT3.

The word lines of each of the memory mats MAT0 to MAT3 are represented by W0 to W0 shown as representatives in FIG.
Like the W3, the selection is made by a word line driver unit which receives the selection signal supplied from the main word line and the decode signals 00 to 11 of the address signals A0 and A1 for selecting each of the memory mats MAT0 to MAT3. The main word line is formed by an X decoder XDEC. The X decoder XDEC is provided commonly to the four memory mats MAT0 to MAT3, and forms a selection signal for a main word line formed to penetrate the four memory mats MAT0 to MAT3.

A complementary data line of each of the memory mats MAT0 to MAT3 is connected to a Y selection circuit (column switch) YSW.
0 to YSW3, the memory mat MA
They are connected to sense amplifiers SA0 to SA3 provided in one-to-one correspondence with T0 to MAT3. The Y selection circuit YS
W0 to YSW3 select the corresponding complementary data lines according to the Y selection signal formed by the Y decoder YDEC, and connect them to the sense amplifiers SA0 to SA3.

In FIG. 1, the readout system circuit is shown as a representative in order to avoid complicating the drawing. That is, the sense amplifiers SA0 to SA3
The memory corresponding to the memory mat selected by selecting the word line is selectively activated according to a timing signal of a sense amplifier (not shown), and the output signal of the activated sense amplifier is supplied to each of the sense amplifiers. SA0
Output register OUT commonly provided for.
It is conveyed to R.

The write system circuit includes an input register INR shown in a block diagram to be described later, and a write amplifier receiving an output signal of the input register. The write amplifiers include the sense amplifiers SA0 to SA3.
The memory mats MAT0 to MAT3 are provided in a one-to-one correspondence with the memory mats MAT0 to MAT3, and the memory mats corresponding to the selected memory mats similarly to the sense amplifiers are selectively activated according to a timing signal of a write amplifier (not shown). The write signal of the input register INR is written into the selected memory cell of the corresponding memory mat.

For an alternative operation (selection operation) of the sense amplifiers SA0 to SA3 and the write amplifier, an address signal A0 for forming a selection signal for selecting a predetermined memory mat from the memory mats MAT0 to MAT3. And A1 obtained by decoding A1 and A1 are used. Actually, an activation timing signal (not shown) common to the four sense amplifiers and an activation timing signal (not shown) common to the four write amplifiers, A signal obtained by performing logical processing with the decode signal is transmitted to the sense amplifiers SA0 to SA3 and the write amplifier.

In the figure, in order to avoid complication of the drawing,
The above logic processing and detailed signal wiring are omitted. In this case, if a plurality of memory cells are simultaneously selected from one memory mat, sense amplifiers and write amplifiers corresponding to the number of bits are provided, and memory access is performed in units of a plurality of bits.

FIG. 2 is a timing chart for explaining a burst read operation of the static RAM according to the present invention. Static RA of this embodiment
In M, the memory operation is performed in synchronization with the clock signal CLK as described later. An address counter, which will be described later, is provided to realize a burst operation. Address signals for the second and subsequent cycles are generated by the address counter.

When the burst read mode is instructed by a chip select signal, a write enable signal, etc., not shown, or a low level of the control signal ADSC, the external address signal A is taken in in synchronization with the clock signal CLK inputted at that time. Then, by decoding the address signal A, the word line W0 of the first memory mat MAT0 is selected. The word line W0 is selected at a high level after the decoding time of the address signal A, and is selected over the next clock signal CLK.

As a result, the storage information of the memory cell is read out to the complementary data line of the memory mat MAT0, and transmitted to the input of the sense amplifier SA0 through the Y selection circuit YSW0. Since it takes time before the information stored in the memory cell is transmitted to the input of the sense amplifier, the sense amplifier SA0 is activated with a delay of one clock with respect to the operation of selecting the word line W0 to form the output signal S (A). . The signal S (A) is transmitted to the output register OUTR with a further delay of one clock, and is output as a read signal DQ (A).

In parallel with the operation of selecting the word line W0, 2
The address counter increments the address signal in synchronization with the clock signal CLK to generate an A + 1 internal address signal. Therefore, in the address selection circuit, the memory mat M is synchronized with the third clock signal CLK.
A memory mat MAT1 is used instead of the word line W0 of AT0.
Is selected. Hereinafter, similarly, the selection of the word lines W2 and W3 of the memory mats MAT2 and MAT3 is sequentially performed, and the sense amplifiers SA1, SA2 and SA are delayed by one clock with respect to the selection of each word line.
3 are activated, and output signals DQ (A + 1), DQ (A + 2) and DQ (A
+3) are sequentially output. Therefore, six cycles of the clock signal CLK are consumed for the above-described four-cycle burst read, and the signal ADSC for the next burst read is set to the low level in the seventh cycle.

In this embodiment, the word lines W0 to W0
1, switching from word line W1 to W2,
At the time of switching from the word line W2 to the word line W3, a state occurs in which a plurality of word lines are selected at the same time, as indicated by hatching in FIG. However, the word line W0
To W3 are separate memory mats MAT0 to MAT, respectively.
Since the word line is T3, the memory cells are not double-selected. Then, the sense amplifiers SA0 to SA0
Since SA3 is also provided in one-to-one correspondence with each of the memory mats MAT0 to MAT3, no signal competition occurs here.

FIG. 3 is a timing chart of a burst operation for explaining the present invention. To facilitate understanding of the present invention, FIG. 3A shows a Y switching system in which one word line is selected and the Y selection circuit is switched, and FIG. 3B shows the present invention. The X switching method by switching the memory mat is shown.

As shown in FIG. 3A, when the word line is set to the selected state and the selection signal YSW of the Y selection circuit is switched during the same cycle of the clock signal CLK, the selected state is inevitably changed from the selected state. A double-selection state occurs as indicated by hatching in the figure between the column switch that switches to the non-selection state and the column switch that switches from the non-selection state to the selection state. Then, a read signal from the selected complementary data line is transmitted through the Y selection circuit (column switch), and the common data line
When the previous read signal is 0 data (“0” Data) and the next read signal is 1 data (“1” Data), the signal inversion timing is delayed, and the signal is still sufficient at the sense amplifier activation timing. Erroneous reading occurs without obtaining the level. For this reason, in the above-mentioned Y switching method, if the pipeline operation is performed in synchronization with the clock signal CLK, the switching of the Y selection circuit in one clock cycle cannot be performed, and the burst operation becomes slow. Problem.

On the other hand, as shown in FIG. 3B, in the X switching system by switching memory mats, even if double selection occurs in switching between word lines W0 and W1,
The word lines of the memory mats MAT0 and MAT1 different from each other are double-selected, and can be switched without any problem. Since a Y selection circuit and a sense amplifier are provided in one-to-one correspondence with the memory mats MAT0 and MAT1, and are electrically isolated from each other, there is no competition for read data, and the sense amplifiers SA0 and SA1 are respectively A read signal such as 0 data (“0” Data) or 1 data (“1” Data) is obtained from the state in which the common data line is precharged, and the memory mats MAT0 and MAT1 are obtained.
Can be accurately read by the activation signal of the sense amplifier corresponding to the selection timing.

FIG. 4 is a timing chart for explaining the burst write operation of the static RAM according to the present invention. When the burst write mode is instructed by a low level of a chip select signal, a write enable signal, and the like or a control signal ADSC (not shown), the external address signal A and the write signal Din (A) are synchronized with the clock signal CLK input at that time. The address signal A is decoded in the same manner as in the burst read operation, and the word line W0 of the first memory mat MAT0 is selected. The word line W0 is selected at a high level after the decoding time of the address signal A, and is selected over the next clock signal CLK. Therefore, the write signal Din (A) captured by the input register INR described later is synchronized with the next clock CL in synchronization with the selection timing of the word line W0.
The data is transmitted to the complementary data line of the memory mat MAT0 in synchronization with K, and is written to the selected memory cell.

In parallel with the operation of selecting the word line W0, 2
The address counter increments the address signal in synchronization with the clock signal CLK to generate an A + 1 internal address signal. Therefore, the write signal Din (A +
1) is input in synchronization with the next clock signal CLK, and is taken into the input register INR. Therefore, the address selection circuit provides the third clock signal CL
In synchronization with the word line W0 of the memory mat MAT0.
, The word line W1 of the memory mat MAT1 is selected.

Hereinafter, memory mats MAT2,
The selection of the word lines W2 and W3 of MAT3 is sequentially performed,
The input register IN is synchronized with the selection of each word line.
Write Din (A + 1), Din (A +
2) and Din (A + 3) are connected to the word line W
The data is transmitted to the complementary data lines of the memory mats MAT1, MAR2, and MAT3 in synchronization with the selection timing of 1, W2, and W3, and is written to the selected memory cell. In the last memory mat MAT3, one cycle is spent for the recovery (precharge) of the write signal of the complementary data line, so that six cycles of the clock signal CLK are eventually spent for four cycles of burst write. , 7
Signal ADSC for the next burst read in the cycle
Is set to the low level. As described above, both burst read and burst write with the burst length of 4 can be realized by 6 cycles of the clock signal CLK.

FIG. 5 is an overall block diagram of one embodiment of the static RAM according to the present invention. Each circuit block shown in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. In the figure, a memory array MARY is
In addition to the memory mats MAT0 to MAT3 as described above,
It should be understood that address selection circuits such as X decoders and Y decoders and peripheral circuits such as sense amplifiers SA0 to SA3 and write amplifiers are also included.

Although not particularly limited, a 15-bit address signal such as A0-A14 is input to the address terminal Add, and these address signals are stored in the address register AD.
It is taken into R. Among the address signals A0 to A14 taken into the address register ADR, the address signals A2 to A14 except for the address signals A0 and A1 forming a selection signal for selecting a desired memory mat from the memory mats MAT0 to MAT3 are: The above memory array M
This is supplied to the ARY address selection circuit. The 2-bit address signals A0 and A1 are supplied to one input of an addition circuit including, for example, an exclusive OR circuit. A 2-bit address signal formed by an address counter ADC is supplied to the other input of the adder circuit, and output signals of the adder circuit are supplied to the memory array as A0 and A1.

Each of the memory mats MAT0 to MAT3 of the memory array MARY is not particularly limited, but performs memory access in units of 32 bits. In other words, 32 memory cells are simultaneously selected by the address selection circuit, and memory access is performed in units of 32 bits. Therefore, each of the input register INR and the output register OUTR is composed of 32 bits, and the data terminal Data is composed of 32 lines, and signals D0 to D31 are input / output.

The control circuit CONT includes, but is not limited to, a chip select signal / CE and a write enable signal / W.
E, burst control signal / ADSC and clock signal CL
Receiving K, the operation mode is determined, and a timing signal according to each operation mode is generated. When the burst mode is instructed, the address counter ADC is supplied with a count pulse synchronized with the clock signal CLK and performs the above-described address increment operation.

When the address register ADR is set to the chip selection state by the chip selection signal or the like, the clock signal CLK is supplied to fetch the external address signal Add. Input register INR and output register O
The clock signal CLK is supplied to the UTR, the output register OUTR is activated when the read mode is instructed by the control circuit CONT, and the input register INR is activated when the write mode is instructed. You. In this case, each operation is performed in synchronization with the clock signal CLK.

The burst length may be fixed or may be set by a control signal. Although not particularly limited, the address counter ADC is reset when the chip is selected.
Therefore, when the burst mode is not specified,
The output is 00. Therefore, the output of the adding circuit is the address signal A0 supplied to the address terminal Add.
A0 and A1 of .about.A14 become equal to each other, and are eventually taken into the address register ADR and become the same as the external address signal. Therefore, the signals A0 and A1 generated by the adder circuit as described above cause the memory array MAR
Even if Y is selected, no problem occurs in read / write operations other than the burst mode.

FIG. 6 is a circuit diagram of one embodiment of one memo mat in the static RAM according to the present invention. The memory mat shown in FIG.
A pair of complementary data lines D1, / D1, D2, / D2 and D1
5, / D15 and four word lines WL0 to WL255 are exemplarily shown. In the figure, a P-channel type M
OSFETs are distinguished from N-channel MOSFETs by the addition of arrows to their back gates (channel portions). In addition, / (slash) represents an overbar of a logical symbol having an active level of the inverting side or the low level among complementary data lines composed of non-inverting and inverting. This is the same in FIG.

Memory cells are indicated by black boxes at the intersections of word lines and complementary data lines. The numbers shown in the black boxes represent the X address and the Y address. Although not shown, the memory cell includes a CMOS latch circuit in which the input and output of a pair of CMOS inverter circuits each composed of a P-channel MOSFET and an N-channel MOSFET are cross-connected to each other, and an input / output node of the latch circuit. N-channel type M for address selection provided between memory and data line
It is composed of OSFET. The P-channel MOSFET constituting the CMOS inverter circuit can be replaced with a polysilicon resistor having a high resistance value.

The complementary data lines D0 and / D0 are constantly supplied with the ground potential GND of the circuit at their gates, so that a P-channel type MO acting as a pull-up resistor is provided.
SFETs Q3 and Q4 are provided. The sources of these P-channel MOSFETs Q3, Q4 are connected to the power supply voltage, and perform operations such as pulling up the complementary data lines D0, / D0 to the power supply voltage side. P-channel MOSFETs Q3 and Q4 acting as pull-up resistors
Is designed to allow only a small current to flow by increasing its on-resistance value, thereby reducing the current consumption when selecting a memory cell, and reducing the load on the write amplifier during writing to reduce the complementary data line D0 or /. D0, which is brought to a low level such as the ground potential of the circuit in response to the write signal, acts to speed up the potential change.

The complementary data lines D0 and / D0 have P-channel MOSFETs Q1 and Q2 as loads for reading.
Is provided. P-channel MOSFETs Q1 and Q2
Is turned on by an equalize signal EQ except during a substantial write operation, and the complementary data line D
0, / D0. Further, a P-channel type MOSFE provided between complementary data lines D0 and / D0 is provided.
TQ5 acts as a short-circuit MOSFET during write recovery, and acts as a level limiter of a read signal during the above-described read operation.

That is, when the memory cell selected by the word line selecting operation is connected to the complementary data lines D0 and / D0, the ON-state N-channel MOSFET and the N-channel MOSFET constituting the latch circuit in the memory cell -Type transmission gate MOSFET and the P-channel type MO
The low read level is determined by the conductance ratio of the SFET to the load resistance. At this time, the conductance of the load MOSFET is set relatively large, so that the low level is set to a relatively high level close to the power supply voltage VCC. And the short-circuit MOS
If the low level is going to be lower than the threshold voltage of the FET, the short-circuiting MOSFET is also turned on and acts to limit the low level.

The column switch is connected to the complementary data line D
A so-called CMOS switch circuit in which P-channel MOSFETs Q7 and Q8 and N-channel MOSFETs Q9 and Q10 are connected in parallel between 0, / D0 and the common data lines SCD, / SCD, respectively. The Y selection line YS0 to which the selection signal from the Y decoder YDEC is supplied is connected to the gates of the N-channel MOSFETs Q9 and Q10 provided on the complementary data lines D0 and / D0. The output terminal of the inverter circuit N1 is connected to the gates of the P-channel MOSFETs Q7 and Q8 provided on the complementary data lines D0 and / D0. Thus, when the Y selection line YS0 is set to the high level, the N-channel MOSFETs Q9 and Q10 and the P-channel MOSFETs Q7 and Q8 can be simultaneously turned on.

A total of 16 pairs of complementary data lines D0, / D0 to D15, / D15 provided in one memory mat are provided.
, A total of 16 Y selection lines YS0 to Y
S15 is provided. These Y selection lines YS0 to YS1
No. 5 is arranged in a skewed state with respect to a total of 32 memory blocks including the memory block MB0 shown as an example and the memory block B31 shown by the dotted line. Such a Y selection line does not need to be physically constituted by one continuous wiring. If the selection operation of the column switch is delayed due to a signal delay due to a heavy load on the Y selection line or a long wiring length, a plurality of drivers may be provided.

The common data lines SCD and / SCD are connected to an input terminal of a sense amplifier (not shown) and a write amplifier (not shown). As described above, the memory block is MB
In the case where 32 of 0 to MB31 are provided, 32 pairs of the common data lines SCD and / SCD are also provided, and the sense amplifier and the write amplifier are provided correspondingly.

The memory mats MAT0 to MAT3 divided into four as described above are each composed of a memory block as shown in the embodiment of FIG. When four memory mats MAT0 to MAT3 are provided as in this embodiment, and the word lines are switched to perform burst read or burst write, word lines are not selected in the same memory mat. In addition, contention (competition) of read data or write data on the common data line can be prevented.

Therefore, each operation cycle and the next cycle can be used effectively. Taking a burst read mode as an example, a word line selection operation, a sense amplifier selection operation, and an operation of transmitting the output of a sense amplifier to an output register by effectively utilizing the current operation cycle and the next cycle. Can be. Thus 2
When one clock cycle is used, sufficient word line selection time and data line recovery time after writing can be ensured. Since the multiple selection of the Y selection circuit in the same memory mat does not occur, the common data line potential is always in a precharge state before it is selected, and the reverse data is not amplified when the sense amplifier is activated. In addition, the operation margin of the sense amplifier can be improved. For these reasons, for example, it is possible to increase the speed of the clock signal CLK at 200 MHz or more.

Since the high-speed operation as described above can be performed,
For example, it can be used as a cache memory.
5 as the data memory in the cache memory
Can be used.
The entire cache memory is roughly composed of a cache tag (address array), the cache data memory and the cache controller. An example using such a cache memory will be described later. The cache tag stores a part of an address called an address tag, and the cache data memory stores data corresponding to the address tag stored in the cache tag.

When a part of the address stored in the cache tag matches the corresponding address from the central processing unit CPU, a hit signal is output from the cache tag and the hit signal is selected in parallel. The data read from the cache data memory is taken into the central processing unit CPU. If a miss occurs, the main memory is accessed. In the case where the burst mode as described above is provided, the central processing unit CPU synchronizes with the clock signal CLK,
Bit data can be read and written continuously. Further, in the case of the above-mentioned mishit, it becomes possible to speed up data transfer between the main memory and the above-mentioned data memory.

FIG. 10 is a block diagram showing one embodiment of a computer system using the static RAM according to the present invention. In FIG. 1, a processor serving as a central processing unit includes a controller for controlling a cache memory, a primary cache memory, and a processor core. When a mishit occurs in the primary cache memory, the processor accesses the outside of the processor. Do.

In order to perform access to the outside, etc., the processor uses a data terminal DAT connected to an external CPU bus.
A and the address terminal Add connected to the external address bus
less. In the figure, TAG represents a cache tag, compares the address output to the external address bus with the tag in the cache tag, and transmits the result to the processor. Here, when a cache hit occurs, data from the cache memory is taken into the primary cache memory in the processor. In the case of a mishit, access to the main memory is further performed.

The cache memory shown in FIG.
Although not particularly limited, this embodiment represents a secondary cache memory, which has a data terminal Data connected to the external data bus and an address terminal Address connected to the external address bus. In the present embodiment, since the size of the data bus of the processor is 64 bits, two secondary cache memories that access data in 32-bit units are used. The same addresses A0 to A15 are given from the processor to these cache memories, and the cache memory shown on the front side in the figure is connected to the half external buses D0 to D31 of the 64-bit external bus and to the data terminals thereof. Da
ta is connected to the cache memory arranged at the back in FIG.
The data terminal Data is connected to 63.

These cache memories have three chip enable terminals / CE1, / CE2 and CE3, of which two chip enable terminals / CE2.
And CE3 are provided with a predetermined power supply voltage (for example, +
2.5 V) and the ground potential of the circuit.

A clock signal generated by a clock signal generating circuit CLK that operates in synchronization with the processor and the cache memory is supplied to both of them. In addition, the processor forms control signals / ADSC, / CE1, and / WE to control the cache memories and supplies the control signals to these cache memories. In these control signals, control signal / ADSC corresponds to / ADSC in FIG. 5, and control signal / CE1 corresponds to / C in FIG.
E, and the control signal / WE corresponds to / WE in FIG.

Next, an embodiment of the static memory used as the cache memory will be described. This embodiment also has four memory mats as in the embodiment shown in FIG.

FIG. 7 is a circuit diagram showing two of the memory mats MAT0 and MAT1. In the figure, D0, / D0, Dn, / Dn, Dm, / D
m, Dx, / Dx are data lines, for example, D0, / D
0 constitutes a pair of complementary data lines. In the static memory cell M, the input / output terminal is connected to the complementary data line pair, and the selection terminal is connected to the word line. The word line in the memory mat MAT0 is
It is selected and driven by a word line selection circuit WSD0 that receives a selection signal from the main word line and a signal (00) for selecting a memory mat. The word line selection circuit WSD0 in this embodiment includes a two-input NAND (NAND) circuit that receives the selection signal and an inverter that receives the output and supplies a signal to the word line.

Complementary data line pairs D0, / D0, Dn, / D
n is a common data line pair CD via a column switch.
0, / CD0. The column switch can be considered to be composed of a plurality of unit column switches YSW. Since the unit column switch YSW has the same configuration as the column switch shown in FIG. 6, a detailed description thereof will be omitted. A precharge circuit is provided for the common data line pair CD0 and / CD0. This precharge circuit includes a P-channel type MO connected between a power supply voltage node and a common data line.
It has SFETs QP1 and QP2 and a P-channel type MOSFET QP3 for equalizing between a pair of common data lines, and has a common data line precharge signal CDEQB.

By setting [00] to low level, the common data line pair is precharged and equalized.

The common data line precharge signal CD
EQB

[00] is formed by the precharge control circuit PC0. Precharge control circuit PC0 has a NAND circuit for receiving an inverted signal of memory mat select signal (00) assigned to memory mat MAT0 and a common data line recovery signal, and assigned memory mat select signal (00). , The low level common data line precharge signal CDEQB when the recovery signal indicates the precharging of the common data line,

[00] is formed.

An activation signal from the column switch selecting circuit CSD0 is supplied to each of the unit column switches YSW constituting the column switches. The column switch selection circuit CSD0 receives an upper address of a column address (Y address) and a memory mat selection signal (00) assigned to this memory mat, and when the memory mat MAT0 is selected, the column switch Is selected, and one unit column switch YSW is selected from the plurality of unit column switches YSW to make it conductive.

An input terminal of a corresponding sense amplifier is connected to the pair of common data lines CD0 and / CD0, and a sense amplifier timing signal SAE

When [00] rises to a high level, the potential difference between the common data line pair is determined, and the determination result is transmitted to the read data bus. The sense amplifier timing signal SAE

[00]
Is formed by a sense amplifier control circuit CSC0 receiving a memory mat select signal (00) assigned to the memory mat MAT0 and a sense amplifier activation signal.

Although there is no particular limitation on the sense amplifier, for example, two inverter circuits are cross-connected, and the common data lines CD0 and / CD0 are connected to the input / output points thereof, so that the two cross-connected inverter circuits are positive. By the feedback operation, the configuration is such that the potential difference between the pair of common data lines CD0 and / CD0 is amplified. In this case, the potential difference between the pair of common data lines CD0 and / CD0 is enlarged by the operation of the sense amplifier.

Regarding the data writing, this embodiment is different from the previous embodiment. That is, write data is supplied to the read data bus via a separate bus. The write data is supplied to a write amplifier provided corresponding to the memory mat MAT0, and complementary data according to the write data is supplied from the write amplifier to the pair of common data lines CD0 and / CD0.

The memory mat MAT0 has been described above, but other memory mats, for example, the memory mat MAT0
1 has the same configuration as the memory mat MAT0. Although a memory mat select signal (00) has been assigned to the memory mat MAT0,
For another memory mat (for example, MAT1), another memory mat selection signal (01 for MAT1) is assigned.

As can be understood from FIG. 7, the memory mat has a one-to-one correspondence with a common data line pair CD, //.
A CD, a common data line precharge circuit, a sense amplifier, and a write amplifier are provided. If you change the perspective, one pair (or one) via a column switch
It can be considered that one memory mat is constituted by the memory cells connected to the common data line. In this case, memory cells connected to different common data lines via column switches are considered to be included in different memory mats.

Next, the operation of the embodiment shown in FIG. 7 will be described with reference to the operation waveform diagrams shown in FIGS. As shown in FIG. 8, according to the clock signal CLK, for example, a column switch (YS) in the memory mat MAT0 is provided.
W) The activation signal changes from a low level to a high level. Similarly, the common data line precharge signal CDEQB in the memory mat MAT0 also changes from a low level to a high level. When the common data line precharge signal CDEQB changes from low level to high level, precharging of the common data lines CD0 and / CD0 is completed, and the column switch activation signal changes from low level to high level. Data of the memory cell is transmitted to common data lines CD0 and / CD0. Thereby, common data lines CD0, / CD0
Changes as shown in FIG.

Thereafter, the sense amplifier activation signal is changed to a high level, thereby amplifying, for example, the potential difference between the common data line pair. Since the mode is the burst read mode, the column switch activation signal in the memory mat MAT1 subsequently changes from a low level to a high level. Similarly, the common data line precharge signal CDEQB in the memory mat MAT1 also changes from a low level to a high level. When the common data line precharge signal CDEQB changes from low level to high level, precharging of the common data lines CD1 and / CD1 is completed, and the column switch activation signal changes from low level to high level. Data of the memory cell is transmitted to common data lines CD1, / CD1. Thereby, the potentials of the common data lines CD1, / CD1 change as shown in FIG.

As can be understood from this figure, when data is read from one memory mat, a precharge operation can be performed on the common data line of another memory mat. A relatively large number of transistors (MOSFETs) are connected to the common data line, and the wiring length is relatively long. Therefore, the parasitic capacitance connected to the common data line becomes relatively large. The increase in the parasitic capacitance increases the time required for the precharge. However, according to the present embodiment, the precharge may be performed during a period in which data is read from another memory mat. On the other hand, if a common data line is shared between a plurality of memory mats, the time allowed for precharging is reduced.

When a common data line is shared among a plurality of memory mats, if the potential of the common data line is lowered according to previously read data, the potential is returned by the precharge operation. Before returning the potential, the next data may be transmitted to the common data line via the column switch. As a result, a malfunction may occur. According to the present embodiment, since the common data line is separated and continuous reading is performed between different memory mats, the above-described malfunction can be prevented.

FIG. 9 shows an operation waveform diagram in the burst read mode. This waveform diagram is similar to the waveform diagram described above with reference to FIG. The operation according to the waveform diagram shown in FIG. 9 will be easily understood from the waveform diagram shown in FIG. 2 and the waveform diagram of FIG. Therefore, detailed description is omitted.

As shown in FIG. 9, the column switch selection signal Y
SWE

[00], YSWE [01], YSWE [1
0] and YSWE [11] are selected at the same time,
Because the common data line is separated, it was previously selected,
Even if data is transmitted to the common data line, no problem occurs. Also, the precharge operation of the common data line
No problem occurs even if the plurality of common data lines overlap.

FIG. 10 is a waveform chart for explaining the burst write mode of this embodiment. This operation waveform diagram is also similar to the waveform diagram of FIG. 4 used in the above description. Therefore, detailed description is omitted. FIG. 10 particularly shows the common data line precharge signal and the potential of the common data line. From this figure, it is easily understood that when data is written to one memory mat, a precharge operation is performed to a common data line corresponding to another memory mat. Would.
Therefore, even if a relatively large parasitic capacitance is connected to the common data line, the precharge operation can be reliably performed.

The operation and effect obtained from the above embodiment are as follows. (1) First and second memory mats each having a plurality of word lines, a plurality of complementary data lines, and a plurality of static memory cells respectively connected to the word lines and the complementary data lines. , A first and a second common data line pair respectively corresponding to the first and the second memory mats and electrically separated from each other, and respective complementary data lines in the first and the second memory mats Are selectively connected to the first and second common data line pairs, respectively.
And a second selection circuit; first and second precharge circuits for precharging the first and second common data line pairs, respectively; and first and second common data line pairs, respectively. By providing the first and second sense circuits, even if a relatively large parasitic capacitance is connected to the common data line, the precharge operation can be reliably performed, and a high-speed and stable read operation is performed. The effect that it can be obtained is obtained.

(2) In the static RAM of (1), a continuous write operation is further provided by further providing first and second write circuits respectively connected to the first and second common data line pairs. The speed can also be increased.

(3) In the static RAM of (1), a bus to which the output from the first sense circuit and the output from the second sense circuit are continuously supplied;
By further providing an output circuit for outputting a signal on the bus, there is an effect that continuous reading can be performed at high speed.

(4) In the static RAM of (3), first and second write circuits respectively connected to the first and second common data line pairs, and the second common data line pair Is further provided with a second write circuit connected to the second circuit, so that an effect that continuous read and write operations can be performed at high speed can be obtained.

(5) In the static RAM of (4), a write bus connected to the first write circuit and the second write circuit, and write data are continuously supplied to the write bus. Providing an input circuit further provides an effect that a continuous writing operation can be further speeded up.

(6) In the static RAM of (1), a first word line selection circuit for selecting a word line in the first memory mat and a second word line for selecting a word line in the second memory mat. By further providing the word line selection circuit, the effect that continuous reading and writing operations can be further accelerated can be obtained.

(7) A memory mat having a plurality of word lines, a plurality of data lines, and a plurality of static memory cells each connected to the word line and the data line, is taken into an address register. Receiving the address signal, a memory cell of a specific memory mat among the plurality of memory mats of the memory array is selected by an address selection circuit and connected to a sense amplifier or a write amplifier provided corresponding to each memory mat. At the same time, an address signal corresponding to an address signal for selecting a specific memory mat of the memory array is generated by an address counter, and when a burst mode is designated by a control signal, one address signal is taken by the address signal taken into the address register. Select the memory cell of the memory mat and select the corresponding sense By connecting to an amplifier or a write amplifier, and subsequently selecting a memory cell of another memory mat in accordance with an address signal formed by the address counter and connecting it to a corresponding sense amplifier or write amplifier, high-speed reading and The effect that high-speed writing becomes possible is obtained.

(8) The above address signal and control signal are fetched in synchronization with the input clock signal.
The operation of selecting a memory cell and the operation of inputting / outputting data are sequentially performed in synchronization with the clock signal in synchronization with the clock signal, so that one operation is performed over two clock cycle periods. In other words, since it is performed in a pipeline system, there is an effect that continuous reading and continuous writing synchronized with the clock signal become possible.

(9) The address signal supplied to the address selection circuit is a signal obtained by adding the address signal fetched into the address register and the address signal generated by the address counter. The burst operation and the memory operation each time can be selectively performed depending on whether the counter is operated or not, and the effect that the circuit can be simplified can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, when the burst mode is performed by switching for each memory mat, the Y selection operation of the memory mat may be performed in synchronization with the word line selection operation. In addition to determining the number of memory mats in accordance with the burst length, for example, when the number of memory mats is four as described above, four or more memory mats can be set. That is, the number of bits of the address counter may be set to a plurality of bits corresponding to the burst length, and the internal address signal corresponding to the burst operation may be generated. In this case, instead of narrowing down one word line corresponding to the four memory mats by the main word line as shown in FIG. 1, a memory mat is selected in accordance with sequentially generated address signals. The address selection circuit may be devised as described above.

In the above embodiment, the word lines are separated for each memory mat. However, the word lines may be shared for a plurality of or all memory mats. For example, FIG.
In the following description, the word lines W0 to W3
, One main word line may be used. In this case, each memory mat MA
The memory cells in T0 to MAT3 are selected. However, if a common data line and a sense amplifier or / and a write amplifier are provided for each memory mat, multiplexing of column switches between the memory mats can be performed. Even if a choice occurs,
Since the potential of the common data line is not changed by data from another memory mat, the operation timing of the sense amplifier can be sped up. However, in this case, it is necessary to keep in mind that the power consumption may increase because a plurality of memory mats are activated almost simultaneously. In this case, it is necessary that the common data line has one-to-one correspondence with the memory mats and is electrically separated from the common data lines corresponding to other memory mats. INDUSTRIAL APPLICABILITY The present invention can be widely used for a static RAM in which data is input and output in synchronization with a clock signal.

[0076]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, it has a memory mat having a plurality of word lines, a plurality of data lines, and a plurality of static memory cells each connected to the word line and the data line, and receives an address signal taken into an address register. A memory cell of a specific memory mat among the plurality of memory mats of the memory array is selected by an address selection circuit and connected to a sense amplifier or a write amplifier provided corresponding to each memory mat; An address signal corresponding to an address signal for selecting a specific memory mat of an array is generated by an address counter, and when a burst mode is designated by a control signal, a memory of one memory mat is designated by an address signal taken into the address register. Select a cell and use the corresponding sense amplifier or By connecting to a write amplifier, and subsequently selecting a memory cell of another memory mat in accordance with an address signal formed by the address counter and connecting the selected memory cell to a corresponding sense amplifier or write amplifier, high-speed reading and high-speed writing are performed. Becomes possible.

[Brief description of the drawings]

FIG. 1 is a main block diagram showing an embodiment of a static RAM according to the present invention.

FIG. 2 is a timing chart for explaining a burst read operation of the static RAM according to the present invention;

FIG. 3 is a timing chart for explaining a burst operation according to the present invention;

FIG. 4 is a timing chart for explaining a burst write operation of the static RAM according to the present invention;

FIG. 5 is an overall block diagram showing an embodiment of a static RAM according to the present invention.

FIG. 6 is a circuit diagram showing one embodiment of one memory mat in the static RAM according to the present invention.

FIG. 7 is a main part circuit diagram showing one embodiment of a static RAM according to the present invention.

FIG. 8 is a waveform chart for explaining a read operation of the present invention.

FIG. 9 is a waveform chart for explaining a burst read operation of the present invention.

FIG. 10 is a waveform chart for explaining a write operation of the present invention.

FIG. 11 is a block diagram of a computer system in which a static RAM according to the present invention is used as a cache memory.

[Explanation of symbols]

MAT0 to MAT3: memory mat, XDEC: X decoder, YDEC: Y decoder, YSW0 to YSW3 ... Y
Selection circuit (column switch), SA0 to SA3: sense amplifier, OUTR: output register, ADR: address register, ADC: address counter, MARY: memory array, INR: input register, CONT: control circuit,
WL0 to WL255: word line, D0, / D0 to D1
5, / D15: complementary data line, SCD, / SCD: common data line, Q1 to Q10: MOSFET, N1: inverter circuit. YSW: unit column switch, M: memory cell, WSD0, WSD1: word line selection circuit, QP1
~ QP3 ... P-channel MOSFET, PC0, PC
1: Precharge circuit, CSD0, CSD1: Column switch selection circuit, CSC0, CSC1: Sense amplifier control circuit, TAG: Cache tag, CLK: Clock signal generation circuit.

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Morita Sadayuki 3-1-1 Higashi Koigakubo, Kokubunji, Tokyo Metropolitan Government Inside Hitachi Ultra LSE Engineering Co., Ltd. 3-1-1, Hitachi Ultra-SII Engineering Co., Ltd. (72) Inventor Haruko Kawauchi 3-1-1, Higashi-Koikekubo, Kokubunji-shi, Tokyo Hitachi Ultra-SII Engineering, Ltd. (72) Inventor Hideharu Yawata 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Kenichi Fukui 5-2-1, Josuihoncho, Kodaira-shi, Tokyo (72) Tomohiro Nagano, Inventor, Semiconductor Division, Hitachi, Ltd. (1) Hitachi Ultra LSE Engineering Co., Ltd. (72) Inventor Masaki Harada 3-1-1 Higashi Koigakubo, Kokubunji-shi, Tokyo Hitachi Ultra LSE Engineering Co., Ltd.

Claims (10)

[Claims] A first memory mat having a plurality of word lines, a plurality of complementary data lines, and a plurality of static memory cells respectively connected to the word lines and the complementary data lines; and a plurality of word lines. A second memory mat having a plurality of complementary data lines, a plurality of static memory cells respectively connected to the word lines and the complementary data lines; a first common data line pair; A second common data line pair electrically separated from the common data line pair, and a first selection for selectively connecting a complementary data line in the first memory mat to the first common data line pair. Circuit, a second selection circuit for selectively connecting a complementary data line in the second memory mat to the second common data line pair, and a second selection circuit for precharging the first common data line pair. A first precharge circuit; a second precharge circuit for precharging the second common data line pair; a first sense circuit connected to the first common data line pair; And a second sense circuit connected to the common data line pair. 2. The static RAM according to claim 1, further comprising: a first write circuit connected to said first common data line pair; and a second write circuit connected to said second common data line pair. And a write circuit.
M. 3. The static RAM according to claim 1, further comprising: a bus to which an output from the first sense circuit and an output from the second sense circuit are continuously supplied; A static type RAM including an output circuit for outputting a signal. 4. The static RAM according to claim 3, further comprising: a first write circuit connected to said first common data line pair; and a second write circuit connected to said second common data line pair. And a write circuit.
M. 5. The static RAM according to claim 4, further comprising: a write bus connected to said first write circuit and said second write circuit; and continuously supplying write data to said write bus. A static R
AM. 6. The static RAM according to claim 1, further comprising: a first word line selection circuit for selecting a word line in said first memory mat; and a second word line for selecting a word line in said second memory mat. A static RAM including two word line selection circuits. 7. A memory array having a plurality of memory mats in which a plurality of static memory cells are arranged in a matrix at intersections of a plurality of word lines and a plurality of complementary data lines, and a specific memory mat of the memory array. An address counter for generating an address signal corresponding to the address signal to be selected; an address register for receiving the input address signal; and an address register for receiving the address signal captured by the address register. An address selection circuit for selecting a memory cell of a specific memory mat, a plurality of sense amplifiers provided corresponding to the plurality of memory mats, receiving a read signal from the selected memory cell, and the selected memory Multiple write-uns that supply write signals to cells And an output circuit provided in common with the plurality of sense amplifiers and an input circuit provided corresponding to the write amplifier; and a control signal supplied from an external terminal to determine an operation mode and perform necessary control. A control circuit for forming a signal, wherein when the burst mode is designated by the control signal,
A memory cell of one memory mat is selected by an address signal taken into the address register and connected to a corresponding sense amplifier or write amplifier, and then a memory of another memory mat is operated in accordance with an address signal generated by the address counter. A static RAM, wherein cells are sequentially selected and connected to corresponding sense amplifiers or write amplifiers. 8. The static RAM according to claim 7, wherein said address signal and control signal are fetched in synchronization with an input clock signal, and a memory cell selecting operation and data are synchronized in synchronization with said clock signal. A static RAM characterized by performing the following input / output operations. 9. The static RAM according to claim 7, wherein the address signal for selecting the memory mat is a part of an address signal for selecting a word line of the memory mat. Static RA
M. 10. The static RAM according to claim 7, wherein the address signal supplied to said address selection circuit is obtained by adding an address signal taken into said address register and an address signal generated by said address counter. A static RAM characterized in that the signal is a static RAM.