JPH10275112A - Cache memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the cache memory system which can be optimized according to a distribution of such data that the time of data transfer from a cache memory to a main storage device needs to be written back. SOLUTION: Relating to the cache memory system 10 equipped with a cache memory 20 provided with dirty bits by subblocks obtained by dividing cache lines and a data writing-back means 30 which writes data stored in the cache lines back to the main storage device 50, the data writing-back means 30 when writing the data stored in the cache lines back refers to a table showing the relation between written-back data sizes and times needed for writing-back operation and also refers to a dirty bit in an on state among dirty bits stored in a dirty bit storage part, thereby determining an optimum combination of subblocks to be written back.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cache memory, and more particularly, to a cache memory employing a write-back method.

[0002]

2. Description of the Related Art Generally, this kind of cache memory is
In an information processing system, for example, it is provided between a central processing unit (hereinafter, referred to as a CPU) and a main storage device, and transfers data to the CPU upon reading from the main storage device and from the CPU to the main storage device. Is used to compensate for a decrease in throughput due to data transfer accompanying the write operation. Such a cache memory utilizes the fact that information handled in an information processing system has temporal locality and spatial locality due to its nature. In such an information processing system, when data to be read and written exists in the cache memory, reading and writing of the data
U is performed quickly between the U and the cache memory, and only when the target data does not exist in the cache memory,
The CPU accesses data stored in the main storage device. With this configuration, access from the CPU to data stored in the main storage device can be reduced, thereby improving the throughput of the entire information processing system.

Here, a CPU for a cache memory
When the data in the cache memory is rewritten by the write operation from, the data in the cache memory and the corresponding data in the main storage device become inconsistent. Since it is not preferable that the data is inconsistent in this way, the data in the cache memory whose contents have been rewritten is written back to the main storage device, and the data in the cache memory does not match the data in the main storage device. Is controlled so as to eliminate the problem. On the other hand, when the CPU issues a read request or a write request to the cache memory and the target data does not exist in the cache memory, the CPU reads the target data from the main storage device and stores the data in the cache memory. Request to be transferred within.

The cache memory performs address translation at a high speed and detects whether or not the address of the target data is stored in the cache memory.
translation Lookaside Buff
er) section and a data cache for storing data. Since the TLB is not directly related to the present invention, the data cache is hereinafter referred to as a cache memory.

Conventionally, in this type of cache memory, it is necessary to divide a data storage area into a plurality of partial areas called cache lines, provide a flag called a dirty bit for each cache line, and write it back to the main storage device. Some cache lines are configured to turn on a dirty bit for a cache line storing certain data. In such a cache memory, the data of the cache line whose dirty bit is on is written back to the main storage device when the data of the cache line becomes a replacement target, so that the cache memory and the main storage device are written. Inconsistency in the data between the two. Such a method for maintaining consistency between data stored in the cache memory and data stored in the main storage device is called a write-back method.

[0006] By the way, the memory capacity of the cache memory tends to increase with the increase of the processing capacity of the CPU and the gap of the data transfer speed with the lower level, and the data stored in each cache line also has a miss rate. For example, 32 bytes or 64 bytes
Bytes and has increased. However, if the size of the data stored in the cache line is increased in this way, if a mistake occurs once, for example, in order to write back only one byte of data in a single cache line, the entire cache line is rewritten. The time required to write back this data to the main storage device is longer than the time required to write back 1-byte data. That is, when the cache line size is increased, the miss rate decreases, while the miss penalty in the case of a miss increases.

Conventionally, the data storage area of the cache memory is divided into cache lines, and each cache line is further divided into sub-blocks. If only a part of each cache line needs to be rewritten, the data should be rewritten. A cache memory in which only the sub-blocks are written back and the remaining sub-blocks are not written back has been proposed (JP-A-4-195563 (hereinafter referred to as Conventional Example 1)) and JP-A-5-282208. Gazette (hereinafter,
Refer to Conventional Example 2). In addition, in each of the above-described conventional examples 1 and 2, a dirty bit is provided for each sub-block, and a sub-block smaller than a cache line is used as a unit or a sub-block including a target sub-block. A cache memory of a type that is written back to the main storage device for each block group is disclosed, whereby a decrease in throughput due to useless data transfer can be prevented.

[0008]

However, the cited examples 1 and 2 point out a problem when the dirty bits corresponding to a plurality of sub-blocks are on in each cache line of the cache memory. I haven't. That is, in each cache line,
When the corresponding sub-blocks with the dirty bit on are dispersed or scattered, the main storage device is provided for each sub-block with the dirty bit on or for each sub-block group including each sub-block. , The data transfer time may be shortened by performing the write-back for each cache line depending on the number of sub-blocks to be written. In such a case, Conventional Example 1 and Conventional Example 2 do not consider at all, and cannot be said to disclose the optimum data to be rewritten. In other words, Conventional Example 1 and Conventional Example 2
Does not consider at all the relationship between the size of data to be rewritten and the time required for rewriting.

An object of the present invention is to provide a data size,
An object of the present invention is to provide a cache memory capable of adaptively obtaining an optimal data transfer time according to the number of sub-blocks.

Another object of the present invention is to provide a cache memory system capable of optimizing a data transfer time from a cache memory to a main storage device according to a data size.

Still another object of the present invention is to store data having an optimum size from a cache memory to a main storage device by utilizing the distribution of sub-blocks to be rewritten and the relationship between the data size and the required rewriting time. It is to provide a way to ask.

[0012]

According to the present invention, there are provided a plurality of cache lines each storing a predetermined amount of data, and a plurality of dirty bit storages respectively corresponding to the plurality of cache lines. In a cache memory system including a cache memory and data write-back means for writing back data stored in the cache line to a lower-level storage area as viewed from the cache memory, a data size and a write The cache memory further includes a table indicating a relationship with a time required for return, wherein the cache memory includes a plurality of cache lines each of which is divided into a predetermined number of sub-blocks, and each of the dirty bit storage units includes , Dirty corresponding to sub-block in corresponding cache line The data write-back means refers to the table when writing back the data stored in the specific cache line, and stores the dirty data corresponding to the specific cache line. Of the dirty bits stored in the bit storage unit, with reference to the dirty bit indicating ON, an optimal combination of the sub-blocks to be written back is determined, and the sub-blocks constituting the optimal combination are determined. A cache memory system is characterized in that stored data is written back to the lower level storage area.

According to the present invention, in the cache memory system, the cache memory has a plurality of tag fields for storing tags corresponding to each of the plurality of cache lines. A cache memory system that performs

Further, according to the present invention, in the cache memory system, the data write-back means, when writing data stored in the specific cache line back to the lower-level storage area, Referring to a table, the specific tag that is the tag stored in the tag field corresponding to the specific cache line, and the specific tag stored in the dirty bit storage unit corresponding to the specific cache line. Referring to a specific dirty bit, which is a dirty bit, a data size and a write-back size for generating an address in the specific cache line for data of the sub-blocks constituting the optimal combination.
When writing back the data stored in the specific cache line to the lower-level storage area, refer to the table and refer to the specific tag and the specific dirty bit. A write-back data generating unit for generating write-back data as data of the sub-blocks constituting the optimum combination, the data size generated by the write-back size / address generating unit, and the specific cache An address in a line, and a write buffer for temporarily storing the write-back data generated by the write-back data generation unit, and a state of the write buffer are monitored, and the lower-level storage area is The data size temporarily stored in the write buffer, Cache memory system is obtained which is characterized by comprising a write-back controller for controlling write back address and the write-back data.

Further, according to the present invention, in the cache memory system, an address having the same content as an address included in a request for the cache memory is received from an upper level of the cache memory, and the lower level storage area is received. And a read control unit for receiving a data request corresponding to the data request from the lower-level storage area and transmitting the data to the cache memory. A cache memory system characterized in that

Further, according to the present invention, in the cache memory system, the write-back control unit arranges the write-back data, the data size, which is the size of the write-back data, and the address in the write buffer. A write buffer status signal indicating that the write back data, the data size, and the data size in the write buffer are received in response to a data transfer end signal from the read control unit. The read control unit responds to the data request received from the lower-level storage area after receiving the write buffer state signal after writing the address back to the lower-level storage area. Transferring data to the cache memory; Cache memory system, wherein the data transfer end signal indicating that finished is for sending to the write-back controller is obtained.

Further, according to the present invention, there is provided a cache memory having a plurality of cache lines as a data storage area, wherein the cache line is divided into a plurality of sub-blocks, and a plurality of dirty bits corresponding to each of the sub-blocks are stored. In a cache memory to be provided, a method for obtaining an optimum write-back data size when it is necessary to write back data stored in the cache line to a lower-level storage area as viewed from the cache memory. The sub-block corresponding to the dirty bit indicating ON and the sub-block adjacent to the sub-block are grouped together based on the relationship between the data size and the time required for write-back, and Judge whether to write back to the A write-back data block composed of a plurality of the sub-blocks that are determined to be written back according to the distribution of dirty bits indicating ON, and a data block having the same data size as the write-back data block. A method for obtaining an optimum write-back data size by determining whether data blocks adjacent to the write-back data block should be written back to the lower-level storage area. .

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a cache memory and a cache memory system according to an embodiment of the present invention will be described with reference to the drawings.

The cache memory according to the present embodiment has the structure shown in FIG.
, The first to n-th cache lines CL1 to CL (n) as the data storage unit DM and the corresponding first to n-th tag fields TF1 to TF
(N) and first to nth dirty bit storage units DBM
1 to DBM (n).

The first to n-th cache lines CL1 to CL1
Each of CL (n) can store a predetermined amount of data. Hereinafter, the data size that can be stored in the cache line is called a cache line size. In the present embodiment, the first to n-th
Are recognized as a group of n (four in FIG. 1 are shown) cache lines CL1 to CL (n). For example, in FIG. 1, the first cache line is recognized as a group of first to fourth sub-blocks SB1 to SB4.
Each of the sub-blocks SB1 to SB4 can store a second predetermined amount of data. Here, the second predetermined amount is obtained by dividing the cache line size by the number n of the sub-blocks. Hereinafter, this second
, The data size that can store the sub-block is called the sub-block data size. For example, if the cache line size is 32 bytes and the number n of sub-blocks is 32, the sub-block data size is 1 byte (8 bits).
In the field of the cache memory, there is a concept of a block which means the minimum unit of data transfer. However, the sub-block is not limited to this block, but follows the above-described definition.

The first to n-th tag fields TF1 to TF
F (n) is for storing a tag. Here, the tag is information for determining whether or not a desired word is stored in a corresponding one of the first to n-th cache lines CL1 to CL (n). .

First to nth dirty bit storage units DB
Each of M1 to DBM (n) is for storing n (four as an example in FIG. 1) dirty bits. The n dirty bits in the first to nth dirty bit storage units DBM1 to DBM (n) are stored in one of the n subblocks in the first to nth cache lines CL1 to CL (n), respectively. Corresponding. For example, in FIG. 1, the first dirty bit DB1 stored in the second dirty bit storage unit DBM2 corresponds to the first sub-block SB1 in the second cache line CL2, and the (n-3) th dirty bit The fourth stored in the storage unit DBM (n-3)
Dirty bit DB4 corresponds to the fourth sub-block SB4 in the (n-3) th cache line CL (n-3). Note that the dirty bit is a bit for determining whether or not to rewrite the currently stored data to a lower level when replacing data stored in the cache line with another data. If the dirty bit is on, the data stored in the cache line is written back. In particular, in the present embodiment, since a dirty bit corresponds to a sub-block, if a certain dirty bit is turned on, data stored as a corresponding sub-block is stored in a lower-level storage area. Can be determined to need to be written back.

As shown in FIG. 2, the cache memory system 10 of the present embodiment includes the cache memory 20 described above and a data write-back unit 30 described in detail below. In the present embodiment, the cache memory system 10 provided between the CPU 40 and the main storage device 50 will be described as an example. However, the storage unit in the information processing apparatus generally includes a plurality of levels of memories having different speeds and capacities. Here, in a storage hierarchy composed of a plurality of levels of memories, a level close to the CPU of the information processing apparatus is called an upper level,
If a level far from the PU is defined as a lower level, the cache memory system of the present invention only needs to be arranged at a level where at least a lower level storage area exists. According to the above definition, in the present embodiment, a lower-level storage area as viewed from the cache memory corresponds to the main storage device 50.

The data write-back means 30 is for writing data stored in the cache line back to the main storage device 50. In particular, in the present embodiment, the data write-back unit 30 performs the following operation when it is necessary to write back the data stored in the third cache line CL3 to the main storage device 50, for example. Process. That is, taking FIG. 1 as an example, the third cache line CL3 is provided with reference to four dirty bits stored in the third dirty bit storage unit DBM3 corresponding to the third cache line CL3. Among the first to fourth sub-blocks SB1 to SB4, the optimum combination of the sub-blocks to be rewritten is determined, and the data stored in the sub-block constituting the optimum combination is stored in the main storage according to the determination. This is for writing back to the device 50.

Here, each of the sub-blocks constituting the optimum combination includes a write-back required time required for writing data of various data sizes back to the main storage device 50 and the data as described later. According to the relationship with the size, the determination is made such that the required rewrite time is the shortest, so that the present invention is not limited to only the sub-block in which the dirty bit is on. That is, the optimal combination of sub-blocks to be rewritten may consist only of sub-blocks with the dirty bit on, while sub-blocks with the dirty bit on and sub-blocks with the dirty bit off. In some cases, it is different from the above-mentioned conventional example 1 in this point. Also, the optimal combination of sub-blocks to be written back may be a combination of a collection of an arbitrary number of consecutive sub-blocks and a collection of an arbitrary number of consecutive sub-blocks having different data sizes. In this respect, this point is different from the above-mentioned conventional example 2. Since the term “rewrite subblock” is used as a term in the following description, the “subblock to be rewritten” and the “rewrite subblock” in the description so far should not be confused with each other. Need attention.

Data write-back means 30 in this embodiment
As shown in FIG. 3, a write-back size / address generation unit 301 and a write-back data generation unit 302
, Write buffer 303 and write-back control unit 30
4 and a read control unit 305.

Write-back size / address generator 30
1 designates, for a cache line to be written back to the main storage device 50, a tag stored in the tag field TF corresponding to the cache line and a predetermined number of dirty bits stored in the corresponding dirty bit storage DBM. With reference to the bit DB, an optimal combination of sub-blocks to be rewritten is determined in accordance with a table representing the relationship between the data size and the required write-back time, and the data size and the cache line address information relating to the optimal combination are determined. This is for sending to the write buffer 303. The table showing the relationship between the data size and the required write-back time for the data size is as follows:
The write-back size / address generation unit 301 may be provided, the cache memory 20 may be provided, or the data may be stored in a separately provided storage unit. However, when the write-back size / address generation unit 301 determines an optimal combination of sub-blocks to be rewritten, the table needs to be able to be referred to by the write-back size / address generation unit 301.

The write-back data generation unit 302 operates similarly to the write-back size / address generation unit 301.
An optimal combination of sub-blocks to be rewritten is determined according to a table representing the relationship between the data size and the required write-back time, and write-back data, which is data relating to the optimal combination, is sent to the write buffer 303. It is for doing. The write-back data generator 3
02, write-back size / address generation unit 3
Similarly to 01, when the write-back data generation unit 302 determines the optimum combination of sub-blocks to be rewritten, the table needs to be able to be referred to by the write-back data generation unit 302.

The write buffer 303 receives the write-back data size and address information generated by the write-back size / address generation unit 301 and the write-back data generated by the write-back data generation unit 302, and temporarily stores them. It is for storing.

The write-back control unit 304 monitors the state of the write buffer 303 and sends a write buffer status signal indicating that the write-back data size and address and the write-back data are ready in the write buffer 303 to the read control unit 305. Is to be sent out. Further, the write-back control unit 304 receives the data transfer end signal from the read control unit 305, and stores the data size and address of the write-back data in the write buffer 303 and the write-back data in the main storage device 50.
This is for performing control to write back to.

The read control unit 305 receives an address having the same content as the address sent from the CPU 40 to the cache memory 20, sends the address and the required data size to the main storage device 50, and The data corresponding to the address and the data size is received from the main storage device 50, and further, after receiving a write buffer status signal from the write-back control unit 304, the data received from the main storage device 50 is stored in the cache memory 20. This is for writing to the corresponding cache line. When the writing of the data received from the main storage device 50 to the cache memory 20 ends, the read control unit 305 sends a data transfer end signal indicating that the data transfer has ended to the write back control unit 30.
4 for transmission.

The operation of the cache memory system 10 having such a configuration will be described below together with the operations of the CPU 40 and the main storage device 50. In the following, a case where a read request is made from the CPU 40 to the cache memory 20 and a case where a write request is made will be described separately.

First, a case where a read request is made will be described.

When making a read request, the CPU 40 sends an address to the cache memory 20 to request data.

The cache memory 20 determines whether the request from the CPU 40 is a miss or a hit, and returns the result of the determination to the CPU. When a request hits, the cache memory 20 sends the requested data to the CPU 40. On the other hand, if the request misses, the data stored in one of the cache lines must be replaced. Here, in the direct map method, since the address received from the CPU 40 and the cache line in the cache memory 20 uniquely correspond to each other, the cache line for which data must be replaced, that is, the cache line to be updated is also uniquely determined. Will be. However, in the set associative method and the full associative method, a cache line to be replaced cannot be uniquely determined from an address. Therefore, the set associative or full associative cache memory 20
In, when a request is missed, it is necessary to find a cache line to be updated.

Further, the cache memory 20 stores a dirty bit storage unit D corresponding to the cache line to be updated.
A predetermined number of dirty bit DBs stored in the BM
Of the write-back control unit 304, the write-back size /
Address generation unit 301 and write-back data generation unit 3
02 is sent.

The CPU 40 receives the determination result from the cache memory 20 and, if the determination result indicates a hit, further receives the requested data. On the other hand, when the determination result indicates a mistake, the address relating to the necessary data is transmitted to the read control unit 305 to request the main storage device 50 for the necessary data. The main storage device 50 sends the requested data to the read control unit 305.

Write-back address / size generator 30
In accordance with a predetermined number of dirty bits received from the cache memory 20 corresponding to the cache line to be updated, when the data stored in the cache line needs to be written back, the data size and the required write-back time Then, it is determined how best to rewrite, based on the relationship between the data size and the address, and the data size and the address information based on the determination are sent to the write buffer 303.

On the other hand, the write-back data generator 302
Determines, in the same manner as the write-back address / size generation unit 301, how to best write back according to the dirty bit from the cache memory 20,
The write-back data based on the determination is sent to the write buffer 303.

The write-back control unit 304 monitors the state of the write buffer 303, and when the write-back data, the data size and the address information relating to the write-back data are aligned in the write buffer 303, the read control unit 30
5, a write buffer status signal is transmitted.

The read control unit 305 receives the write buffer state signal, and thereafter transfers the data received from the main storage device 50 to the CPU 40 via the cache memory 20. Further, after the transfer is completed, the read control unit 305 sends a data transfer end signal to the write-back control unit 304.

The write-back control unit 304 receives the data transfer end signal from the read control unit 305, and receives the write-back data temporarily stored in the write buffer 303, the data size and address information related to the write-back data, and the like. Are sequentially transmitted to the main storage device 50 to write back the write-back data.

Next, a case where a write request is made will be described.

When making a write request, the CPU 40 sends an address and data to the cache memory 20.

The cache memory 20 determines whether the request from the CPU 40 is a miss or a hit, and returns the result of the determination to the CPU. Here, if the request hits, C
The data from the PU 40 will be written to the cache line corresponding to the request in the cache memory 20. When the request hits, the cache memory 20 sets a dirty bit in the dirty bit storage unit corresponding to the cache line in which the data is written. In particular, in the present embodiment, since a dirty bit corresponding to each sub-block is provided, a dirty bit is set for each sub-block whose data has been changed. On the other hand, if the request misses, the data stored in one of the cache lines must be replaced. In that case, the cache memory 20
As in the case of the read request described above, if necessary, a cache line to be updated is determined. Further, the cache memory 20 stores a predetermined number of dirty bits DB stored in the dirty bit storage unit DBM corresponding to the cache line to be updated into the write-back control unit 304,
It is sent to the write-back size / address generation unit 301 and the write-back data generation unit 302.

When the CPU 40 receives the determination result from the cache memory 20 and the determination result indicates a mistake, the CPU 40 sends the address related to the data to be written to the read control unit 305, thereby making the main storage A request for the data is made to the device 50. The main storage device 50 sends the requested data to the read control unit 305.

Write-back address / size generator 30
In accordance with a predetermined number of dirty bits received from the cache memory 20 corresponding to the cache line to be updated, when the data stored in the cache line needs to be written back, the data size and the required write-back time Then, it is determined how best to rewrite, based on the relationship between the data size and the address, and the data size and the address information based on the determination are sent to the write buffer 303.

On the other hand, the write-back data generator 302
Determines, in the same manner as the write-back address / size generation unit 301, how to best write back according to the dirty bit from the cache memory 20,
The write-back data based on the determination is sent to the write buffer 303.

The write-back control unit 304 monitors the state of the write buffer 303, and when the write-back data, the data size and the address information relating to the write-back data are aligned in the write buffer 303, the read-back control unit 30
5, a write buffer status signal is transmitted.

The read control unit 305 receives the write buffer status signal, and thereafter transfers the data received from the main storage device 50 to the cache line in the cache memory 20 to be updated. Is written from the CPU 40 to the. Further, after the data transfer or the like is completed, the read control unit 305 sends a data transfer end signal to the write-back control unit 304.

The write-back control unit 304 receives the data transfer end signal from the read control unit 305, and receives the write-back data temporarily stored in the write buffer 303, the data size and address information related to the write-back data, and the like. Are sequentially transmitted to the main storage device 50 to write back the write-back data.

As described above, in the present embodiment, the CPU 4
This is a series of processing operations when a read request and a write request are made from 0.

Next, the processing when the write-back size / address generator 301 and the write-back data generator 302 determine the optimum combination of sub-blocks to be rewritten will be described with reference to FIGS. This will be described with reference to a typical example. In the following processing operation example,
The cache line size is 32 bytes, and the sub-block size of the initial sub-block is 1 byte.
Therefore, the number of sub-blocks is initially 32. Here, during the processing operation, the size of the sub-block changes as described later. Therefore, when it is necessary to distinguish the initial sub-block from the sub-block in the subsequent processing, the initial sub-block is referred to as an initial sub-block. Simultaneously, the data size of the initial sub-block is called an initial sub-block data size, and the number of initial sub-blocks is called an initial sub-block number.

As described above, in determining the optimum combination of sub-blocks to be rewritten in the present embodiment, the data size and the required rewriting time required for rewriting data of that size are determined. Is needed. In the following processing, a specific example of the table will be described with reference to FIG. The left column in FIG. 4 shows each data size, and the unit is byte. In addition, the right column in FIG. 4 is the required write-back time corresponding to each data size shown in the left column, and t is 30 ns.
The right column in this table may be the number of clocks or the like. For example, if one clock is 30 ns in FIG. 4, each value in the right column is 4,
4, 5, 7, 11, and 22.

FIGS. 5 and 9 are diagrams showing a process of obtaining an optimum combination of sub-blocks to be rewritten in each specific example. FIGS. 6 to 8 are flowcharts showing the processing operation for finding the optimum combination.

First, as shown in FIG. 6, each initial value of the sub-block data size, the number of sub-blocks, and the cache line size is set, and the sub-block data size is set as the current data size (step S101). . Here, the sub-block data size and the number of sub-blocks are the initial sub-block data size and the initial number of sub-blocks according to the above-mentioned definitions, and are 1 byte and 32 in this processing example, respectively. The cache line size is 32 bytes. Further, the current data size is 1 byte because it is the same as the initial sub-block data size.

Next, a write-back sub-block is determined according to the dirty bit DB sent from the cache memory 20 (step S102). Specifically, a sub-block in which the corresponding dirty bit is on is set as a write-back sub-block. In FIG. 5A, the write-back sub-block is shown in black.

Next, the data stored in the write-back sub-block is stored as a write-back data block (step S103). The rewrite data block is a data block having a data size that is actually determined to be rewritten in the determination process, and the data size may change in the processing process. The write-back sub-block refers to a sub-block including a write-back data block among the sub-blocks in the respective determination processes. Therefore, in the initial stage shown in FIG. 5A, the write-back sub-block matches the write-back data block.

Next, half of the number of sub-block pairs are determined using adjacent sub-blocks as sub-block pairs (step S104). For example, in FIG. 5A, the lowermost sub-block S
B1 and the sub-block SB2 located above (next to)
Is a sub-block pair SBP1, and a sub-block SB3 and a sub-block S
A pair with B4 is referred to as a sub-block pair SBP2. Sub-block pairs are determined in the same manner for the remaining sub-blocks, and a total of 16 sub-block pairs are determined.

Next, the sub-block pair to which the write-back sub-block belongs is defined as a write-back sub-block pair, and a sub-block number is assigned to each write-back sub-block pair (step S105). For example, in FIG. 5A, there are four write-back sub-blocks, each of which forms a sub-block pair with a sub-block which is not a write-back sub-block. Become.
The four write-back sub-block pairs SBP1, SBP2,
SBP3 and SBP4 are assigned subblock numbers 1, 2, 3, and 4, respectively, from the lower order.

Next, as the current sub-block number,
In addition to setting 1, the number of write-back sub-block pairs is set as the number of sub-block pairs (step S10).
6). In the state of FIG. 5A, since there are four write-back sub-block pairs, the number of sub-block pairs is four.

Next, regarding the sub-block pair to which the current sub-block number is assigned, whether or not it is better to collectively write back as a sub-block pair according to the table showing the relationship between the required time for rewriting and the data size. It is determined (step S107), and when it is determined that it is better to collectively write back, the process proceeds to step S108, and when it is determined that it is not preferable to collectively write back, the process proceeds to step S109.

Here, the determination in step S107 will be described in more detail with reference to FIG. First, it is determined whether or not both of the sub-block pairs to which the current sub-block number is assigned are sub-blocks forming the sub-block pair (Step S1071). Step S107
If it is determined in step 1 that both of the sub-block pairs are write-back sub-blocks, the write-back time required for each of the write-back data blocks included in the sub-block pair is the time required for the write-back. Is short or not
The determination is made according to a table indicating the relationship between the data size and the required write-back time (step S1072). If it is determined in step S1072 that the required write-back time is short, the process proceeds to step S109. If it is determined that the time is not short, the process proceeds to step S108, and the subsequent processes are executed. On the other hand, if it is determined in step S1071 that only one of the sub-blocks is a write-back sub-block, the write-back sub-block may be collectively written back as a sub-block pair based on a table indicating the relationship between the required write-back time and the data size. It is determined whether or not the required write-back time does not change, as compared with the case where only the write-back data block included in the return sub-block is written back (step S1073). If it is determined in step S1073 that the required write-back time does not change, the process proceeds to step S108. If it is determined that the collective write-back as a sub-block pair requires a longer write-back time, the process proceeds to step S109. Execute the process. At present, since the current sub-block number is 1, only one of the sub-blocks constituting the sub-block pair SBP1 is a write-back sub-block. Therefore, according to the determination in step S1071, the process proceeds to step S1073, where the sub-block pair SB
P1 is determined based on the table shown in FIG. According to the table shown in FIG. 4, since the required write-back time does not change whether the data size is 1 byte or 2 bytes, it is better to collectively write back the sub-block pairs as a larger data size. It is determined to be good (step S1073), and the process proceeds to step S108.

Next, if it is determined in step S107 that it is better to collectively write back, the initial sub-blocks forming the sub-block pairs are stored as new write-back data blocks (step S108). At this time, instead of the sub-block SB1 stored as the write-back data block, the two initial sub-blocks SB1 and SB2 forming the sub-block pair SBP1 are stored as new write-back data blocks.

Next, it is determined whether or not the current sub-block number is equal to the number of sub-block pairs (step S109).
Execute the following processing. On the other hand, if the result of the determination in step S109 is not the same, 1 is added to the current sub-block number, the addition result is reset as a new current sub-block number (step S111), and the process proceeds to step S107 to continue the processing. I do. At this time, the current sub-block number is 1 and the number of sub-block pairs is 4. Therefore, the process proceeds to step S111, where the current sub-block number is reset to 2, and the sub-block number of the sub-block pair SBP2 of 2 is set. S
The determination at 107 is made. Similarly, when the determination is completed up to the sub-block pair SBP4, an initial sub-block as shown in black in FIG. 5B is stored as the rewrite data block. When the determination is completed up to the sub-block pair SBP4, the sub-block number is 4, which is equal to the number of sub-block pairs.

If the current sub-block number and the number of sub-block pairs match in step S109, then it is determined whether or not the current data size and half the cache line size match (step S110). If they match, step S1
The process proceeds to step S13, and the subsequent processing is executed. Step S1
If it is determined in step 10 that they do not match, the current data size doubled is reset as a new current data size, and a sub-block pair is set as a new sub-block. The sub-block including the return data block is reset as a new write-back sub-block (step S112), and step S104 is performed.
Return to and continue the processing. At this time, as shown in FIG. 5A, the current sub-block size is 1 byte, while the data size that is half of the cache line size is 32/2 and 16 bytes.
The determination at 110 does not match. Therefore, the process proceeds to step S112, and the value is reset. That is, the current data size (1 byte) so far is doubled, and 2 bytes are set as a new current data size. Further, for example, the sub-block pair SBP1 is replaced with a new sub-block SB1 '.
Similarly, the sub-block pair SBP2 is set as a new sub-block SB2 '. When all sub-block pairs are set as new sub-blocks,
The number of new sub-blocks is 16. This 16
Among the sub-blocks, the four sub-blocks including the write-back data block are blacked out in FIG. 5B, and are set as new write-back sub-blocks.

After these settings are completed, step S1
Proceeding to step 04, eight sub-block pairs are determined using adjacent new sub-blocks as new sub-block pairs. For example, in FIG. 5B, a new sub-block SB1 'and a sub-block SB2' are used as a new sub-block pair SBP1 ', and eight sub-blocks (SBP2' and others) are similarly determined (step S104). reference). In FIG. 5B, there are four write-back sub-blocks, but since one set of the write-back sub-blocks constitutes one sub-block pair, there are three write-back sub-block pairs. . Accordingly, the three sub-block pairs SBP1 ', SBP2', and SBP3 'are assigned sub-block numbers of 1, 2, and 3 in order from the lower order (see step S105). Further, it is determined whether it is better to collectively write back all of them as a sub-block pair (steps S107 and S10).
9), if it is better to collectively write back, the initial sub-blocks forming the sub-block pair are stored as new write-back data blocks. Regarding the sub-block pair SBP1 ', the time required for rewriting is 3t when collectively rewriting data, rather than rewriting for each rewriting data block.
Can be shortened (see FIG. 4 and step S1072),
As a new write-back data block, four initial sub-blocks S forming the sub-block pair SBP1 '
B1 to SB4 are stored (see step S108). On the other hand, as for the sub-block pair SBP2 'and the sub-block pair SBP3', the rewriting time is longer by 1 t if rewriting together (see FIG. 4 and step S1073).
The current sub-block SB3 'and sub-block SB
4 'remains as the initial sub-block. In this way, even if the determination is completed for all the write-back sub-block pairs in FIG. 5B, the current data size is 2 bytes, and the data size (16 bytes) which is half the cache line size (32 bytes) Byte) (see step S110),
Proceed to 112. In step S112, the new current data size is set to 4 bytes, and the sub-block pair SB is set.
Let P1 'and the sub-block pair SBP2' be new sub-blocks SB1 "and SB2", respectively. Similarly, assuming that the sub-block pair in FIG. 5B is a new sub-block, eight new sub-blocks are created. Of the eight sub-blocks, the number of sub-blocks including the write-back data block is three as shown in FIG. 5C (sub-blocks SB1 ″, SB).
2 ", SB3"). After these settings, the process returns to step S104 again to determine four new sub-block pairs, and further executes the processing from step S105. In this way, as shown in FIGS. 5C to 5E, the judgment on the write-back data block is performed while gradually increasing the current data size. In the state shown in FIG. 5E, the current data size is 16 bytes,
Since it is half of the cache line size (32 bytes), as a result of the determination in step S110, step S110
You can proceed to 113.

At this stage, the stored write-back data block is determined as an optimal combination of initial sub-blocks to be written back (step S113). For example, referring to FIG. 5F, two write-back data blocks WBD1 and WBD2 are obtained by the processing up to FIG. 5E. That is, the initial sub-block constituting the optimum combination to be rewritten is the lowest sub-block #
8 sub-blocks from 0 to sub-block # 7;
There are a total of 10 sub-blocks including a top-level sub-block # 31 and a sub-block # 30 located below the top-level sub-block # 31.
+ 4t = 11t. If rewriting is performed for each sub-block in which the dirty bit is on as in Conventional Example 1, the required rewriting time is 4t × 4 = 16t. Further, when writing back for each sub-block group including a write-back sub-block as in Conventional Example 2, even if the size of the sub-block group is set to any size of 2 bytes, 4 bytes, 8 bytes, and 16 bytes, The time required for writing back is longer than 11t in this specific example. In other words, in both cases of Conventional Example 1 and Conventional Example 2, a longer write-back time is required as compared with the present embodiment in which the optimum combination of sub-blocks to be written back is adaptively determined. .

FIG. 9 shows another example of the process of determining the sub-blocks constituting the optimum combination. FIG.
Four initial sub-blocks # 0, # 6, # 16, and # 3
This is the case where the dirty bit corresponding to 1 is on. In FIG. 9A, processing is performed in the same manner as the above-described determination in FIG.
The write-back data block is determined in the order of (c), FIG. 9 (d), and FIG. 9 (e). As a result, as shown in FIG. 9F, eight initial sub-blocks # 0 to # 0 are used as sub-blocks constituting the optimum combination to be rewritten.
# 7, two initial sub-blocks # 16 and # 17,
A total of 16 with two initial sub-blocks # 30 and # 31
Are determined. The time required to write back these 16 sub-blocks to the main memory is 15
t. Also in this case, if the rewriting is performed for each sub-block in which the dirty bit is on as in Conventional Example 1, the required rewriting time is 4t × 4 = 16t.
Further, even if the data is rewritten for each sub-block group including the rewrite sub-block as in Conventional Example 2, the required rewrite time is longer than 15t.

Further, according to the method described in the present embodiment, when the dirty bits corresponding to all the sub-blocks are on for the cache line to be updated, the required write-back time is in units of cache lines. The time is the same as that in the case of rewriting, and the problem as in the conventional example 1 and the conventional example 2 does not occur.

As can be understood from the above, in the present embodiment, the time required for rewriting can be shortened even in comparison with Conventional Example 1 and Conventional Example 2.

Further, the fact that the time required for write-back can be reduced means that the cache line size can be made larger. Further, when the cache line size is set to a larger size, the miss rate in the cache memory is reduced, and the performance of the cache memory can be improved. That is, by applying the method described in this embodiment, it is possible to realize a cache memory with improved performance.

In the present embodiment, the cache memory and the cache memory system provided between the CPU and the main storage device have been described as examples. However, the concept of the present invention is not limited to the present embodiment. Not something.

[0074]

As described above, according to the present invention, the optimum combination of sub-blocks to be rewritten can be determined based on the table showing the relationship between the data size and the required rewriting time. Therefore, a cache memory system that can reduce the time required for writing back can be obtained.

Further, according to the present invention, a cache memory with improved performance can be realized by having a larger cache line size.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a cache memory according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a relationship between a cache memory system according to an embodiment of the present invention, a CPU, and a main storage device.

FIG. 3 is a block diagram illustrating a configuration of a data write-back unit according to the embodiment of the present invention.

FIG. 4 is an example of a table showing a relationship between a data size and a required write-back time according to the embodiment of the present invention.

FIG. 5 is a diagram illustrating an example of a process of determining an optimum combination of sub-blocks to be rewritten in the embodiment of the present invention.

FIG. 6 is a diagram showing a part of a flowchart for determining an optimum combination of sub-blocks in the embodiment of the present invention.

FIG. 7 is a diagram showing the rest shown in FIG. 6 of the flowchart for determining the optimal combination of sub-blocks in the embodiment of the present invention.

FIG. 8 is a diagram showing step S107 shown in FIG. 6 in further detail;

FIG. 9 is a diagram illustrating another example of a process of determining an optimum combination of sub-blocks to be rewritten in the embodiment of the present invention.

[Description of Signs] 10 Cache memory system 20 Cache memory 30 Data write back means 40 CPU 50 Main storage device 301 Write back size / address generation unit 302 Write back data generation unit 303 Write buffer 304 Write back control unit 305 Read control unit TF Tag field DBM dirty bit storage DM data storage

Claims (6)

[Claims] 1. A cache memory having a plurality of cache lines each storing a predetermined amount of data, a plurality of dirty bit storage units corresponding to each of the plurality of cache lines, and a lower order memory as viewed from the cache memory. In a cache memory system including data write-back means for writing back data stored in the cache line to a storage area of a level, a table representing a relationship between a data size to be written back and a time required for the write-back. The cache memory further includes a plurality of cache lines, each of the plurality of cache lines is divided into a predetermined number of sub-blocks, and each of the dirty bit storage units corresponds to a sub-block in a corresponding cache line, respectively. To store dirty bits The data write-back unit refers to the table when rewriting data stored in the specific cache line, and writes dirty data stored in the dirty bit storage unit corresponding to the specific cache line. Among the bits, the optimum combination of the sub-blocks to be rewritten is determined by referring to the dirty bit indicating ON, and the data stored in the sub-blocks constituting the optimum combination is written to the lower level. A cache memory system for rewriting data in a storage area of the cache memory. 2. The cache memory system according to claim 1, wherein said cache memory has a plurality of tag fields for storing tags corresponding to each of said plurality of cache lines. Cache memory system. 3. The cache memory system according to claim 2, wherein the data write-back unit is configured to write back the data stored in the specific cache line to the lower-level storage area. And a specific tag that is the tag stored in the tag field corresponding to the specific cache line and the dirty bit stored in the dirty bit storage unit corresponding to the specific cache line. A write-back size / address generation unit for generating a data size and an address in the specific cache line with respect to the data of the sub-block constituting the optimum combination with reference to a specific dirty bit being a bit And the data stored in the specific cache line is When writing back to the lower level storage area, the table is referred to, and the specific tag and the specific dirty bit are referred to, and write-back as data of the sub-block configuring the optimal combination is performed. A write-back data generation unit for generating data; the data size and the address in the specific cache line generated by the write-back size / address generation unit; and the write-back data generated by the write-back data generation unit A write buffer for temporarily storing the data size, the address, and the data size of the data temporarily stored in the write buffer for the lower-level storage area while monitoring the state of the write buffer. Write-back for controlling write-back data write-back A cache memory system characterized by comprising a control unit. 4. The cache memory system according to claim 3, wherein an address having the same content as an address included in a request to said cache memory is received from an upper level of said cache memory and said storage area of said lower level is received. A read control unit for performing a data request corresponding to the request, receiving data corresponding to the data request from the lower-level storage area, and transmitting the data to the cache memory; A cache memory system characterized by the above-mentioned. 5. The cache memory system according to claim 4, wherein said write-back control unit comprises:
A write buffer status signal indicating that the data size, which is the size of the write-back data, and the address are aligned in the write buffer to the read control unit, and a data transfer end signal from the read control unit. Receiving the write-back data, the data size, and the address aligned in the write buffer in the lower-level storage area. After receiving the signal, data corresponding to the data request received from the lower level storage area is transferred to the cache memory, and a data transfer end signal indicating that the transfer has been completed is transmitted to the write-back control. A cache memory for sending to the Moly system. 6. A cache memory having a plurality of cache lines as a data storage area, wherein the cache line is divided into a plurality of sub-blocks and includes a plurality of dirty bits corresponding to each of the sub-blocks. A method for obtaining an optimum write-back data size when it is necessary to write back data stored in the cache line to a lower-level storage area as viewed from the cache memory, Based on the relationship with the time required for write-back, the sub-block corresponding to the dirty bit indicating ON and the sub-block adjacent to the sub-block should be collectively written back to the lower level storage area. Judge whether or not the plurality of dirty bits are on A write-back data block composed of a plurality of the sub-blocks determined to be written back according to the distribution of the write-back data block, and a data block having the same data size as the write-back data block. A method of determining an optimum write-back data size by determining whether data blocks adjacent to the block should be written back to the lower-level storage area.