JPH10269799A - Semiconductor memory tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the utilization factor of the memory devices for defect analysis memories to 100 % even in a low speed test mode and store fail data of a large number of test object memories by a small number of the memory devices by a method wherein a plurality of banks of which each memory cell is composed are assigned as the fail data storage regions of corresponding test object memories respectively in the low speed test mode. SOLUTION: The banks #1, #2, #3, #4,... of a memory block MBLK provided in each defect analysis memory unit are made to correspond to test object memories 15 one-to-one and utilized as the fail data storage regions of the respective test object memories 15 in a low speed test mode. Therefore, if the number of tested memories in a high speed test mode is denoted by (m) and the number of phases of an interleave operation is denoted by (n), (m) × (n) defect analysis memories can be prepared. With this constitution, the capacities of the memory devices for the defect analysis memories can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory test apparatus for testing a semiconductor memory.

[0002]

2. Description of the Related Art FIG. 4 shows a schematic configuration of an entire memory test apparatus. The memory test apparatus includes a timing generator 11, a pattern generator 12, a failure analysis memory 13, a waveform shaper 14, and a logical comparator 16, and tests the memory under test 15. The timing generator 11 generates a reference clock. The pattern generator 12 outputs an address signal, test pattern data, and a control signal to be supplied to the memory under test 15 according to the reference clock. These signals are applied to a waveform shaper 14, where the signals are shaped into waveforms necessary for a test and applied to a memory under test 15.

The memory under test 15 is controlled to write and read test pattern data by a control signal.
The test pattern data read from the memory under test 15 is given to the logical comparator 16, where the pattern generator 1
2 is compared with the expected value data outputted from the memory 2, and the quality of the memory under test 15 is determined based on the coincidence and the disagreement. When the occurrence of the mismatch is detected, fail data indicating the position of the memory cell where the mismatch has occurred is stored in the failure analysis memory 13 described below.

FIG. 5 shows a failure analysis memory 13 and a logical comparator 1.
6 shows a schematic configuration. An address signal and test pattern data are given to the memory under test 15 from the pattern generator 12 via the waveform shaper 14, and writing and reading of the test pattern data are performed. In the example of FIG. 5, the memory under test 15 has four input / output terminals I / O1, I / O2, and I / O.
3 and I / O4, and shows a configuration in which test pattern data having a 4-bit width is written and read.

The test pattern data read from the memory under test 15 is compared with the expected value pattern data by the logical comparator 16. The logical comparator 16 outputs the fail data F for each of the input / output terminals I / O1 to I / O4 of the memory under test 15.
AL1, FAL2, FAL3, and FAL4 are output and supplied to the failure analysis memory 13. For example, a static RAM (hereinafter, referred to as X1 SRAM) having a 1-bit data width for each of the input / output terminals I / O1 to I / O4 is prepared in the failure analysis memory 13, and the fail data FAL1 to FAL4 are stored in the X1 SRAM. . In this example, since the data width is 4 bits, four X1SRAM _{1 to} X1SRAM
₄ was prepared, fail data FAL1~FA to the chip select terminal / CS of each X1SRAM ₁ ~X1SRAM ₄
L4, and only when an inconsistency occurs, L logic is input to the chip select terminal / CS to control it to an active state,
It operates so as to write the H logic input to the data input terminals FD0 to FD3 to the address given at that time in synchronization with the supply of the write command pulse / WE. FIG.
Shows the storage format of fail data.

The configuration and operation of the failure analysis memory 13 described above is a configuration and operation for testing a memory at a normal speed (relatively low speed). A configuration for testing a high-speed memory is also added to the semiconductor memory test device. That is,
The failure analysis memory 13 is configured by providing a plurality of normal-speed memories, operating the plurality of memories in a time-division manner, and storing high-speed fail data. This method is hereinafter referred to as interleaving. In order to perform the interleave operation, the X1SRA shown in FIG.
It is necessary to provide the configurations of M _{1 to} X ₁ SRAM _{4 for} the number of interleaved phases. If the four-phase phase number of interleaving, the combination of X1SRAM ₁ ~X1SRAM _{4 4}
X1SRAM _{1 to} X1SRAM _{4 of} these sets are provided.
Are interleaved. Here, these sets are referred to as banks, and when the number of interleaving phases is four, four banks are prepared.

FIG. 7 shows the operation of interleaving.
The high-speed fail data HFAL is dispersed and stored in banks # 1 to # 4 in accordance with the four-phase bank select signals S1, S2, S3 and S4 shown in FIG. 7B. Therefore, the X1 SRAM ₁ to X1 SRAM ₄ constituting each bank # 1 to # ₄
Suffices to operate at a period T that is four times longer than the high-speed fail data HFAL.

FIG. 8 shows a configuration of a conventional failure analysis memory 13 which can be operated by switching between a high-speed mode and a low-speed mode. Shows a case where the failure analysis memory 13 in this example by a plurality of failure analysis memory unit 13 ₁ to 13 _m. If the number of memories under test that can be tested at the same time is m regardless of whether the test mode is the high-speed test mode or the low-speed test mode, the defect analysis memory units are also 13 _{1 to} 13.
_m are provided up to m. Each failure analysis memory unit 1
3 memory block MBLK is provided with a memory configuration tall unit MCON to ₁ to 13 _m. This memory block MBLK has as many banks BNC # 1 as the number of interleaved phases.
~ BNC # n. In the example of the figure, the bank BN is used to enable the interleaving operation up to n phases.
This shows a case where n banks C # 1 to BNC # n are provided.

The memory control unit MCON includes a fail format unit FLFO and a bank selector BLSE.
, An operating frequency register FRG, and a shifter SFT. The fail format section FLFO cuts out a bit width corresponding to the output bit width of the memory under test and supplies fail data having the same bit width as the bit width output by the memory under test to each of the banks BNC # 1 to BNC # n. .

The bank selector BLSE outputs a bank select signal corresponding to the low-speed test mode and the high-speed test mode. That is, in the low-speed test mode, a bank select signal is generated based on the value set in the operating frequency register FRG, and generally, a bank select signal is output to the bank BNC # 1, and the bank BNC # 1 is set to the operation mode.

In the high-speed test mode, the shifter SFT operates to generate a multi-phase bank select signal (see FIG. 7B) corresponding to the number of interleaved phases in accordance with the upper bits of the address signal applied to the memory under test 15. The bank select signal is distributed to each of the banks BNC # 1, BNC # 2,... And the banks BNC # 1 to BNC # n are operated in an interleaving manner.

An address signal applied to the memory under test 15 is applied to each address input terminal An of the X1 SRAM constituting each of the banks BNC # 1 to BNC # n, and the same address as that of the memory under test 15 is accessed. Also each X
H logic is applied to the data input terminal FD of the 1SRAM, and when fail data is inverted to L logic, H logic is written to the address given at that time.

[0013]

As described above, a conventional semiconductor memory test apparatus has a configuration for operating in a low-speed test mode and a high-speed test mode. In the low-speed test mode, as shown in FIG.
The configuration is such that the bank BNC # 1 in K is mainly used, and the other banks BNC # 2 to BNC # n are left unused.

Accordingly, in the low-speed test mode, only one-third of the number of phases of the interleaving operation of the memory mounted on the failure analysis memory 13 is practically used, and the test cost is high. In other words, when the number of phases of the interleave operation is four, only one-fourth of the mounted memory is practically used, and the ratio of the cost of equipment to the number of memories under test is large. Cost is high.

In general, the cost required for testing is reduced by increasing the number of semiconductor memories that can be tested simultaneously. However, in reality, the number of semiconductor memories that can be tested simultaneously in a low-speed test mode is reduced. As the number increases, the amount of memory (failure analysis memory) left unused in the high-speed test mode increases, and the cost required for the test apparatus increases. In this respect, there is a drawback that the test cost increases.

An object of the present invention is to improve the practical use rate of memory elements constituting a failure analysis memory to 100% even in a low-speed test mode, and to store fail data of many memories under test with a small number of memory elements. It is intended to provide a memory test device.

[0017]

According to the present invention, in the high-speed test mode, the number of memory blocks having the number of banks corresponding to the number of phases of the interleave operation is provided in the same number as the number of memories to be tested in the high-speed mode. In the semiconductor memory test apparatus equipped with the configured failure analysis memory, in the low-speed test mode, the failure data storage area of the memory under test is designated for each bank of each memory block constituting the failure analysis memory, and each memory under test is designated. Is stored in each bank.

Therefore, according to the semiconductor memory test apparatus of the present invention, especially in the low-speed test mode, the fail data storage area of the memory under test is designated for each of a plurality of banks constituting each memory block. Almost 100% can be practically used. As a result, if the number of interleaved phases is n and the number of memories under test that can be tested simultaneously in the high-speed test mode is m, then m
By using the failure analysis memory that stores the high-speed fail data of the memories under test,
A failure analysis memory for storing fail data of × n memories under test can be configured.

Therefore, even if the number of semiconductor memories that can be tested simultaneously in the low-speed test mode is increased, the amount of memory left unused can be reduced. Therefore, an advantage that the utilization rate of the memory can be improved is obtained.

[0020]

FIG. 1 shows an embodiment of the present invention. In FIG. 1, portions corresponding to those in FIG. 8 are denoted by the same reference numerals. This embodiment shows a case where the number of memories under test that can be tested simultaneously in the high-speed test mode is m as described with reference to FIG. Thus, 13 ₁ ~13 _{m m} pieces of failure analysis memory unit is provided as a failure analysis memory unit.

According to the present invention, each of the failure analysis memory units 13 _{1 to} 13 _m is provided with the same number of input terminal groups IN _{1 to} IN _n as the number of phases of the interleave operation. In the low-speed test mode, these input terminal groups IN ₁ to IN _n are provided. Low-speed fail data L in _n
To enter the FAL ₁ ~LFAL _n. The memory control unit MCON is provided with the same number of fail format units FLFO _{1 to} FLFO _n as the number of phases n of the interleave operation,
These n fail format sections FLFO _{1 to} FLFO
FO banks provided in the memory block MBLK through _n BNC # _1~BNC # _n to the low speed failure data LF
AL ₁ supplies ~LFAL _n.

A multiplexer MUX is provided at the preceding stage of each of the other fail format units FLFO _{2 to} FLFO _n except for the fail format unit FLFO ₁ , so that the multiplexer MUX can switch between the high speed test mode and the low speed test mode. ing. That is,
Another fail format section other than the fail format section FLFO ₁ fast failure data supplied to the input terminal group IN ₁ is a fast test mode FLFO ₂ ~FLFO
configured so that it can be applied to _n, as in the low-speed test mode can enter the low-speed failure data LFAL ₁ ~LFAL _n entered in the input terminal group IN ₁ to IN _n each fail formatter FLFO ₁ ~FLFO _n It is composed. RG is a register for controlling the state of the multiplexer MUX. That is, the multiplexer MU
X is switched to the input terminal A in the high-speed test mode, and is switched to the input terminal B in the low-speed test mode.

In the low-speed test mode, the bank selector BLSE has the same number of banks BNC # 1 to BNC # as the number of phases of the interleave operation according to the numerical value set in the operating frequency register FRG.
A select signal is given to NC # n, and all banks BNC #
1 to BNC # n in each fail format section FLFO ₁
～FLFO _n and 1: operate in correspondence to one. Therefore, each of the banks BNC # 1 to BNC # n is simultaneously accessed in accordance with the applied address signal, and stores the H logic supplied to the data input terminal FD at the address of the bank each time a failure (mismatch) occurs.

On the other hand, as shown in FIG. 2 is a fast test mode, high-speed failure data HFAL is supplied to the input terminal group IN _1, the multiplexer MUX is switched to the input terminal A, all of the fail formatter FLFO ₁ to FL
To supply high-speed fail data HFAL to FO _n. Fail format sections FLFO _{1 to} FLFO _n are high-speed fail data HF to which the bit width of fail data is input.
Bank BNC aligned with AL bit width and high-speed data
# 1 to BNC # n.

Each of the banks BNC # 1 to BNC # n is supplied with the multi-phase bank select signal shown in FIG. 7B from the bank selector BLSE. 7C, interleave operation is performed, and each bank BNC # 1 to BNC # 1
High-speed fail data HFAL is distributed and stored in BNC # n.

[0026]

According to the present invention, each of the failure analysis memory units 13 _{1 to} 13
By configuring as described above the _m, the low-speed test mode as shown in the bank #. 1 to # n is 3 of the memory blocks MBLK provided in each failure analysis memory unit 13 ₁ to 13 _m is the memory under test 15 is used as a storage area for fail data in each memory under test 15. Therefore, if the number of memories to be tested in the high-speed test mode is m, and the number of phases of the interleave operation is n,
In the low-speed test mode, m × n failure analysis memories can be prepared. That is, m memory blocks MBL
100% of each of the banks BNC # 1 to BNC # n of K can be used. If the same number of semiconductor memories are to be tested in the low-speed test mode, the memory capacity required for the failure analysis memory is reduced. be able to. Further, even when the number of memories under test that can be tested simultaneously is increased, each bank B of each memory block MBLK can be tested.
Since NC # 1 to BNC # n are practically used 100%, an increase in the memory capacity required for the failure analysis memory can be suppressed. Therefore, even if a test apparatus in which the number of memories under test that can be tested in the low-speed test mode is increased is manufactured, an increase in cost required for the failure analysis memory can be suppressed, and an advantage that the memory test apparatus can be manufactured at low cost can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment when a semiconductor memory test apparatus of the present invention is operated in a low-speed test mode.

FIG. 2 is a block diagram showing an embodiment when the semiconductor memory test apparatus of the present invention is operated in a high-speed test mode.

FIG. 3 is a diagram for explaining the concept of the main part of the present invention.

FIG. 4 is a block diagram for explaining the entire semiconductor test apparatus.

FIG. 5 is a block diagram for explaining the operation and configuration of a conventional failure analysis memory.

FIG. 6 is a diagram for explaining a storage format of fail data in a conventional failure analysis memory.

FIG. 7 is a waveform chart for explaining an interleaving operation.

FIG. 8 is a block diagram for explaining a configuration of a conventional failure analysis memory.

FIG. 9 is a view for explaining a conventional defect.

[Explanation of symbols]

13 Failure analysis memory 13 _{1 to} 13 _m Failure analysis memory unit MBLK Memory block BNC # 1 to BNC # n Bank

Claims (1)

[Claims] 1. A failure analysis memory comprising a plurality of memory blocks each having a number of banks corresponding to the number of phases of an interleave operation in a high-speed test mode, the number being equal to the number of memories to be tested in a high-speed mode. In the low-speed test mode, the failure data storage area of the memory under test is designated for each bank of each of the memory blocks constituting the failure analysis memory, and the fail data of the memory under test is stored in each bank. A semiconductor memory test apparatus characterized by being stored in a memory.