JPH10269508A - Magnetic recording and reproducing device and record compensation circuit applied thereto - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a high density recording of a magnetic recording and reproducing device by realizing a recording compensation msans capable of efficiently suppressing non-linear recording distortion caused by NLTS(non-linear transition shift) and PE(partial erasure) as well. SOLUTION: This device is a HDD(hard disk device) recording system provided with a distortion compensation circuit 5 operating recording compensation processing of fixed bit shift processing, so as to efficiently suppress non-linear recording distortion caused by NLTS and PE, to bit pattern recorded data in which two or more recorded bits corresponding to a magnetization transition position of digital magnetic recording succeed. When a bit pattern with two or more consecutive bits exists, the distortion compensation circuit 5 shift not only positions of a second bit and thereafter but also shifts a first bit position to an time-preceded position by a fixed quantity with respect to the original position.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic recording / reproducing apparatus for performing digital magnetic recording / reproducing such as a hard disk drive, and more particularly to a magnetic recording / reproducing apparatus having a recording compensation function.

[0002]

2. Description of the Related Art Conventionally, for example, a hard disk drive (HD)
A magnetic recording / reproducing apparatus such as D) magnetically records digital data on a disk serving as a recording medium by a magnetic head (hereinafter, simply referred to as a head) and reads recorded data from the disk to convert the original digital data. Reproduce.

It is known that a non-linear recording distortion (reproduction waveform distortion) occurs in HDDs when data is recorded magnetically on a disk. For this reason,
A recording distortion compensating circuit (recording compensating circuit) for compensating for recording distortion during data recording is provided. The distortion compensation circuit is a processing circuit that shifts a bit position corresponding to a position of magnetization transition on a disk by a predetermined amount when a bit pattern of encoded recording data is a continuous bit string, as described later.

[0004] The nonlinear recording distortion phenomenon includes a nonlinear bit shift (non-linear tr).
anion shift (hereinafter referred to as NLTS) and a partial erasure (partial er)
assure, hereinafter referred to as PE).

In the NLTS, the position (bit position) of a magnetic transition of a bit to be recorded later in a recording bit adjacent to each other having a magnetic transition is changed by the influence of a magnetic field from a previously recorded bit. Is shifted in the direction of the recorded bit.

[0006] Specifically, as shown in FIG.
In the continuous bit string, adjacent recording bit positions B1,
Assume that B2 is the original recorded bit position. In such a case, the NLTS changes the bit position B2 recorded with a time delay to the bit position B2s shifted in the direction of the bit position B1 recorded earlier. Such recording bit positions B1, B
FIGS. 2B and 2B show a recording current pattern without performing the recording distortion compensation processing, and FIG. 2C shows a recording current pattern after the recording distortion compensation processing is performed.

That is, the conventional distortion compensating circuit uses NLT in advance.
A bit shift by S is scheduled, and a bit position B2 to be recorded later in the continuous bit string is changed to a bit position B2d delayed (shifted) by a time T from the original position. As a result, when the data is actually magnetically recorded on the disk, the compensated bit position B2d is shifted by the shift amount due to the NLTS, and the original bit position B2d is shifted.
Will be recorded.

Therefore, in the conventional HDD, a distortion compensation amount (shift amount) corresponding to the electric delay amount T is obtained from the characteristics of the disk and the recording head and the recording conditions, and a data pattern in which a bit shift is likely to occur due to the NLTS. , A predetermined recording compensation (delay compensation) is performed to compensate for non-linear recording distortion during data recording.

In the above specific example, the case of recording data in which two recording bits are continuous has been described. However, the same applies to the case of recording data of a bit string in which three or more recording bits are continuous. That is, as shown in FIG.
In the recording data of a bit pattern such as “011101111010”, a bit string is assumed in which the recording bit “1” corresponds to the bit position of the magnetic transition and the recording bit “0” corresponds to the absence of the magnetic transition.

[0010] The distortion compensating circuit, as shown in FIG. 3C, applies a continuous three-bit sequence C1, C2, and C3 to the recording data pattern shown in FIG.
Delay compensation is performed on the bit positions C2 and C3 in C3 to change to the shifted bit positions C2d and C3d. Similarly, successive 4-bit strings D1, D2,
Delay compensation is performed on bit positions D2, D3, and D4 among D3 and D4, and shifted bit positions D2d,
Change to D3d, D4d.

As described above, the NLTS recording compensation is realized by executing the bit shift by the delay processing on the bit positions of the second and subsequent bits with respect to the bit string in which the recording bit of “1” is normally continuous. doing.

On the other hand, PE is a phenomenon in which a portion between adjacent magnetic transitions magnetically interferes with each other, so that the state is changed from a sharp magnetic transition state to a collapsed state. When such a PE occurs, the amplitude characteristic of the reproduction signal waveform read from the head during data reproduction deteriorates, which causes a reproduction error.

[0013]

As described above, the HD
In a digital magnetic recording / reproducing apparatus such as D, when recording data, NLTS or PE nonlinear recording distortion occurs.
In particular, due to the increase in the linear density of the disk, the influence of nonlinear recording distortion is large, and in order to realize accurate data reproduction, the recording compensation processing reduces the nonlinear recording distortion (waveform distortion of the reproduced waveform). It is necessary to plan.

Conventionally, as described above, an effective system has been developed as a recording compensation system for suppressing non-linear recording distortion due to NLTS. However, P
An effective method for suppressing the recording distortion of nonlinearity due to E has not been developed. Conventionally, during data playback,
There has been proposed a method of performing compensation in a reproduction system in which a gain is changed in accordance with a bit interval and an increase in output (deterioration in amplitude) due to PE is lifted and compensated. However, a good S / N ratio cannot be obtained, and this is not always an effective method.

Therefore, an object of the present invention is to provide non-linear recording distortion (reproduction waveform distortion) due to PE together with NLTS.
It is an object of the present invention to realize a recording compensating means capable of effectively suppressing the increase in recording density of a magnetic recording / reproducing apparatus.

[0016]

SUMMARY OF THE INVENTION According to the present invention, there is provided a method for recording data having a bit pattern in which two or more consecutive recording bits corresponding to a magnetic transition position of digital magnetic recording are recorded by a NLTS and a PE. The magnetic recording / reproducing apparatus is provided with a recording compensating means for performing a recording compensation process as a predetermined bit shift process so as to effectively suppress the recording distortion of the magnetic recording / reproducing apparatus.

More specifically, the recording compensating means, when there is a bit pattern in which two or more recording bits corresponding to the magnetization transition position of digital magnetic recording exist in the recording data, the second and subsequent bits. The position is shifted by a predetermined amount to a position that is temporally delayed from the original position, and the bit position of the first bit is shifted by a predetermined amount to a position that temporally precedes the original position.

Here, the non-linear recording distortion due to the NLTS is a non-linear distortion generated in the time axis direction of the reproduction signal waveform with respect to the bit string of the recording data. In contrast, P
The non-linear recording distortion due to E is a non-linear distortion generated in the amplitude direction of the reproduction signal waveform. For this reason, conventionally, N
In order to suppress the non-linear recording distortion due to the LTS, a method of performing recording compensation processing in the time axis direction (bit position direction) is adopted. In contrast, the present invention provides
In order to suppress non-linear recording distortion due to PE, recording compensation processing is performed in the time axis direction.

The present invention is based on the principle that the amplitude of the reproduced signal waveform increases when the recording bit interval is generally increased in a region where reproduced waveform interference occurs.
Is compensated by increasing the interval between recording bits. By the way, in the signal processing of the reproducing system of the magnetic recording / reproducing apparatus, data detection is performed assuming a linear system. As a reproduction signal waveform, a waveform obtained as a linear addition of isolated bit waveforms corresponding to isolated bits of recording data is an ideal waveform. The present invention suppresses the difference between the actual reproduced signal waveform and the ideal waveform by shifting the recording bit position, thereby obtaining a reproduced signal waveform close to the ideal waveform, and having an excellent S / N ratio. It is to realize a data reproducing operation.

Further, the present invention is a magnetic recording / reproducing apparatus having a self-adjustment function for calculating parameters required for the recording compensation processing by the apparatus itself. That is, the self-adjustment function is an optimal shift calculated by using a method based on error rate evaluation or a method based on waveform matching based on a reproduced signal waveform obtained by recording and reproducing test data set in advance on a recording medium. This function uses the amount as a parameter necessary for the recording compensation processing. With a device having such a self-adjustment function, an optimal shift amount can be set as a parameter necessary for the recording compensation process. It is possible to realize a simple recording compensation process.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 shows an H related to the first embodiment.
FIG. 2 is a block diagram illustrating a DD recording system, and FIG. 2 is a block diagram illustrating a configuration of a distortion compensation circuit according to the first embodiment.
Is a timing chart for explaining the recording compensation operation of the embodiment. (Configuration of HDD Recording System)
As shown in FIG. 1, a recording system having a disk 1, a spindle motor 2, a recording head 3, a recording amplifier 4, and a distortion compensation circuit (recording compensation means) 5 is provided. Further, a reproduction system including a reproduction head 6, a reproduction amplifier 7, and a reproduction signal processing circuit 8 is provided. Here, an inductive type thin film head is used as the recording head 3 and an MR thin film head is used as the reproducing head 6.
A recording / reproducing separation type head using a head is assumed. Incidentally, the recording head 3 may be a single inductive type thin film head which also serves as a reproducing head. The heads 3 and 6 are supported by a head actuator mechanism 9 and are configured to rotate and move in the radial direction of the disk 1. (Structure of distortion compensation circuit) Distortion compensation circuit 5 of the embodiment
Is a bit pattern determination circuit 11, as shown in FIG.
It has a shift amount selection circuit 12, a shift amount table 13, an addition circuit 14, a delay circuit 15, and a variable shift circuit 16. The function of the distortion compensating circuit 5 is that the position of the first bit of a continuous bit sequence (a continuous bit sequence of “1” corresponding to the magnetization transition position of digital magnetic recording) in the bit pattern of the encoded recording data WDa is Is shifted forward (a position preceding in time) from the recording timing position, and the position after the second bit is shifted backward (a position delayed in time) from the original recording timing position. Hereinafter, each component of the distortion compensation circuit 5 will be described.

The bit pattern determination circuit 11 receives the recording data WDa and determines whether the bit pattern is an isolated bit or a continuous bit string in a predetermined number of bits. Here, as described above, the bit pattern of the continuous bit string is assumed to be a continuous bit string of “1” corresponding to the magnetization transition position of digital magnetic recording.
The shift amount selection circuit 12 includes a bit pattern determination circuit 11
Based on the determination result, "0" is output for an isolated bit, and the shift amount table 13 is output for a continuous bit string.
See The shift amount table 13 previously stores shift amount data corresponding to the number of consecutive bits and the order of bit positions (how many bits are in which bit of a continuous bit sequence) in a continuous bit sequence. The shift amount data includes positive and negative sign codes indicating the shift direction. Here, the “negative” sign code is forward in the time axis direction,
That is, it indicates the direction of the bit position that precedes in time,
Conversely indicates the direction of the bit position that is delayed in time.

In the case of the first bit of the continuous bit string, the shift amount selecting circuit 12 obtains from the table 13 shift amount data D1 indicating the shift amount in the shift direction (negative sign code) ahead of the original recording position. Output. For the second and subsequent bits, the shift amount data D1 indicating the shift amount in the shift direction (positive code code) behind the original recording position is obtained from the table 13 and output.

The adder 14 adds the constant basic shift amount (delay amount) D0 and the output D1 of the shift amount selection circuit 12 and outputs the sum (D0 + D1) of the shift amount D2 to the variable delay circuit 16. Output. Here, the delay circuit 15
Transfers the input recording data WDa to the variable shift circuit 16 with a predetermined delay in accordance with the processing time from the bit pattern determination circuit 11 to the addition circuit 14.
The variable shift circuit 16 outputs the recording data WDb obtained by shifting the bit sequence of the recording data WDa transferred from the delay circuit 15 by the shift amount (delay amount) D2 output from the adding circuit 14 for each individual bit. (Recording Compensation Operation) Hereinafter, the recording compensation operation of the present embodiment will be described with reference to FIGS.

As shown in FIG. 3A, "0"
The recording data WDa having a bit pattern such as “1011010111010” is recorded on the disk 1 by the recording head 3.
Assume to record above. Here, the recording bit “1” corresponds to the bit position of the magnetic transition, and the recording bit “0” corresponds to the absence of the magnetic transition. FIG.
5 shows a recording current pattern (output of the recording amplifier 4) according to the bit pattern of the recording data WDa.

FIG. 3C shows the bit positions written at the original recording timing when the recording data WDa is recorded. That is, the positions of the isolated bits S1, S2,
This is a recording timing determined based on S3. The isolated bit positions S1, S2, and S3 are regarded as not shifting.

The distortion compensating circuit 5 of the present embodiment is similar to that of FIG.
As shown in (D), the recording data WDb in which the bit position of the original recording timing is shifted by a predetermined shift amount (recording is compensated) is output. For example, the bit pattern “E” of a two-bit string that is a continuous bit string of the recording data WDa
1, E2 ”and the bit pattern“ F
When “1, 1, F2, F3” is detected, the distortion compensating circuit 5 shifts the first bit “E1 and F1” forward from the original bit position by the operation of the components 12 to 16 described above. . That is, as shown in FIG. 3D, the first bits “E1 and F1” are the bit positions of “E1s, F1s”, respectively. As a result, the isolated bit position S
1, S2 and the bit positions E1, F1 of the first bit are “S1-E1s) and“ S2-F1s ”, respectively.
, Which is shorter than the original interval.

On the other hand, "E2, F2, F3" from the second bit onward in the continuous bit string are shifted backward (time delayed) from the original bit positions. That is, as shown in FIG. 4D, the second and subsequent bits “E2, F2,
“F3” is the bit position of “E2d, F2d, F3d”.

Thus, the recording data WDb whose nonlinear waveform distortion has been compensated for by the distortion compensating circuit 5 is sent to the recording amplifier 4, and a recording current pattern shown in FIG. 3D is generated. According to this recording current pattern, digital magnetic data of a bit pattern corresponding to the encoded data shown in FIG. At this time, the distortion compensating circuit 5 can suppress the non-linear recording distortion due to the NLTS, as described above, by shifting each bit position after the second bit of the continuous bit string.

Further, by shifting the first bit (the leading bits E1 and F1 of the continuous bit string) forward as well as the bit positions of the second and subsequent bits, the position of the isolated bit position (S1, S2) can be determined. The interval is reduced. In other words, the bit interval between the first bit and the second and subsequent bits is
Will increase. That is, the original bit interval (for example, the interval between E1 and E2) becomes the increased bit interval (the interval between E1d and E2d) by the recording compensation processing by both shifts.

Here, it has been confirmed that normally, when the recording bit interval is increased, the amplitude of the reproduced signal waveform is increased. Therefore, the present invention increases the recording bit interval of a continuous bit string by shifting the bit position of the first bit forward and shifting the second and subsequent bits to a greater extent than when only NLTS is compensated. Consequently P
The amplitude deterioration due to E can be compensated.

The shift amount of each recording bit position is determined by, for example, a waveform matching method. As a specific example, a procedure of waveform matching for a signal pattern in which two bits are continuous (a dibit pattern) will be described with reference to FIGS.

First, as shown in FIG. 4, the recording signal shown in FIG. 4A is recorded on the disk 1 so that the reproduced signal waveform shown in FIG. That is, a signal having a sufficiently low density that does not cause inter-bit interference is recorded. Then, based on the reproduced signal waveform reproduced from the disk 1, FIG.
As shown in (D), positive and negative isolated waveforms are obtained.

FIG. 5 is a diagram showing the process of dibit waveform matching. 2 bits (B) as shown in FIG.
(B), a test signal is generated by shifting each recording bit position by the shift amounts T1 and T2, as shown in FIG. Here, in practice, the bit position is examined with reference to the isolated bit at the time of reproduction. Therefore, as shown in FIG. 6A, for example, a test signal in which an isolated bit is inserted between dibits is used. .

This test signal is recorded on the disk 1, and
The reproduction head 6 obtains a reproduction signal waveform as shown in FIG. Here, the reproduced waveform signal corresponding to the recording signal including the isolated bits shown in FIG. 6A is as shown in FIG. When a test signal as shown in FIG. 6A is used, the isolated bit reproduction waveform is not the low recording density reproduction signal waveform of FIG. 4B but the isolated signal waveform of FIG. 6B. It may be obtained from the bit part.

The difference between the thus-obtained reproduced signal waveform of the test signal and the ideal waveform (a waveform assuming that there is no nonlinear waveform distortion such as NLTS or PE) is examined. FIG.
(D) shows a comparison state between the reproduced waveform (solid line) of the test signal and the ideal waveform (dotted line). In this comparison state, FIG.
As shown in (D), ideal waveforms at several points on the time axis (for example, points X2, X5 where the ideal waveform takes a peak value and points X1, X3, X4 and X6 where the ideal waveform takes a half value of the peak value). Is evaluated by the root mean square P of the difference between the output value and the output value of the reproduced waveform. FIG. 11E is a graph showing the difference between the reproduced waveform and the ideal waveform, and the vertical axis is enlarged for easy understanding of the difference.

FIG. 7A shows an ideal waveform (dotted line) and a reproduced waveform (solid line) in an actual measurement example. FIG. 7 (B)
Is the difference between the reproduced waveform and the ideal waveform in the actual measurement example,
This is shown as an output value with respect to the time axis.

Then, by changing the shift amounts T1 and T2 of the recording bit positions shown in FIG. 5B, the recording and reproduction of the test signal are repeated, and the comparison between the reproduced waveform of the test signal and the ideal waveform is repeated. Thus, the values of the shift amounts T1 and T2 are set so that the root mean square P of the differences between the waveforms is minimized. The point at which the root mean square of the difference between the output value of the reproduced waveform of the test signal and the output value of the ideal waveform is obtained is the above point (X1 to
6) and may be set so that the integrated value of the square error in a certain range including the dibit is minimized. Further, a method of setting the position of each recording bit so as to minimize the reproduction error rate may be used.

As described above, even in a signal pattern in which three or more bits are continuous, the first bit position is shifted forward, and the second bit and subsequent positions are appropriately shifted, so that the nonlinearity caused by the PE is increased. Recording distortion can be suppressed. In this case, the shift amount of each recording bit position is also the shift amount of each recording bit position (T1, T2,
T3,...) Can be set as parameters by the waveform matching method. Also in this case, the position of each recording bit may be set so that the reproduction error rate is minimized.

As described above, according to the present embodiment, by shifting the bit position of the first bit as well as the second bit and subsequent bits of the continuous bit string of the recording data, the nonlinearity of the reproduced waveform by the NLTS is shifted. Not only distortion,
It is possible to reduce the influence of the nonlinear distortion of the reproduced waveform due to the PE. Therefore, even when a head or a disc having a large PE characteristic is used, it is possible to reduce the influence of the nonlinear distortion of the reproduction waveform and improve the reproduction error rate.

In the conventional recording compensation system, compensation processing is performed to shift only the bit positions of the second and subsequent bits in a continuous bit string. As shown in FIG. 12A, the reproduced signal waveform in the conventional recording compensation method becomes a solid line reproduced waveform with respect to a dotted ideal waveform, and is compensated so that the bit positions are substantially coincident. That is, NLT
Bit shift due to S is compensated. FIG.
FIG. 7 is a waveform diagram for a dibit pattern (a bit pattern in which two bits are close to each other) as a continuous bit string.

However, as shown in FIG.
In contrast to the dotted ideal waveform, the solid waveform reproduced waveform shows a decrease in the amplitude value (reproduced output reduction), which is considered to be the effect of PE. Here, in the conventional recording compensation method, the position after the second bit is shifted backward to increase the interval between the two bits, and as shown in FIG. It is also possible to increase the amplitude value).
However, although the reduction of the amplitude value can be suppressed, a problem occurs that the bit position deviates from the ideal waveform this time.

Accordingly, the present invention shifts the bit position of the first bit (B1 in FIG. 5A) forward and removes the second bit in order to simultaneously remove each waveform distortion in the amplitude direction and the time axis direction. By the recording compensation processing for shifting the position after the bit backward, it is possible to make the reproduced waveform represented by the solid line substantially coincide with the ideal waveform represented by the dotted line, as shown in FIG. That is, as compared with the cases shown in FIGS. 12A and 12B, it is possible to reduce each difference between the reproduced waveform and the ideal waveform in the amplitude direction and the time axis direction.

In other words, in the present invention, if the amplitude increase caused by increasing the recording bit interval is offset from the amplitude deterioration due to the PE, the recording bit position is shifted to correct in the time axis direction. , Can be substantially corrected in the amplitude direction. Conventionally, PE
A method for compensating for the amplitude deterioration due to the above has been developed in the reproduction system. However, in the present invention, since the compensation method is used at the time of recording, the S / N at the time of reproduction is relatively good.

In the present embodiment, a recording compensation method in which the first bit is shifted forward with respect to the nonlinear distortion caused by PE is described. However, in practice, waveform distortions other than NLTS and PE, such as hard
There are phenomena such as easy transition shift. With respect to such a phenomenon, the difference between the reproduced waveform and the ideal waveform may be smaller when the first bit position is shifted backward or the position after the second bit is shifted forward. . Even in such a case, the distortion compensation circuit 5 of the present embodiment shifts an arbitrary bit of the continuous bit sequence in any of the forward and backward directions by using a code code indicating the shift direction of the shift amount data stored in the shift amount table 13 in advance. Therefore, it is possible to realize an optimum recording compensation operation based on the factor of the waveform distortion. (Second Embodiment) The second embodiment optimizes the shift amount of the recording bit position necessary for the shift processing of the distortion compensation circuit 5 which is the recording compensation circuit in the HDD related to the first embodiment. This realizes a self-adjustment function for setting a value.

The configuration and operation of this embodiment will be described below with reference to FIG. As shown in FIG. 9, the HDD of this embodiment includes a disk 1, a spindle motor 2, a recording / reproducing head 3, a recording amplifier 4, a distortion compensating circuit 5, a reproducing amplifier 7,
A test pattern control circuit 9, a test signal generation circuit 10,
AGC amplifier Amplifier 21, gain controller 22, A
/ D conversion circuit 23, timing control circuit 24, waveform data separation circuit 31, isolated waveform memories 32A and 32B, waveform memory 33, waveform shift circuits 34A and 34B, waveform synthesis circuit 35, waveform comparison circuit 36, and shift control circuit 37
Having.

The test pattern control circuit 9 outputs to the test signal generation circuit 10 and the shift control circuit 37 information (test pattern information) indicating the number of continuous bits of the test signal and the shift amount for each bit. According to the test pattern information, the test signal generation circuit 10
A test signal as shown in FIG. The test signal is amplified by the recording amplifier 4 and supplied to the head 3, so that the test signal is recorded on the disk 1 as a magnetization pattern.

Next, in the reproducing operation, the test signal, which is the magnetization pattern recorded on the disk 1,
And is amplified by the reproduction amplifier 7 and further sent to the A / D conversion circuit 23 and the timing control circuit 24 after the output level is kept constant by the AGC amplifier 21. Here, the gain controller 2
Reference numeral 2 has a function of monitoring the output level of the reproduction signal from the AGC amplifier 21 and applying feedback to the AGC amplifier 21 to keep the output level constant.

The timing control circuit 24 creates a timing signal on the basis of an isolated waveform in the reproduced output signal from the AGC amplifier 21 and supplies it to the A / D conversion circuit 23 and the waveform data separation circuit 31. The A / D conversion circuit 23 converts an analog signal, which is a reproduction output signal from the AGC amplifier 21, into a digital signal using the timing signal from the timing control circuit 24 as a trigger, and outputs the digital signal to the waveform data separation circuit 31.

The waveform data separation circuit 31 stores an isolated bit waveform (digital data) convex on the plus side in the isolated waveform memory 32A, stores an isolated bit waveform convex on the minus side in the isolated waveform memory 32B, and further continuously. The bit waveform is stored in the waveform memory 33. Further, the waveform shift circuits 34A and 34B respectively control the isolated waveform memory 32 according to the shift amount information input from the shift control circuit 37.
A, the waveform read from 32B is shifted in the time axis direction,
Output to the waveform synthesis circuit 35.

The waveform synthesizing circuit 35 includes a waveform shifting circuit 34
A and 34B are combined and output to the waveform comparison circuit 36. The waveform synthesizing circuit 35 can also synthesize a waveform having three or more consecutive bits by inputting and synthesizing a plurality of waveforms having different shift amounts from the respective waveform shift circuits 34A and 34B. The waveform comparison circuit 36 compares the synthesized waveform from the waveform synthesis circuit 35 with the input waveform (continuous bit waveform) from the waveform memory 33, calculates the square error thereof, and outputs the square error to the test pattern control circuit 8.

The test pattern control circuit 8 stores the square error from the waveform comparison circuit 36 and outputs information obtained by changing the shift amount of each bit of the test pattern to the shift control circuit 37. The shift control circuit 37 outputs shift amount information based on the information to the waveform shift circuits 34A and 34B. The waveform shift circuits 34A and 34B shift the waveform read from the isolated waveform memories 32A and 32B in the time axis direction according to the new shift amount information, and output the resultant to the waveform synthesis circuit 35. The waveform synthesis circuit 35 includes a waveform shift circuit 34A,
The waveform comparison circuit 36 combines the waveforms input from the
Output to The waveform comparing circuit 36 compares the synthesized waveform from the waveform synthesizing circuit 35 with the input waveform (continuous bit waveform) from the waveform memory 33, calculates the square error thereof, and outputs the squared error to the test pattern control circuit 9.

By repeating the comparison between the composite waveform obtained by changing the shift amount of each bit and the actual continuous bit waveform stored in the waveform memory 33 in this manner, the composite waveform is minimized so that the square error is minimized. The shift amount of each bit is adjusted. As a result, a difference between the shift amount of each bit position of the test signal to be recorded and the shift amount of each bit position obtained by waveform matching with respect to a reproduced waveform in which the test signal is recorded and reproduced is obtained.

The test pattern control circuit 9 adjusts the shift amount of each bit of the test signal based on the difference so that each bit of the reproduced waveform is at a correct position (a bit position when there is no nonlinear distortion). The adjusted test pattern information is output to the test signal generation circuit 10. The test signal generation circuit 10 generates a new test signal according to the new test pattern information. Thereafter, the processing for recording, reproducing and waveform matching of the test signal is repeated in the same manner to converge the shift amount of each bit to an optimum value. The converged shift amount of each bit is calculated by the distortion compensating circuit 5.
, The distortion compensation circuit 5 can always execute the recording compensation processing according to the optimum shift amount data.

[0055]

As described above in detail, according to the present invention, the first bit and the second bit of the continuous bit sequence
The recording compensating means for shifting the bit and subsequent bits by a predetermined shift amount in the time axis direction set in advance, especially NL
The nonlinear waveform distortion due to the PE and the nonlinear waveform distortion due to the TS can be effectively suppressed. Therefore, when data is recorded on the disk, it is possible to record a magnetization pattern in which the occurrence of nonlinear distortion is suppressed. As a result, it is possible to obtain a reproduced waveform close to an ideal waveform with suppressed waveform distortion during data reproduction, and to realize a reproducing operation with an excellent reproduction error rate. If the reproduction error rate is the same, higher-density data recording can be realized.
It becomes easy to increase the recording density of a magnetic recording / reproducing apparatus such as D.

[Brief description of the drawings]

FIG. 1 is an exemplary block diagram showing a main part of an HDD according to a first embodiment of the present invention;

FIG. 2 is an exemplary block diagram showing the configuration of a distortion compensation circuit according to the first embodiment;

FIG. 3 is a timing chart for explaining a recording compensation operation related to the embodiment.

FIG. 4 is an exemplary view for explaining an isolated bit waveform related to the embodiment;

FIG. 5 is an exemplary view for explaining reproduction waveform matching related to the embodiment;

FIG. 6 is a view showing test signals related to the embodiment.

FIG. 7 is an exemplary view for explaining actual reproduction waveform matching related to the embodiment;

FIG. 8 is a block diagram showing a main part of an HDD according to a second embodiment of the present invention.

FIG. 9 is a timing chart for explaining a conventional recording compensation method for an NLTS.

FIG. 10 is a timing chart for explaining a conventional recording compensation method for an NLTS.

FIG. 11 is a reproduction signal waveform diagram for explaining the effect of the recording compensation operation related to the first embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Disk 2 ... Spindle motor 3 ... Magnetic head (recording head or recording / reproduction head) 4 ... Recording amplifier 5 ... Distortion compensation circuit (recording compensation circuit) 6 ... Reproduction head 7 ... Reproduction amplifier 8 ... Reproduction signal processing circuit 9 ... Test Pattern control circuit 10 Test signal generation circuit 11 Bit pattern determination circuit 12 Shift amount selection circuit 13 Shift amount table 14 Addition circuit 15 Delay circuit 16 Variable shift circuit 21 AGC amplifier 22 Gain controller 23 A / D conversion circuit 24 timing control circuit 31 waveform data separation circuit 32A isolated waveform memory 32B isolated waveform memory 33 waveform memory 34A waveform shift circuit 34B waveform shift circuit 35 waveform synthesis circuit 36 waveform comparison circuit 37 ... Shift control circuit

Claims (7)

[Claims] 1. A magnetic recording / reproducing apparatus for performing digital magnetic recording / reproducing on a recording medium by a head, comprising: means for generating recording data to be recorded on the recording medium during a data recording operation; When there is a bit pattern in which two or more recording bits corresponding to the magnetization transition position of digital magnetic recording exist, the first bit position and the second and subsequent bit positions are set with respect to the original positions. A magnetic recording / reproducing apparatus comprising: a recording compensation means for shifting a predetermined amount in a time axis direction set in advance based on a waveform distortion effect of a reproduced waveform. 2. The magnetic recording / reproducing apparatus according to claim 1, wherein the recording data is a recording current pattern. 3. The recording compensating means, when a bit pattern in which two or more recording bits corresponding to a magnetization transition position of digital magnetic recording exist in the recording data is present, a bit position after a second bit. Is shifted by a predetermined amount to a position delayed in time with respect to the original position, and the bit position of the first bit is shifted by a predetermined amount to a position temporally preceding the original position. 2. The magnetic recording / reproducing apparatus according to claim 1, wherein: 4. The recording compensating means includes means for determining whether a bit pattern of the recording data is an isolated bit or a continuous bit string; and in the case of the continuous bit string, a shift amount of a bit position according to the order of the bit string. 4. The magnetic recording / reproducing apparatus according to claim 1, further comprising: means for determining a shift direction. 5. A recording compensation circuit which is applied to a magnetic recording / reproducing apparatus for performing a digital magnetic recording / reproducing operation on a recording medium by a head, and performs recording compensation processing of recording data for recording on the recording medium. Determining means for determining whether the bit pattern of the recording data generated at the time of the recording operation is an isolated bit or a continuous bit sequence; and a shift amount corresponding to the order of the bit sequence at the bit position corresponding to the magnetization transition position in digital magnetic recording. Shift amount table means for holding table information indicating the shift direction and the shift direction; and, based on the result of the determination by the determination means, the bit pattern of the recording data is a continuous bit string. The bit position is shifted by a predetermined shift amount in the shift direction for advancing the original position in time with respect to the original position. A compensating means for compensating recording data of a bit pattern shifted by a predetermined shift amount in a shift direction for temporally delaying a bit position of a second bit or later with respect to an original position. . 6. The recording compensation according to claim 5, wherein said shift amount table means holds, for each successive bit number, table information indicating a shift amount and a shift direction corresponding to the order of a bit string. circuit. 7. An optimum shift amount calculated based on a reproduced signal waveform obtained by recording and reproducing test data set in advance on a recording medium is used as a shift amount required for a compensation process performed by the recording compensating means. 7. The magnetic recording / reproducing apparatus according to claim 1, wherein the apparatus has a self-adjustment function.