JPH10262248A - Micro controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a micro controller by which image data are compressed and extended inexpensively at a high speed. SOLUTION: A micro controller 2 of an image processing unit 1 that applies compression processing to image data is provided with a conversion execution means 5 that converts image data transferred via an internal bus 3 into a DCT coefficient. The conversion execution means 5 is provided with an image data storage area 6 to which image data are inputted, an intermediate value storage area 7 to which intermediate data in the conversion processing are stored, a conversion coefficient storage area 8 to which the DCT efficient is stored and together with a conversion circuit 9 that stores the intermediate data resulting from applying conversion processing to the image data in the area 6 to the area 7 and stores the DCT coefficient resulting from applying conversion processing to the intermediate data in the area 7 to the area 8. Then a data transfer means 4 transfers the DCT coefficient stored in the conversion coefficient storage area 8 during the conversion processing to the image data and transfers the image data in which the conversion processing is applied next during the conversion processing for the intermediate data to the image data storage area 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a microcontroller provided in an image processing apparatus for compressing and expanding still image data.

In recent years, image information processing apparatuses such as cameras and videos have begun to be digitized, and compression / expansion processing of digital images has become an important basic technology. And in the microcontroller provided in the image processing device,
There is a demand for a reduction in processing time in the compression / decompression processing.

[0003]

2. Description of the Related Art In recent years, cameras and videos have been digitized, and the still image compression / expansion technology used in such digital still cameras is called JPEG. The JPEG processing is performed using software or dedicated hardware. Will be The JPEG processor, which is dedicated hardware, can perform JPEG processing at high speed, but requires a considerable circuit scale, which increases the cost of the entire system such as a camera. For this reason, inexpensive systems often include a microcontroller and perform JPEG processing by software.

[0004]

However, the JPE
Since the G processing requires a large amount of arithmetic processing or memory operation, it is difficult to obtain a desired speed by processing using only software. For example, in a digital still camera or the like, when the shutter is pressed, the captured image data becomes J
After being compressed by PEG, it is stored in the memory. Therefore, if the compression process takes a long time, it takes a long time (for example, about 5 to 10 seconds) until the shutter can be pressed next time, and it becomes impossible to wait.

[0005] Some digital cameras are provided with a continuous shooting mode for continuously capturing images while the shutter is pressed. The continuous shooting mode is a motion JPEG (Motion JPEG) that continuously compresses or decompresses color images based on JPEG and records or reproduces moving images.
It is performed by In this case, if a predetermined speed (for example, 30 frames per second) cannot be obtained in the compression / decompression processing,
Necessary image data cannot be recorded, or the movement becomes jerky and difficult to see.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a microcontroller capable of performing inexpensive and high-speed compression and decompression processing of image data.

[0007]

FIG. 1 is a diagram illustrating the principle of the present invention. That is, the microcontroller 2 is used in the image processing apparatus 1 that performs a compression process on image data. The microcontroller 2 is connected to the internal bus 3 and transfers data via the internal bus 3. And a conversion execution unit 5 that performs cosine conversion and converts the data into DCT coefficients required for compression processing. The transformation execution means 5 includes an image data storage area 6 for inputting image data, an intermediate value storage area 7 for storing intermediate data in the conversion processing, and a transform coefficient storage area 8 for storing DCT coefficients. In addition, the result of performing the conversion process on the image data in the image data storage region 6 is stored as intermediate data in the intermediate value storage region 7, and the result of performing the conversion process on the intermediate data in the intermediate value storage region 7 As a DCT coefficient, a transform coefficient storage area 8
Is provided. The data transfer means 4 transfers the DCT coefficients stored in the transform coefficient storage area 8 during the conversion processing on the image data, and then performs the conversion processing on the image data storage area 6 during the conversion processing on the intermediate data. Transfer image data.

According to a second aspect of the present invention, in the microcontroller according to the first aspect, the conversion executing means includes:
The image data is subjected to a two-dimensional discrete cosine transform, and the conversion circuit is configured to perform a one-dimensional discrete cosine transform. The conversion circuit is configured to perform a one-dimensional discrete cosine transform on the image data in the image data storage area. The result of the cosine transform process is stored in the intermediate value storage area as the intermediate data, and the result of the one-dimensional discrete cosine transform on the intermediate data in the intermediate value storage area is stored in the transform coefficient storage area as the DCT coefficient. I did it.

According to a third aspect of the present invention, in the microcontroller according to the first or second aspect, a coefficient memory in which a quantization table including quantization coefficients used for quantization processing is stored in advance, and the quantization coefficient And a quantization processing unit that quantizes the DCT coefficient transferred from the transform coefficient storage area based on the DCT coefficient. The transform execution unit compares the DCT coefficient with the quantized coefficient. A quantization prediction circuit for predicting whether or not the code data has a predetermined value by a quantization process based on a result, and adding information to the code data having the predetermined value; Is based on information added to the DCT coefficient, and when the DCT coefficient is a predetermined value, the D
The quantization processing for the CT coefficients is not executed.

According to a fourth aspect of the present invention, in the microcontroller according to the third aspect, the quantization prediction circuit inputs the DCT coefficient, and expands and outputs the least significant bit of the DCT coefficient. Unit, a comparing unit that compares the quantized coefficient stored in the quantized coefficient storage area with the output data of the bit operation unit, and outputs a result of the comparison.
And a data generation unit for storing in the conversion coefficient storage area in addition to the coefficients.

According to a fifth aspect of the present invention, in the microcontroller according to any one of the first to fourth aspects,
A first address signal generating a first address signal corresponding to a zigzag scanning method for rearranging the two-dimensional DCT coefficients in a one-dimensional manner;
And the DCT coefficients are stored in the transform coefficient storage area in a zigzag scanning order based on the first address signal.

According to a sixth aspect of the present invention, in the microcontroller according to the fifth aspect, a second address generating circuit for generating a second address signal in the order of calculating the DCT coefficients, and the first address signal And a switching circuit for switching between the second address signal and the second address signal, wherein the DCT coefficient is stored in the conversion coefficient storage area based on the switched first or second address signal.

According to a seventh aspect of the present invention, in the microcontroller according to any one of the third to sixth aspects,
The coefficient memory previously stores a plurality of tables corresponding to the type of image, and the conversion executing means divides the two-dimensional DCT coefficient into a plurality of regions, and stores each DCT coefficient and its DCT coefficient. A table determination circuit that compares a threshold value set corresponding to each region to be stored and stores the number of DCT coefficients larger than the threshold value for each region, wherein the quantization execution unit is stored for each region. One of the plurality of tables is selected based on the calculated number, and the quantization processing is performed on the DCT coefficients using the selected table.

According to an eighth aspect of the present invention, in the microcontroller according to the seventh aspect, the table determination circuit comprises: a threshold register for storing a threshold set for each of a plurality of areas of the divided code data; A comparator that compares the input code data with a threshold stored in a threshold register of an area where the code data exists, and outputs a signal when the code data is larger than the threshold based on the comparison result; , Provided in correspondence with the plurality of areas, and configured to count up based on a signal from the comparator.

According to the first aspect of the present invention, the conversion circuit stores the intermediate data obtained by performing the discrete cosine transform on the image data input to the image data storage area in the intermediate value storage area. Access to the transform coefficient storage area is not performed. At this time, the data transfer means transfers the DCT coefficients stored in the transform coefficient storage area. When the transform circuit stores the DCT coefficients obtained by performing the discrete cosine transform on the intermediate data in the intermediate value storage area in the transform coefficient storage area, the image data storage area is not accessed. At this time, the data transfer means stores the next image data in the image data storage area. Therefore, data transfer to the image data storage area or the transform coefficient storage area and the discrete cosine transform are performed in parallel.

According to the second aspect of the present invention, the conversion executing means performs two-dimensional discrete cosine transformation on the image data, and the conversion circuit performs one-dimensional discrete cosine transformation. Then, the conversion circuit stores the result of the one-dimensional discrete cosine transform processing on the image data in the image data storage area as intermediate data in the intermediate value storage area, and performs one-dimensional discrete cosine transform on the intermediate data in the intermediate value storage area. Is stored in the transform coefficient storage area as a DCT coefficient.

According to the third aspect of the present invention, a quantization table including quantization coefficients used for quantization processing is stored in the coefficient memory in advance. The quantization processing means is configured to output the D transferred from the transform coefficient storage area based on the quantization coefficient.
Quantize the CT coefficients. Then, the conversion executing means includes D
A CT that compares a CT coefficient with a quantized coefficient, predicts whether or not code data has a predetermined value by a quantization process based on the comparison result, and adds information to the code data having a predetermined value. A quantization prediction circuit is provided, and the quantization processing means does not execute the quantization processing on the DCT coefficient based on the information added to the DCT coefficient when the DCT coefficient has a predetermined value.

According to the fourth aspect of the present invention, the quantization prediction circuit receives the DCT coefficient, expands the least significant bit of the DCT coefficient and outputs the result, and the quantization operation is stored in the quantization coefficient storage area. A comparison unit that compares the quantized coefficient with the output data of the bit operation unit and outputs the comparison result, and a data generation unit that adds information bits based on the comparison result to the DCT coefficient and stores the DCT coefficient in the transform coefficient storage area It is composed of

According to the fifth aspect of the present invention, the two-dimensional D
A first address generation circuit for generating a first address signal corresponding to a zigzag scanning method in which CT coefficients are arranged one-dimensionally is provided, and a zigzag based on the first address signal is provided in a conversion coefficient storage area. DCT coefficients are stored in the order of scanning.

According to the sixth aspect of the present invention, the second address generating circuit for generating the second address signals in the order of calculating the DCT coefficients, and switching between the first address signal and the second address signal. A DCT coefficient is stored in the transform coefficient storage area based on the switched first or second address signal.

According to the seventh aspect of the present invention, a plurality of tables corresponding to the types of images are stored in the coefficient memory in advance, and the two-dimensional DCT coefficients are divided into a plurality of regions by the conversion executing means. And a table determination circuit that compares each DCT coefficient with a threshold set corresponding to an area including the DCT coefficient, and stores the number of DCT coefficients larger than the threshold for each area. Then, the quantization execution means selects one of the plurality of tables based on the number stored for each region, selects and performs quantization processing on the DCT coefficients using the table.

According to the eighth aspect of the present invention, the table determination circuit includes: a threshold register for storing a threshold set for each of a plurality of regions of the divided code data; input code data; Comparing the threshold value stored in the threshold value register of the region where there is, and a comparator that outputs a signal when the code data is larger than the threshold value based on the comparison result, provided for a plurality of regions, And a counter that counts up based on a signal from the comparator.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

As shown in FIG. 2, an image information processing apparatus 10 such as a digital still camera has a CC as an image sensor.
D11 is provided. The CCD 11 includes a conversion circuit 12
Is connected to the external bus 13 via the. External bus 13
Includes a microcontroller (hereinafter referred to as a microcomputer)
14, a ROM 15, a frame memory 16, and a flash memory 17 are connected.
Further, an LCD 19 as a display element is connected to the external bus 13 via a drive circuit 18.

The CCD 11 is provided to capture and store an image, and the LCD 19 is provided to display the stored image. The microcomputer 14 captures an image,
It is provided to control the display of an image. ROM1
5 includes a control program for the microcomputer 14 to capture and display an image and a processing program for compressing and expanding the captured image data based on a predetermined method (in this embodiment, the JPEG method). It is remembered.

The microcomputer 14 controls the CCD 11 based on the operation of a release button (not shown) and the like.
Converts the captured image for one screen into image data and outputs it. The image data is converted into digital data via a conversion circuit, and is temporarily stored in the frame memory 16 via the external bus 13. The frame memory 16 is composed of, for example, a DRAM, and is set to a capacity capable of storing image data for one screen.

The microcomputer 14 operates based on the processing program and generates compressed image data obtained by compressing the image data for one screen stored in the frame memory 16 based on the JPEG system. And the microcomputer 14
Stores the generated compressed image data in the flash memory 17. The flash memory 17 is an electrically erasable non-volatile memory (EEPROM), and is set to have a capacity capable of storing compressed image data of a plurality of screens subjected to compression processing. The microcomputer 14 deletes all the compressed image data stored in the flash memory 17 or the compressed image data for one screen based on the operation of a button (not shown).

Further, the microcomputer 14 generates decompressed image data obtained by decompressing the compressed image data stored in the flash memory 17 based on the JPEG method based on the operation of a button (not shown). Then, the microcomputer 14 transmits the generated decompressed image data to the external bus 13 and the driving circuit 18.
And outputs the image to the LCD 19 via the. This L
According to the image displayed on the CD 19, the flash memory 1
The compressed image data stored in 7 is confirmed.

The LCD 19 receives image data of an image captured by the CCD 11 when capturing an image, and displays the image captured by the CCD 11 on the LCD 19. From the image displayed on the LCD 19, the configuration of the image to be captured and the like are confirmed.

Next, the configuration of the microcomputer 14 will be described in detail. As shown in FIG. 2, the microcomputer 14 includes a central processing unit (hereinafter referred to as a CPU) as a quantization processing unit.
21. Data transfer circuit (DMA
C: Direct Memory Access Controller) 22, a buffer memory 23, a DCT operation unit 24 as a conversion execution unit,
Further, a coefficient memory 25 is provided. CPU 21,
DMAC 22, buffer memory 23, DCT operation unit 2
4, and the coefficient memory 25 are connected to an internal bus 26, and the internal bus 26 is connected to the external bus 13.

The DMAC 22 stores the frame memory 16
DCT without using the CPU 21
It is provided for transferring to the arithmetic unit 24. Also, DMAC
Reference numeral 22 denotes a calculation result of a DCT calculation unit 24 described later,
The data is sequentially transferred to the buffer memory 23 without going through the U21.
The DMAC 22 performs one DCT operation in the DCT operation unit 24.
The image data required for the T operation is sequentially transferred.

The DCT operation section 24 performs DCT on the transferred image data to generate DCT coefficients. In this embodiment, the DCT operation unit 24
Performs a two-dimensional discrete cosine transform on image data of a general number of pixels, that is, 8 × 8 pixels. Therefore, DM
The AC 22 sequentially transfers the image data of 8 × 8 pixels to the DCT operation unit 24 at a time.

The DCT operation section 24 is provided with an internal buffer memory 27, and the image data is temporarily stored in the internal buffer memory 27. The DCT operation unit 24 performs a two-dimensional DCT operation on the image data stored in the internal buffer memory 27, and stores the DCT coefficient as the operation result in the internal buffer memory 27 again. Therefore, DC
Since the T operation unit 24 does not use the internal bus 26 in the operation, it does not affect the processing of the CPU 21 described later.
Further, since the DMAC 22 directly transfers image data necessary for the DCT operation unit 24 and DCT coefficients after the operation, the DMAC 22 does not load the CPU 21.

The CPU 21 performs predetermined compression processing on the DCT coefficients transferred by the DMAC 22 and stored in the buffer memory 23 based on the processing program stored in the ROM 15, and stores the processing result in the flash memory 17. I do. When the DCT coefficient for one screen is stored in the buffer memory 23, the CPU 21
The compression processing is performed on the DCT coefficients for one screen to generate compressed image data for one screen.

In the present embodiment, the CPU 21 executes the quantization processing and the encoding processing as compression processing. In the quantization process, the CPU 21 uses the DCT stored in the RAM.
The coefficient is compared with a predetermined quantization table threshold value stored in the coefficient memory 25 in advance, and DCT is performed based on the comparison result.
Quantize the coefficients. Further, in the encoding process, the CPU
21 encodes the quantized value using a predetermined code table (for example, a Huffman table) stored in the coefficient memory 25 in advance to generate compressed image data. Then, the CPU 21 stores the generated compressed image data in the flash memory 17.

Conversely, when the compressed image data stored in the flash memory 17 is displayed on the LCD 19, the reverse process is performed. That is, the CPU 21 decodes the compressed image data stored in the flash memory 17 and generates a DCT coefficient by the inverse amount, and stores the DCT coefficient in the buffer memory 23. The DCT coefficients stored in the buffer memory 23 are sequentially transferred to the internal buffer memory 27 of the DCT operation unit 24 by the DMAC 22.

The DCT operation section 24 performs an inverse DCT operation on the DCT coefficients stored in the internal buffer memory 27 and stores the operation result in the internal buffer memory 27 again. The result of the calculation is DMAC as the decompressed image data.
The data is sequentially read out by the CPU 22 and stored in the frame memory 16. When the expanded image data for one screen is stored in the frame memory 16, the frame memory 16
Decompressed image data for one screen stored in the external bus 1
3 and to the LCD 19 via the drive circuit 18,
An image is displayed on the CD 19.

Next, the configuration of the DCT operation section 24 will be described in detail. As shown in FIG. 3, the DCT operation unit 24 includes a DCT operation unit 31, an address generation circuit 32, and a quantization prediction circuit 33 in addition to the internal buffer memory 27. The internal buffer memory 27 includes an image buffer 27a as an image data storage area, an intermediate value buffer 27b as an intermediate value storage area, and a DCT coefficient buffer 27c as a transform coefficient storage area.

When compressing the image data, the image buffer 27a stores the image data transferred by the DMAC 22. D is stored in the intermediate value buffer 27b.
The intermediate data in the middle of the DCT calculation is stored from the CT calculator 31. The DCT coefficient buffer 27c stores the DC
The DCT coefficient which is the result of the operation of the T calculator 31 is stored.

On the other hand, when decompressing the compressed image data, the data dequantized by the CPU 21 is stored in the DCT coefficient buffer 27c. Intermediate value buffer 2
The data in the middle of the DCT calculation from the DCT calculator 31 is stored in 7b. Then, in the image buffer 27a, D
The expanded image data generated by the CT calculator 31 is stored.

The DCT calculator 31 as a conversion circuit is provided for performing a two-dimensional DCT calculation on the image data stored in the image buffer 27a during the compression processing. The DCT calculator 31 is provided to perform a two-dimensional inverse DCT operation on the data after the inverse quantization stored in the DCT coefficient buffer 27c at the time of the decompression processing.

FIG. 4 is a schematic block circuit diagram around the DCT calculator 31. The DCT operation unit 24 includes a selector 3
4, 35, a control register 36, and a sequence management circuit 37 are provided.

Data output from the DCT operation unit 24 or data transferred on the internal bus 26 is input to the image buffer 27a via the selector 34, and the image buffer 27a stores the input data. The data stored in the image buffer 27a is transferred to the DCT
1 or read by the DMAC 22.

The data output from the DCT calculator 24 is input to the intermediate value buffer 27b, and the intermediate value buffer 27b stores the input data. The data stored in the intermediate value buffer 27b is stored in the DCT
4 is read.

The data output from the DCT operation unit 24 or the data transferred on the internal bus 26 via the selector 35 is input to the DCT coefficient buffer 27c.
The T coefficient buffer 27c stores the input data.
Then, the data stored in the DCT coefficient buffer 27c is read by the DCT calculator 31 or the DMAC 22.

The control register 36 is connected to the internal bus 26, and stores control data for performing various settings from the CPU 21 via the internal bus 26. The setting includes, for example, whether the process at that time is a compression process or an expansion process. That is, the CPU 21 selects the compression process or the decompression process based on the operation of the button (not shown) as described above, and stores control data corresponding to the selected process in the control register 36. And the CPU 21
Notifies the start of the processing by the control bit of the control register 3667 after the setting is completed.

The control register 36 is connected to a sequence management circuit 37. The sequence management circuit 37
Based on the settings stored in the control register 36, both selectors 34 and 35 are controlled respectively. Control register 36
If compression is performed based on settings stored in
The sequence management circuit 37 controls the selectors 34 and 35 to transfer the image buffer 27a to the internal bus 26 and the DC
The T coefficient buffer 27c is connected to the DCT calculator 31.

The DCT calculator 31 starts the DCT calculation based on the setting of the control register 36 in response to the notification of the processing start, and issues a transfer request of the image data. This transfer request is notified to the DMAC 22 by a request bit of the control register 36 or an interrupt signal.

The DMAC 22 transfers the image data of one block (8 × 8 pixels) of the image data stored in the frame memory 16 shown in FIG. Through the image buffer 27a. When the transfer is completed, DM
The AC 22 notifies the DCT operator 31 that the transfer has been completed by the control bit of the control register 36.

The DCT calculator 31 sequentially receives the image data stored in the image buffer 27a in response to the transfer completion notification, and performs a one-dimensional DCT calculation on the image data. Then, the DCT calculator 31 sequentially outputs the calculation results as intermediate data to the intermediate value buffer 27b,
The intermediate value buffer 27b stores the intermediate data. Further, the DCT calculator 31 sequentially inputs the intermediate data stored in the intermediate value buffer 27b, and performs a one-dimensional DCT operation on the intermediate data. Then, the DCT calculator 31 uses the result of the calculation as a DCT coefficient in the selector 35.
Are sequentially output to the DCT coefficient buffer 27c through
The T coefficient buffer 27c sequentially stores DCT coefficients.

Accordingly, the image data stored in the image buffer 27a is stored in the two-dimensional one-dimensional D
A two-dimensional DCT operation is performed by the CT operation, and the operation result is stored as a DCT coefficient in the DCT coefficient buffer 27c. D stored in the DCT coefficient buffer 27c
The CT coefficients are transferred by the DMAC 22 to the buffer memory 23 via the internal bus 26 in accordance with the transfer request issued by the DCT calculator 31, and the buffer memory 23 stores the transferred DCT coefficients.

As described above, the image data of each block stored in the frame memory 16 is subjected to DCT processing, converted into DCT coefficients, and sequentially stored in the buffer memory 23. At this time, when the first one-dimensional DCT operation is completed, the contents of the image buffer 27a become unnecessary. Therefore, the DCT calculator 31 issues a transfer request for the image data of the next block, and outputs the intermediate value buffer 27b.
Second one-dimensional DCT for intermediate data stored in
Start the operation. Then, in response to the transfer request, the DMAC 22 stores the image data of the next block in the image buffer 27a.
Transfer to

That is, while the DCT calculator 31 is executing the second one-dimensional DCT calculation on the intermediate data stored in the intermediate value buffer 27b, the image data of the next block is transferred. Therefore, transfer of image data and DC
The T operation is executed in parallel.

When the second one-dimensional DCT operation is completed, the image data of the next block is stored in the image buffer 27a. Therefore, the DCT calculator 31 calculates
A transfer request for the DCT coefficient stored in the DCT coefficient buffer 27c is generated, and the first one-dimensional DCT operation on the image data stored in the image buffer 27a is started.
The DMAC 22 transfers the DCT coefficient of the DCT coefficient buffer 27c in response to the transfer request.

That is, the DCT operation unit 31 is connected to the image buffer 2
The first one-dimensional D for the image data stored in 7a
During the execution of the CT operation, the previously calculated DCT coefficients are transferred. Therefore, the DCT operation and the transfer of the DCT coefficient after the operation are performed in parallel.

On the other hand, when performing the decompression processing, the CPU 21 stores control data corresponding to the decompression processing in the control register 36. Further, the CPU 21 notifies the start of the processing by the control bit of the control register 3667 after the setting is completed. At this time, the buffer memory 23 stores data (DCT coefficients) obtained by decoding and dequantizing the compressed image data stored in the flash memory 17 by the CPU 21.

The sequence management circuit 37 selects the selectors 34 and 35 based on the settings stored in the control register 36.
To connect the image buffer 27a to the DCT calculator 31 and the DCT coefficient buffer 27c to the internal bus 26. The DCT calculator 31 starts the inverse DCT operation based on the setting of the control register 36 in response to the notification of the processing start, and issues a transfer request of the inversely quantized DCT coefficient. This transfer request includes a request bit of the control register 36,
Alternatively, the DMAC 22 is notified by an interrupt signal tower.

The DMAC 22 transfers the inversely quantized DCT coefficients stored in the buffer memory 23 to the DCT coefficient buffer 27c via the internal bus 26 and the selector 35 according to the transfer request. When the transfer of the DCT coefficient of one block is completed, the DMAC 22 informs the DCT operator 31 that the transfer has been completed by the control bit of the control register 36.
Notify.

The DCT calculator 31 responds to the notification of the completion of the transfer by storing the DCT coefficient stored in the DCT coefficient buffer 27c.
The coefficients are sequentially input, and the one-dimensional inverse D
Perform CT operation. Then, the DCT calculator 31 outputs the calculation result to the intermediate value buffer 27b as intermediate data, and the intermediate value buffer 27b stores the intermediate data. Further, the DCT calculator 31 includes an intermediate value buffer 27b.
Are sequentially input, and a one-dimensional inverse DCT operation is performed on the intermediate data. And DC
The T calculator 31 outputs the calculation result as decompressed image data to the image buffer 27a via the selector 34, and the image buffer 27a stores the decompressed image data.

Accordingly, the inversely quantized DCT coefficient stored in the DCT coefficient buffer 27c is converted into a two-dimensional inverse DCT by two one-dimensional inverse DCT operations by the DCT calculator 31.
The CT operation is performed, and the operation result is stored in the image buffer 27a as decompressed image data. The decompressed image data stored in the image buffer 27a is output to the DCT
1 according to the transfer request issued by the DMAC 22, the internal bus 26 and the external bus 1 shown in FIG.
3 and to the LCD 19 via the drive circuit 18,
The CD 19 displays the transferred decompressed image data.

The compressed image data stored in the flash memory 17 as described above is decoded and inversely quantized by the CPU 21, and then the DCT
T operation is performed to convert the image data into expanded image data.
9 is displayed. At this time, the contents of the DCT coefficient buffer 27c become unnecessary at the time when the first inverse DCT operation is completed. Accordingly, the DCT calculator 31 generates a transfer request for the DCT coefficient of the next block and starts the second inverse DCT calculation on the intermediate data stored in the intermediate value buffer 27b. Then, the DMAC 22 transfers the DCT coefficient of the next block from the buffer memory 23 to the DCT coefficient buffer 27c in response to the transfer request.

That is, while the DCT calculator 31 is executing the second one-dimensional inverse DCT calculation on the intermediate data stored in the intermediate value buffer 27b, the DCT of the next block is
The T coefficient is transferred and stored in the DCT coefficient buffer 27c. Therefore, the inverse DCT operation and the transfer of the DCT coefficient are executed in parallel.

When the second one-dimensional inverse DCT operation is completed, the DCT coefficient of the next block is stored in the DCT coefficient buffer 27c. Therefore, the DCT calculator 31 issues a transfer request for the decompressed image data stored in the image buffer 27a, and starts the first one-dimensional inverse DCT operation on the DCT coefficient of the next block stored in the DCT coefficient buffer 27c. . The DMAC 22 transfers the decompressed image data stored in the image buffer 27a to the LCD 19 in response to the transfer request.

That is, while the DCT calculator 31 is executing the first one-dimensional inverse DCT calculation on the DCT coefficients stored in the DCT coefficient buffer 27c, the decompressed image data previously calculated and stored Is transferred. Therefore, the inverse D
The CT operation and the transfer of the decompressed image data after the operation are performed in parallel.

The CPU 21 does not participate in the transfer of each data in the above-mentioned compression / decompression processing, but only notifies the selection of the compression / decompression processing and the start of the processing. Therefore, CPU
21 indicates a buffer memory 23 during the compression process during the above.
During the quantization, encoding, and decompression processing for the DCT coefficients stored in the buffer memory 23, the decoded and inversely quantized DCT coefficients are stored in the buffer memory 23. That is, the DCT operation and the quantization and encoding are performed in parallel during the compression processing of the image data. Also, when decompressing the compressed image data, the inverse D
The CT operation and the inverse quantization and decoding are performed in parallel.

The address generation circuit 32 shown in FIG.
Used when the DCT calculator 31 stores the DCT coefficient as the calculation result in the DCT coefficient buffer 27c;
It is provided for generating an address of the DCT coefficient buffer 27c for storing the DCT coefficient.

Generally, the DCT calculator 31 shown in FIG.
As shown in FIG. 6, the DCT coefficients (frequency components) stored in the DCT coefficient buffer 27c are arranged in the order of low frequency components to high frequency components from the upper left to the lower right. Usually, each frequency component has the largest value of the DC component (the frequency component located at the first position at the upper left), and the value decreases as the frequency increases. And
The quantized data often approaches 0 at the highest frequency. For this reason, zigzag scanning and encoding of the quantized data according to the arrow shown in FIG. 6 enables efficient compressed image data with a high compression rate to be obtained.

Then, the above zigzag scan is performed as shown in FIG.
Is performed by the CPU 21 shown in FIG. That is, the CPU 21
From the DCT coefficient buffer 27c to the buffer memory 23
After performing a quantization process on the DCT coefficients transferred to the, the zigzag scan is performed in the order shown in FIG. 6 and the read values are encoded to obtain compressed image data with a high compression ratio. It is. However, since the respective frequency components are not arranged in the reading order, the storage addresses of the respective frequency components are discontinuous.
It takes time for the CPU 21 to read.

Therefore, when the DCT coefficients are stored in advance, the frequency components are arranged and stored in the zigzag scan order based on the storage addresses in the zigzag scan order generated by the address generation circuit 32.
The effort of 21 is saved. That is, there is no need for the CPU 21 to scan each frequency component zigzag, and it is possible to perform continuous access and perform processing such as quantization.

As shown in FIG. 5, the address generation circuit 32
Include first and second storage address generation circuits 38 and 39,
And a switching circuit 40. The first storage address generation circuit 38 is provided with the DCT operator 3 shown in FIG.
This is to generate an address signal in a zigzag scan order with respect to the DCT coefficient calculated by (1). The first storage address generation circuit 38 outputs the generated zigzag scan order address signal to the switching circuit 40. The second storage address generation circuit 39 generates an address signal in the calculation order for the DCT coefficient calculated by the DCT calculator 31. Second storage address generation circuit 39
Outputs the generated calculation order address signal to the switching circuit 40. A selection signal corresponding to a selection bit of the control register 36 shown in FIG. 4 is input to the switching circuit 40, and the selection bit is set by the CPU 21. That is, the CPU 21 sets the selection bits of the control register 36 in accordance with the order of the generated address signals, and the switching circuit 40 receives a selection signal corresponding to the selected bits. Then, the switching circuit 40 selects one of the two address signals input from the first and second storage address generation circuits 38 and 39 based on the selection signal, and converts the selected address signal into a DCT coefficient buffer. 27c. Then, the DCT coefficient buffer 27c stores the DCT coefficient (frequency component) output from the DCT calculator 31 at the corresponding address based on the input address signal.

For example, a case where DCT coefficients are stored from the address 0000 of the DCT coefficient buffer 27c will be described. At this time, the DCT calculator 31 converts the DCT coefficients a00 to a63, which are the calculation results, into a00, a01, a0 in the calculation order.
2, ..., a61, a62, a63 are output in order. On the other hand, the first storage address generation circuit 38 outputs an address signal corresponding to the zigzag scan order. For example, DCT coefficient
a00 is read first and the DCT coefficient a01 is read second. And the DCT coefficient a02 is the fifth,
The DCT coefficient a03 is read sixth. Therefore, the first
Generates an address 0000 corresponding to the DCT coefficient a00 and an address 0001 corresponding to the DCT coefficient a01. Further, the first storage address generation circuit 38 stores the address 0005 corresponding to the DCT coefficient a02
An address 0006 is generated corresponding to the CT coefficient a03.

That is, the first storage address generation circuit 38
Are the DCT coefficients a00, a0 output from the DCT calculator 31.
, A60, a61, a62, a63, and generates and outputs addresses 0000,0001,0005,0006, ..., 0057,0058,0062,0036. As a result, the DCT coefficient buffer 27c
Have the DCT coefficients a00 to
a63 is a00, a01, a08, a16, a09, a02, a03, a10, ..., a55, a
It is stored in the order of 62, a63, and transferred to the buffer memory 23 shown in FIG. 2 in the same order.

This order is the order of the zigzag scan in the encoding, so that the CPU 21 in FIG. 2 can read out the DCT coefficients in the order of the zigzag scan simply by accessing in order from the address 0000. Therefore, it is not necessary for the CPU 21 to read the DCT coefficients discontinuously, and it is not necessary for the CPU 21 to rearrange the DCT coefficients in the zigzag scan order, so that the trouble is eliminated.

In the case where the processing for rearranging in the zigzag scan order does not impose a load due to the speeding up of the CPU 21 in FIG. 2 or in the case of encoding that does not require the zigzag scan itself, the CPU 21 determines the DCT coefficient by It is also possible to store them in the DCT coefficient buffer 27c in the order of calculation. That is, the CPU 21 controls the control register 36 shown in FIG. 4 so that the switching circuit 40 shown in FIG. 5 selects the address signals in the calculation order output from the second storage address generation circuit 39. Set. According to the address signal, the DCT coefficients are sequentially stored in the DCT coefficient buffer 27c in the calculation order.

The quantization prediction circuit 33 shown in FIG.
It is provided to reduce the load of the quantization process performed by the CPU 21 on the DCT coefficient stored in the CT coefficient buffer 27c next. The quantization prediction circuit 33
In the quantization processing, a value whose value after quantization becomes a predetermined value (for example, “0”) is detected, and a sign is added to the DCT coefficient that becomes “0”.

As described above, the DCT after the DCT operation is performed.
As shown in FIG. 6, the coefficient (frequency component) has the largest value of the DC component (the frequency component located at the first position on the upper left), and decreases as the frequency increases. Then, the quantized data is often close to “0” at the highest frequency.

Accordingly, the CPU 21 checks the sign of the DCT coefficient read in the quantization processing. And D
When the above-mentioned code is added to the CT coefficient, C
The PU 21 omits the quantization processing on the DCT coefficient read by storing “0”. Then, since the quantization process for the DCT coefficient which becomes “0” after the quantization can be omitted, the calculation load of the CPU 21 is reduced. Furthermore, since the code inspection time in the CPU 21 is shorter than the time required for quantization, the processing time in quantization is reduced.

More specifically, the quantization prediction circuit 33 compares the input DCT coefficient Svu with each quantization coefficient Qvu of a quantization table stored in the coefficient memory 25 in advance.
Then, the quantization prediction circuit 33 calculates the value Sq at the time of quantization.
The prediction process is performed depending on whether or not the solution by vu = round (SvuuQvu) becomes 0 (zero). Note that round is a rounding process, and in this case, a process of rounding off a decimal part.

As a result of the comparison, DC which is predicted to be Sqvu = 0
In the case of the T coefficient Svu, the quantization prediction circuit 33 adds a code indicating the Tv to the DCT coefficient Svu and re-stores it in the DCT coefficient buffer 27c.

As shown in FIG. 8, the quantization prediction circuit 33
Includes a bit operation unit 41, a comparison unit 42, and a data generation unit 43. The DCT coefficients stored in the DCT coefficient buffer 27c are sequentially input to the bit operation unit 41. The bit operation unit 41 is provided to prevent a difference between a result of a round (rounding) process performed by quantization and a result of a prediction process performed by a comparator from occurring. In addition, the bit operation unit 41 is provided for performing a bit operation on the input DCT coefficient Svu to simplify the comparison process in the comparator.

The bit operation unit 41 checks the value of the MSB of the input DCT coefficient Svu. And MSB =
In the case of (0) B, the bit operation unit 41 determines that the DCT coefficient M
Set SB to (1) B and set the DCT coefficient to a negative value. Note that (0) B indicates binary data. As a result, D input in the next comparing section 42
This is to simplify the comparison process by comparing the CT coefficient and the quantization coefficient by an addition process.

Generally, the comparison process is determined by the sign of the result of the subtraction. However, the circuit size of the subtraction processing becomes large. Therefore, by changing one of them to a negative value in advance, it is possible to perform the comparison process by an addition process (addition circuit) having a small circuit scale.

The bit operation unit 41 receives the input DC
LSB extension is performed by adding (0) B to the LSB for the T coefficient. This is because, at the time of final quantization, the value after the decimal point is rounded off by round processing, and the result of quantization and the prediction may be different. Therefore, by extending the LSB in advance, the result of quantization and the prediction are the same.

The bit operating section 41 outputs the above processing result to the comparing section 42. The comparison unit 42 includes a coefficient memory 25
Are input as the quantization coefficients stored in the quantization table. The comparison unit 42 includes an adder in the present embodiment, and includes a processed DCT coefficient input from the bit operation unit 41,
The result is added to the quantization coefficient, and the addition result is output to the data generation unit 43 as a comparison result.

The data generator 43 receives the comparison result from the comparator 42. Further, the DCT coefficient stored in the DCT coefficient buffer 27c is input to the data generation unit 43. The data generator 43 adds a predetermined value to the DCT coefficient based on the comparison result. Specifically, when the input DCT coefficient is n bits, the data generation unit 43 expands the MSB of the DCT coefficient to n + 1
Set to a bit value. Then, the data generating unit 43 stores (0) B or (1) B for the extended MSB based on the comparison result. As a result, the comparison result is added to the original DCT coefficient, and the DCT coefficient buffer 27c
Is stored again.

In the comparing section 42, the addition result of the DCT coefficient and the quantization coefficient is a positive value, that is, the quantization coefficient is
If it is larger than the CT coefficient, it indicates that the quantization result is "0" including the round processing in the quantization. Then, in the present embodiment, the data generation unit 43 adds (1) B to the DCT coefficient whose quantization result is “0”,
(0) B is added to DCT coefficients that do not become “0”. The data generation unit 43 outputs the DC value to which the predetermined value has been added.
The T coefficient is stored again in the DCT coefficient buffer 27c.

Next, a rounding process (roun
d) The processing will be described with a specific example. For example,
When the quantization coefficient Qvu = 4 and the DCT coefficient Svu = 2, the value Sqvu obtained by quantization is Sqvu = round (Svu ÷ Qvu), so that Sqvu = round (2 ÷ 4) = round (0.5) )
= 1 and Sqvu ≠ 0. This is transmitted to the bit operation unit 41
When the processing by the comparing unit 42 is performed without performing the LSB extension in Sqvu0 = Qvu−Svu = 4-2 = 2 and Sqvu0> 0, it is determined that Sqvu = 0, and the original quantization is performed. You will get different results.

Then, when the LSB extension is executed by the bit operation unit 41 and the processing by the comparison unit 42 is performed, Svu =
Since it is (0010) B, the value Svu1 = (00100) B when LSB-extended. Then, Sqvu1 = Qvu-Svu1 = 4-4 = 0, and since Sqvu1≤0, the quantization prediction circuit 33
Is determined as Sqvu ≠ 0, and the same result as the original quantization can be obtained.

Also, the quantization coefficient Qvu = 5, the DCT coefficient Svu
When = 2, the value Sqvu obtained by quantization is: Sqvu = round (2 ÷ 5) = round (0.4)
= 0 and Sqvu = 0. Then, when the processing by the comparing unit 42 is performed, Sqvu1 = Qvu-Svu1 = 5-4 = 1, and Sqvu1> 0.
Is determined to be Sqvu = 0, and the same result as the original quantization can be obtained.

Also, the quantization coefficient Qvu = 3, the DCT coefficient Svu
= 2, the value Sqvu obtained by quantization is: Sqvu = round (2 ÷ 3) = round (0.66)
7) = 1, and Sqvu ≠ 0. Then, when the processing by the comparing unit 42 is performed, Sqvu1 = Qvu−Svu1 = 3-4 = −1, and Sqvu1 ≦ 0.
Is determined as Sqvu ≠ 0, and the same result as the original quantization can be obtained.

As described above, the present embodiment has the following advantages. (1) The microcomputer 14 is the CPU 2 connected to the internal bus.
1 and a DCT operation unit. The DCT operation part is a DCT
Arithmetic unit 31, image buffer 27a, intermediate value buffer 2
7b and a DCT coefficient buffer 27c. The DCT calculator 31 executes the first one-dimensional DCT operation on the image data stored in the image buffer 27a, stores the image data in the intermediate value buffer 27b, and executes the second time on the intermediate data stored in the intermediate value buffer. Performs a one-dimensional DCT operation of
It is stored in the CT coefficient buffer 27c. Accordingly, while the DCT calculator 31 performs the first one-dimensional DCT operation, the previously calculated DCT coefficient is transferred, and during the execution of the second one-dimensional DCT operation, Image data to be calculated is transferred. Therefore, DCT operation and DC after operation
The transfer of the T coefficient is executed in parallel. Also, the CPU 21
Does not involve in the transfer of each data in the above-mentioned compression / decompression processing, but only notifies the selection of the compression / decompression processing and the start of the processing. As a result, during the compression processing of the image data, the DC
Since the DCT calculation by the T calculator 31 and the quantization and encoding by the CPU 21 are performed in parallel, the processing is speeded up. In addition, since the DCT calculator 31 is constituted by a circuit, the operation can be performed at a higher speed than software, and the circuit scale becomes smaller than when all the processing is constituted by a circuit. Can be suppressed.

(2) The DCT operation section 24 of the microcomputer 14 is provided with an address generation circuit 32. The address generation circuit 32 includes the first and second storage address generation circuits 3
8, 39 and a switching circuit 40.
The first storage address generation circuit 38 outputs the D
It generates an address signal in a zigzag scan order for the DCT coefficient calculated by the CT calculator 31. The first storage address generation circuit 38 outputs the generated zigzag scan order address signal to the DCT coefficient buffer 27c via the switching circuit 40. Therefore, DC
The DCT coefficients output from the T calculator 31 are stored by arranging the respective frequency components in the zigzag scan order based on the storage addresses in the zigzag scan order generated by the first storage address generation circuit 38. As a result, CPU2
No. 1 does not need to scan each frequency component zigzag, and can perform processing such as quantization by accessing continuously, so that the work of the CPU 21 is omitted and the load is reduced.

(3) The DCT operation section 24 of the microcomputer 14 includes a coefficient memory 25 and a quantization prediction circuit 33. In the coefficient memory 25, a quantization table including quantization coefficients used for the quantization process is set and stored in advance. The quantization prediction circuit 33 compares the DCT coefficient generated by the DCT calculator 31 and stored in the DCT coefficient buffer 27c with the quantization coefficient read from the coefficient memory 25, and based on the comparison result, Whether or not the coefficient becomes “0” by the quantization process is predicted, and (1) B is stored in the MSB extended for the DCT coefficient that becomes “0” and a sign is added. As a result, when the above-mentioned code is added to the DCT coefficient, the CPU 21
Can omit the quantization process for the DCT coefficient read by storing “0”, so that the calculation load of the CPU 21 is reduced. Furthermore, since the code inspection time in the CPU 21 is shorter than the time required for quantization, the processing time in quantization is reduced.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. For convenience of description, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be partially omitted.

In this embodiment, the coefficient memory 25 shown in FIG. 2 stores a plurality of quantization tables and encoding tables. The plurality of quantization tables and encoding tables are set in advance in accordance with the tendency of image data to be subjected to compression processing, and are stored in the coefficient memory 25.

In the image data, generally, the value of the DCT coefficient (frequency component) after the DCT operation is large in a low frequency region, and decreases as the frequency increases. Also, human vision is sensitive to luminance differences in the low frequency range, but insensitive to high frequencies. Therefore, in the low frequency region, the quantization coefficients constituting the quantization table are set to small values, and the difference in luminance is easily reproduced. In addition, the quantization coefficient is set to a large value in a high-frequency region to achieve a high compression ratio in encoding.

However, some images have a large amount of information in a high-frequency region. If this image is quantized using a general quantization table, information in the high-frequency region is lost, and the reproduced image is significantly different from the original image. Further, when image data having a large amount of information in a high frequency region is compressed using a general quantization table and an encoding table, the compression ratio may not be high.

For this purpose, the tendency of the image data is determined corresponding to the frequency component, and a plurality of quantization tables and encoding tables corresponding to the tendency of the image data are set in advance. Then, information is held and compressed using a quantization table and an encoding table corresponding to the tendency of the obtained image data, and the compression ratio is increased.

As shown in FIG. 9, the DCT operation unit 24 includes a DCT operation unit 31, an address generation circuit 32,
A table determination circuit 50 is provided. Since the DCT calculator 31 and the address generation circuit 32 are the same as those in the first embodiment, detailed description will be omitted.

The table determination circuit 50 is provided for generating selection information for selecting one of a plurality of quantization tables and coding tables stored in the coefficient memory 25. The CPU 21 in FIG. 2 reads out the selection information generated by the table determination circuit 50, and selects one of the plurality of quantization tables and coding tables stored in the coefficient memory 25 based on the selection information. . Then, the CPU 21 performs quantization and encoding processing based on the selected table to generate compressed image data, and stores the compressed image data in the flash memory 17.

The compressed image data stored in the flash memory 17 is processed using a quantization table and an encoding table selected based on the tendency of the original image. Therefore, the compressed image data includes the information of the original image without any loss, and is created at a high compression rate.

Next, the configuration of the table determination circuit 50 will be described in detail. As shown in FIG. 10, the table determination circuit 50 includes a threshold register 51, a selector 52, a comparator 53, a control unit 54, and a counter 55. The threshold registers 51 are provided in a number corresponding to a plurality of areas divided according to the tendency of the DCT coefficient.
In this embodiment, as shown in FIG. 11, the frequency component of the DCT coefficient is divided into four regions, and four threshold registers 51a to 51d are provided for each region.

As shown in FIG. 11, the DCT operation unit 2
The frequency components of the DCT coefficients calculated and output by step 4 are arranged from the low frequency side to the high frequency side. In the present embodiment, the frequency component of the DCT coefficient is divided into two in each of the vertical direction and the horizontal direction in FIG. 11 to be divided into a total of four regions.

Each of the threshold registers 51a-51d has a CP
The threshold corresponding to each area of the DCT coefficient is written by U21. For example, a normal DCT coefficient tends to have a large low-frequency component and a small high-frequency component. Therefore, when quantizing average image data, when the threshold is increased, most of the high-frequency components become “0”, The compression ratio increases. Therefore, the tendency of the image data can be obtained by setting the threshold value of the low frequency region to be the largest and the threshold value of the high frequency region to be the smallest corresponding to the low frequency region.

The threshold values stored in each of the threshold value registers 51a to 51d are output to the comparator 53 via the selector 52. The comparator 53 is connected to the DCT calculator 31. The DCT calculator 31 performs a DCT calculation process on the image data of one block (8 × 8 pixels) stored in the image buffer 27a shown in FIG. 4, and uses the calculation result as a DCT coefficient in the DCT coefficient buffer 27c. To be stored. The DCT coefficient output from the DCT calculator 31 at each time is input to the comparator 53.

The selector 52 is connected to the control unit 54,
A selection signal is input from the control unit 54. The selection signal is generated based on the DCT coefficient address signal stored in the DCT coefficient buffer 27c, and is output to the selector 52. Then, based on the selection signal, the selector 52 outputs to the comparator 53 the sites stored in the threshold registers 51a to 51d corresponding to the area to which the DCT coefficient stored each time belongs. The comparator 53 is
Each time a DCT coefficient is input, the input DCT coefficient is compared with a threshold read out from threshold registers 51a to 51d corresponding to the area to which the DCT coefficient belongs, and the comparison result is output to control unit 54. I do.

The control unit 54 is connected to a number of counters 55 corresponding to the areas obtained by dividing the DCT coefficients.
In this embodiment, since the DCT coefficient is divided into four regions, the control unit 54 includes four counters 55a to 55
d is connected.

The control unit 54 controls the DC input to the comparator 53 based on the comparison result input from the comparator 53.
Counters 55a to 55d corresponding to the area to which the T coefficient belongs
Output the signal. Each of the counters 55a to 55d counts up its count value based on a signal output from the control unit 54. Therefore, each of the counters 55a to 55a
The count value of 5d is a value based on the comparison result between the threshold value stored in each of the threshold value registers 51a to 51d and the DCT coefficient.

Specifically, when the DCT coefficient is larger than the threshold based on the comparison result input from comparator 53, control unit 54 controls counters 55a to 55d corresponding to the area to which the DCT coefficient belongs. Output a signal. Therefore, when the DCT calculation processing for one block of image data is completed, the count values of the counters 55a to 55d indicate how many DCT coefficients have exceeded the threshold in each area. Therefore, the CPU 21 reads out the count values of the respective counters 55a to 55d via the internal bus 26, and determines the tendency of the image data based on the count values.

For example, the counter 55d corresponding to the area 4
Counters 55a-5 corresponding to the other areas
If the count value is significantly larger than the count value of 5c, it is determined that the input image is not average image data but image data having an extremely high frequency component. Therefore, the CPU 21 may not be able to obtain a satisfactory compression rate and image quality with the quantization table and the encoding table that are normally used. Therefore, the CPU 21 performs the quantization and the encoding process using the table emphasizing the high frequency component. . As a result, the high-frequency component is reliably held, the image quality is improved, and the compression efficiency can be increased because the quantization is performed by the optimal quantization table.

Since it is not preferable to make the above-described determination only in the processing of one block, the CPU 21 previously sets a representative block in one frame, for example, around the four corners and the center of the image data, and sets it. Comprehensive judgment is made based on the judgment result in the representative block.

As described above, the present embodiment has the following advantages. (1) The same effects as (1) and (2) in the first embodiment are achieved. (2) A table determination circuit 50 is provided. The threshold registers 51a to 51d of the table determination circuit store thresholds corresponding to a plurality of areas obtained by dividing the DCT coefficient. Comparator 53
Compares the DCT coefficient with the threshold value stored in each of the threshold value registers 51a to 51d. The control unit 54 sets a counter 55a corresponding to each area based on the comparison result of the comparator 53.
５５55d is counted up. Therefore, each of the counters 55a to 55d has a DC value exceeding the threshold value in each region.
The number of T coefficients is stored as a count value, and the count value indicates the type of image. And CP
The U21 selects one of the plurality of quantization tables and the encoding tables when performing the quantization and the encoding, and performs the quantization process and the encoding process. As a result, compression can be performed according to the state of the captured image,
The compression efficiency and the image quality of the compressed image data can be improved.

The present invention may be embodied in the following modes other than the above embodiment. In the above embodiments, the quantization and the inverse quantization are performed by the CPU 21. However, the microcomputer 14 includes the quantization unit 61 that executes the quantization and the inverse quantization as shown by the dotted line in FIG. May be implemented. Although the encoding and decoding are performed by the CPU 21 in each of the above-described embodiments, the microcomputer 14 includes an encoding unit 62 that performs the encoding and decoding processes, as indicated by a dotted line in FIG. May be implemented. Further, the microcomputer 14 may be provided with a quantization operation unit and an encoding unit.

In each of the above embodiments, the DMAC 22 is provided as data transfer means so that each data is transferred to the internal buffer 27 of the DCT operation unit 24 independently of the CPU 21. May be performed. In this case, although the addition of the CPU 21 is slightly increased, it is not necessary to provide the DMAC 22, so that the chip area of the microcontroller 14 can be reduced.

In each of the above embodiments, the first storage address generation circuit 38 and the second storage address generation circuit 39 are provided in the address generation circuit 32, and the calculation order address signal generated by each circuit and the zigzag scan order are generated. Although the address signal and the switching signal can be selected by the switching circuit 40, the configuration may be such that only the first storage address generation circuit 38 is provided. In this case, although the DCT coefficients output from the DCT calculator 31 cannot be stored in the calculation order, the second storage address generation circuit 39
Since the switching circuit 40 can be omitted, the chip area of the microcomputer 14 can be reduced accordingly.

In the first embodiment, the quantization predicting circuit 33 uses the DCT coefficient stored in the DCT coefficient buffer 27c.
For the T coefficient, it is determined whether or not the DCT coefficient becomes “0” after quantization, a sign is added to the DCT coefficient, and the DCT coefficient is stored again in the DCT coefficient buffer 27c.
As shown by the dotted line in FIG. 8, the DCT coefficient output from the DCT calculator 31 is directly input, the DCT coefficient is determined, and the DCT coefficient added with a sign based on the determination result is stored in the DCT coefficient buffer 27c. It may be stored.

In the first embodiment, the quantization prediction circuit 33 determines whether or not the value becomes "0" after quantization, and based on the determination result, the DCT coefficient buffer 27c.
May be stored as “0”. In this case, CP
U21 can omit the quantization process when the read DCT coefficient is "0", and thus has the same effect as the first embodiment.

In the second embodiment, the circuit configuration of the table determination circuit 50 may be changed as appropriate. For example, as shown in FIG.
Number corresponding to a plurality of areas obtained by dividing DCT coefficients (n)
And each of the determination units 50a to 50n.
a to 50n are a threshold register 51a and a comparator 5
3a and a counter 51a.

Although the DCT coefficient is divided into four regions in the second embodiment, the DCT coefficient may be divided into an arbitrary number of regions. For example, the DCT coefficient shown in FIG. 11 is divided into two in the horizontal or vertical direction in the drawing. With this configuration, since only two quantization tables and two encoding tables are required, the capacity of the coefficient memory 25 can be reduced. In addition, DCT is divided into three in the horizontal and vertical directions.
The frequency components of the coefficients are divided into nine regions. With this configuration, it is possible to perform quantization and encoding in more detail according to the state of image data.

In the second embodiment, the quantization prediction circuit 33 of the first embodiment is provided, and after determining the quantization table to be used, the DCT coefficient after quantization is determined based on the quantization coefficient of the quantization table. A determination may be made as to whether the value becomes "0", a sign may be added to the DCT coefficient, and the DCT coefficient may be stored again in the DCT coefficient buffer 27c. With this configuration, it is possible to perform quantization and encoding according to the state of image data, and it is possible to omit the quantization process in quantization, so that the load on the CPU 21 can be reduced.

In each of the above embodiments, the flash memory 17 is built in. However, the flash memory 17 may be connected to the external bus 13 from outside the image information processing apparatus. Further, a built-in flash memory 17 and an externally connected flash memory 17 may be provided to selectively store compressed image data, or to transfer compressed image data between a plurality of flash memories 17.

[0122]

As described in detail above, according to the present invention,
A microcontroller capable of performing inexpensive and high-speed compression and decompression processing of image data can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a schematic configuration diagram illustrating an image processing system according to an embodiment.

FIG. 3 is a block circuit diagram of a DCT operation unit according to the first embodiment.

FIG. 4 is a block circuit diagram for explaining the operation of the DCT calculator.

FIG. 5 is a block circuit diagram of an address generation circuit.

FIG. 6 is an explanatory diagram showing the order of zigzag scanning in DCT calculation.

FIG. 7 is an explanatory diagram showing addresses in a calculation order and a zigzag scan order.

FIG. 8 is a block circuit diagram of a quantization prediction circuit.

FIG. 9 is a block circuit diagram of a DCT operation unit according to the second embodiment.

FIG. 10 is a block circuit diagram of a table determination circuit.

FIG. 11 is an explanatory diagram showing division of DCT coefficients.

FIG. 12 is a block circuit diagram of another table determination circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image processing apparatus 2 Microcontroller 3 Internal bus 4 Data transfer means 5 Conversion execution means 6 Image data storage area 7 Intermediate value storage area 8 Conversion coefficient storage area 9 Conversion circuit

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Masaki Okada 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Inside Fujitsu VSI Co., Ltd. (72) Tomonobu Miyata 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Fujitsu VLSI Corporation

Claims (8)

[Claims] 1. A microcontroller used in an image processing apparatus for performing a compression process of image data, comprising: a data transfer unit connected to the internal bus, for transferring data via the internal bus; Connected to the image data through the internal bus, and performing a discrete cosine transform on the image data to convert the image data into DCT coefficients required for the compression process. An image data storage area to which the image data is input; an intermediate value storage area to store intermediate data in the conversion processing; a transform coefficient storage area to store the DCT coefficients; and an image in the image data storage area. The result of performing the conversion process on the data is stored in the intermediate value storage area as intermediate data, and the intermediate data in the intermediate value storage area A conversion circuit for storing a result of the conversion processing as a DCT coefficient in the conversion coefficient storage area, wherein the data transfer unit stores the DCT coefficient stored in the conversion coefficient storage area during the conversion processing on the image data. A microcontroller configured to transfer image data to be converted next to the image data storage area during the conversion processing on the intermediate data. 2. The microcontroller according to claim 1, wherein said conversion executing means performs two-dimensional discrete cosine transform on said image data, and said conversion circuit performs one-dimensional discrete cosine transform. The conversion circuit stores the result of the one-dimensional discrete cosine transform processing on the image data in the image data storage area as the intermediate data in the intermediate value storage area, The result of the one-dimensional discrete cosine transform
A microcontroller configured to store the coefficients in the conversion coefficient storage area. 3. The microcontroller according to claim 1, wherein a coefficient memory in which a quantization table including a quantization coefficient used for a quantization process is stored in advance, and the conversion is performed based on the quantization coefficient. A quantization processing unit that quantizes the DCT coefficient transferred from the coefficient storage area, wherein the transform execution unit compares the DCT coefficient with the quantization coefficient, and, based on a comparison result, Predict whether the code data will be a predetermined value by the quantization process,
A quantizing prediction circuit for adding information to the code data having the predetermined value, wherein the quantization processing means performs the processing when the DCT coefficient has a predetermined value based on the information added to the DCT coefficient. DCT
A microcontroller that does not perform quantization processing on coefficients. 4. The microcontroller according to claim 3, wherein the quantization prediction circuit receives the DCT coefficient, extends a least significant bit of the DCT coefficient, and outputs the result. A comparing unit that compares the quantized coefficient stored in the coefficient storage area with the output data of the bit operation unit, and outputs a result of the comparison; and adds an information bit based on the result of the comparison to the DCT coefficient. A microcontroller including a data generation unit that stores the data in a conversion coefficient storage area. 5. The microcontroller according to claim 1, wherein a first address signal corresponding to a zigzag scanning method for rearranging the two-dimensional DCT coefficients one-dimensionally is generated. 1
A microcontroller comprising: an address generation circuit, wherein the DCT coefficients are stored in the conversion coefficient storage area in a zigzag scanning order based on the first address signal. 6. The microcontroller according to claim 5, wherein a second address generation circuit generates a second address signal in the order of calculating the DCT coefficients; and the first address signal and the second address. A microcontroller comprising: a switching circuit for switching between a DCT signal and a DCT coefficient in the conversion coefficient storage area based on the switched first or second address signal. 7. The microcontroller according to claim 3, wherein a plurality of tables corresponding to types of images are stored in the coefficient memory in advance, and the conversion execution unit includes the plurality of tables. The two-dimensional DCT coefficient is divided into a plurality of areas, each DCT coefficient is compared with a threshold set corresponding to the area including the DCT coefficient, and the number of DCT coefficients larger than the threshold is determined for each area. The quantization execution means selects one of the plurality of tables based on the number stored for each area, and uses the selected table to generate the DCT coefficient. A microcontroller adapted to execute a quantization process on. 8. The microcontroller according to claim 7, wherein the table determination circuit includes: a threshold register that stores a threshold set for each of a plurality of regions of the divided code data; and the input code data. And a comparator that compares a threshold stored in a threshold register of the area where the code data is present, and outputs a signal when the code data is larger than the threshold based on the comparison result; and A counter provided correspondingly and configured to count up based on a signal from the comparator.