JPH10262087A - Line driver circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a line river circuit, capable of eliminating the need for providing a tertiary winding in a transformer which is connected to a transmission line, generating bipolar signals to which undershoot is added and being miniaturized by semiconductor integration. SOLUTION: This circuit is provided with a first switch 26, connected between one end of a primary winding 22 of a transformer T10 connected to the transmission line and one of a power source and the ground, a first variable current source 27 connected between one end of the primary winding 22 and the other of the power source and the ground, a second switch 28 connected between the other end of the primary winding 22 and on the power source and the ground and a second variable current source 29, connected between the other end of the primary winding 22 and the other one of the power source and the ground. Thus, after outputting a pulse main part waveform by activating the first variable current source 27 and the second switch 28, an undershoot waveform is outputted by activating a second variable current source 29 and the first switch 27, and the need for providing the tertiary winding in the transformer T10 is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line driver circuit, and more particularly, to a line driver circuit for transmitting a bipolar signal to which an undershoot is added to a coaxial or balanced transmission line.

[0002]

2. Description of the Related Art In a system for transmitting digital data, it is specified that an undershoot is added when a bipolar signal is transmitted to a transmission line. FIG.
FIG. 6 shows a configuration diagram of an example of a conventional line driver circuit.
In the figure, a driving circuit 10 is connected to a primary winding 12 of a transformer T1.
Supplies a pulsed current + i or -i. Both ends of the secondary winding 13 of the transformer T1 are connected to the transmission line 14. A resistor 18 and a coil 19 are connected to both ends of the tertiary winding 16 of the transformer T1. This tertiary winding 1
6 and a circuit composed of the resistor 18 and the coil 19,
An undershoot occurs at the falling portion of the positive polarity pulse and the rising portion of the negative polarity pulse sent to the transmission line 14 (the portion where the absolute value of the pulse amplitude changes from the decreasing direction to the reverse polarity increasing direction). Is called an undershoot.)
Is added. In other words, in the case of a positive pulse, even if the pulse falls and the amplitude becomes zero, the coil 19 continues to flow the current until the residual magnetic flux becomes zero. A direction undershoot occurs.
Similarly, in the case of a negative polarity pulse, a positive undershoot occurs at the trailing edge.

[0003]

The conventional circuit requires a transformer T1 having first to third windings 10, 12, and 16,
The transformer T1 has a large number of windings, and thus becomes large. In addition, there is a problem that the cost increases because the semiconductor integration cannot be performed. SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has three transformers connected to a transmission path.
It is an object of the present invention to provide a line driver circuit which can generate a bipolar signal to which an undershoot is added without providing a secondary winding and which can be downsized by semiconductor integration.

[0004]

According to a first aspect of the present invention, in a line driver circuit for transmitting a digital signal to a transmission line, one end of a primary winding of a transformer coupled to the transmission line, a power supply, A first switch connected to one of the grounds; one end of the primary winding; a first variable current source connected between a power supply and the other of the ground; , A second switch connected between the power supply and one of the grounds, and a second variable current connected between the other end of the primary winding and the other of the power supply and the ground A first variable current source and a second switch are activated, and the second variable current source and the first switch are activated to transmit a digital signal.

For this reason, the first variable current source and the second switch are activated to output, for example, a pulse main part waveform of a positive polarity pulse, and then the second variable current source and the first switch are activated. Can be activated to output an undershoot waveform of a positive polarity pulse, eliminating the need to provide a tertiary winding in the transformer to add undershoot.
Further, the circuit can be integrated into a semiconductor.

According to a second aspect of the present invention, in the line driver circuit according to the first aspect, each of the first and second switches is gradually increased according to the current flowing from the second and first variable current sources. Switch. Therefore, the first and second
At the time of switching of the first switch, generation of switching noise is prevented.

[0007] The invention described in claim 3 is the first or second invention.
4. The line driver circuit according to claim 1, wherein the first and second variable current sources are configured to switch and select one of a plurality of current mirror input units having different current values from each other and the plurality of current mirror input units. 1 switch section,
A current mirror output unit connected to the current mirror input unit selected by the first switch unit and outputting a current.

Thus, the main pulse waveform and the undershoot waveform can be formed by the first and second variable current sources. According to a fourth aspect of the present invention, in the line driver circuit according to the first aspect, when the first and second variable current sources output a low level of a digital signal, they output a small current.

For this reason, the delay when the digital signal changes from the low level output to the high level output can be reduced. According to a fifth aspect of the present invention, in the line driver circuit of the third aspect, there is provided a low-pass filter for suppressing a rapid change in a current value when the first switch is switched.

Therefore, the output current can be changed smoothly when the first switch is switched. According to a sixth aspect of the present invention, in the line driver circuit of the fifth aspect, a buffer for holding an output level of each of the plurality of current mirror input units is provided.

Thus, it is possible to prevent the output level of the current mirror input section from being lowered in order to charge the capacitance of the low-pass filter when the first switch is switched. According to a seventh aspect of the present invention, in the line driver circuit according to the sixth aspect, the buffer includes an input switch, a capacitor, and an output switch, and an output of the buffer is selected as an input of the current mirror output unit. When not present, the input switch is closed, the output switch is opened, and when the output of the buffer is selected as the input of the current mirror output unit, the input switch is opened, and the output switch is turned off. Close.

Therefore, it is possible to handle a low-level voltage between the current mirror circuits as compared with a buffer such as a voltage follower. The invention according to claim 8 is the line driver circuit according to claim 1 or 2, wherein the first and second variable current sources include a plurality of current sources;
A second switch unit for selecting whether or not to flow each current of the plurality of current sources through a first resistor; a slew rate limited operational amplifier supplied with a voltage generated in the first resistor; Voltage-current conversion means for converting the output voltage of the operational amplifier into a current and outputting the current.

Thus, the main pulse waveform and the undershoot waveform can be formed by the first and second variable current sources. According to a ninth aspect of the present invention, in the line driver circuit of the eighth aspect, the slew rate value of the operational amplifier is variably controlled. For this reason, the rising and falling slopes for forming the main pulse waveform and the undershoot waveform can be varied.

According to a tenth aspect of the present invention, in the line driver circuit according to the eighth or ninth aspect, a slew rate value of the operational amplifier is limited by a capacitance and a bias current, and the slew rate value is limited. The bias current is determined based on the charge / discharge current of the oscillation capacitor in a phase-locked loop using the oscillation capacitor formed in the same process.

Therefore, it is possible to prevent a change in the slew rate value due to the influence of the process variation, and to improve the accuracy of the output waveform of the line driver circuit. According to an eleventh aspect of the present invention, in the line driver circuit according to the eighth aspect, the voltage-current converting means includes a second resistor formed on the same semiconductor chip as the first resistor, and Means for causing the second resistor to generate a voltage proportional to the voltage generated at the resistor.

By utilizing the first and second resistors having a small relative error on the same semiconductor chip, voltage-current conversion with a small amplitude error can be performed without using an external element.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, one end of a primary winding 22 of the transformer T10 is connected to one end of a first switch 26 and one end of a first variable current source 27, and the other end of the primary winding 20 is connected to a second switch 28.
And one end of a second variable current source 29. Switches 26 each of the other end is connected to a power source V _D, variable current source 27 and 29 respectively of the other end is grounded. The secondary winding 23 of the transformer T10 is connected to a transmission path.

As shown in FIG. 2C, the variable current source 27 supplies a variable current i1 in conjunction with the turning on of the switch 28 shown in FIG. 2B. Here, the variable current i1 has a pulse main portion waveform P1 and an undershoot portion waveform P2.
Similarly, as shown in FIG. 2D, the variable current source 29 interlocks with the turning on of the switch 26 shown in FIG.
Flow 2 The variable current i2 has a pulse main portion waveform P3 and an undershoot portion P4. The above waveforms P1 and P4
2 and the combination of the waveforms P3 and P4, a positive or negative pulse having an undershoot as shown in FIG. 2E is generated between both ends of the secondary winding 23 and transmitted to the transmission line.

The switches 26 and 28 are not turned on at the same time, and the output impedance of the variable current sources 27 and 29 is sufficiently larger than the characteristic impedance of the transmission line seen from the primary side of the transformer T10. In this way,
After activating the variable current source 27 and the switch 28 and outputting the main pulse waveform of the positive pulse, the variable current source 29 and the switch 26 are activated and outputting the undershoot waveform of the positive pulse. Therefore, it is not necessary to provide a tertiary winding in the transformer to add an undershoot, and the circuit can be integrated into a semiconductor.

FIG. 3 is a circuit diagram of a main part of the embodiment of FIG. In the figure, an n-channel MOS transistor t11
, T13, and t15 each have a current mirror configuration and constitute an output section of the variable current source 29. The p-channel MOS transistor t12 for flowing the source current of the transistor t13 forms a current mirror with the p-channel MOS transistor t14 and forms the switch 26.
The variable current i11 is supplied to the drain of the transistor t11 from the terminal 30, the drain of the transistor t14 is connected to one end of the primary winding 22, and the drain of the transistor t15 is connected to the other end of the primary winding 22. . A matching resistor 24 is connected between both ends of the primary winding 22.

The n-channel MOS transistor t2
1 and t23 and t25 each have a current mirror configuration and constitute an output section of the variable current source 27. Further, a p-channel MOS transistor t22 through which a source current of the transistor t23 flows is replaced with a p-channel MOS transistor t24.
And a current mirror to constitute the switch 28. The variable current i21 is supplied to the drain of the transistor t21 from the terminal 31, the drain of the transistor t24 is connected to the other end of the primary winding 22, and the transistor t2
5 is connected to one end of the primary winding 22.

The switches SW11 and SW21 are provided so as to be turned on when the switches 26 and 28 are turned off and to extract charges from the gates of the transistors t12, t14, t21 and t24. Here, the transistor t
The gate length of each of 11 to t15 and t21 to t25 is 11 to
Assuming that l5 and the gate width are w1 to w5, the transistor t
The drain currents i14 and i15 of the transistors 14 and t15 are expressed by the following equations.

[0023]

(Equation 1)

If the transistors t24 and t25 are off when the transistors t11 to t15 are on, the current i1
4, i15 is smaller than transistors t14, t1.
5 will flow. Therefore, when the transistor t14 is set as follows, the transistor t14 operates as a switch rather than as a current source.

[0025]

(Equation 2)

In this case, the drain-source voltage of the transistor t14 only needs to be a value enough to perform the switching operation of the transistor t14, and may be a small value. The transistor t24 is similar to the transistor t14. Thus, the transistor t14 (or t24) is the transistor t15 (or t25) of the variable current source 29 (or 27).
The switching is performed gradually in accordance with the rise and fall of the current i15 (or i25) flowing through the circuit, thereby preventing the generation of switching noise.

FIG. 4 shows the principle of the first embodiment of the waveform generator of the variable current source. In the figure, n-channel MOS transistors 32 and 33 form a current mirror when switch 35 is connected to transistor 32 side (a side), and n-channel MOS transistors 33 and 34 A current mirror is configured when connected to the b side). Transistor 33
Is grounded via a capacitor C, and the gate of the transistor 34 is connected to a switch 36 and a capacitor C.
₀ (C ₀ ≫C), and connected to a switch 35 via a resistor R. The buffer 37
The switch 36 as an input switch, the switch 35 and output switch uses a capacitance of the capacitor C _0.
The above constant current sources 38 and 39 and transistors 32 and 34
Corresponds to the current mirror input section, and the switch 35 is in the first position.
The transistor 33 corresponds to a current mirror output unit, and the resistor R and the capacitor C correspond to low-pass filter means.

Here, when the switch 35 is connected to the a side, the capacitor C is charged by the current i01 of the constant current source 38, the transistors 32 and 33 perform a current mirror operation, and the current i03 corresponding to the current i01. Flows. When the switch 35 is on the a side, the switch 36 is closed and the capacitor C ₀ is charged by the constant current source 39. Next, when the switch 35 is switched to the side b as shown in FIG. 5A, the switch 36 is opened together with this. Since C ₀ ≫C, the buffer 37 holds the gate voltage of the transistor 34, the capacitor C is charged from the capacitor C ₀ by the time constant CR, and the current i03 increases as shown in FIG. 5B.

FIG. 6 is a circuit diagram of a first embodiment of the waveform generator. In the figure, transistors t31 and t35 correspond to transistors 32 and 33, respectively, and transistors t32 and t35
33 and t34 correspond to the transistor 34, and the buffer B
u1 to Bu3 correspond to the buffer 37 and the capacitor C ₃₄
Corresponds to the capacitor C. Also, switches SW34 to
SW37 corresponds to the switch 35, and includes resistors R31 to R33.
Corresponds to the resistor R. A pulse main part waveform is generated in the above part.

The transistors t41 and t44 correspond to the transistors 32 and 33, respectively, and the transistors t42 and t4
3 corresponds to the transistor 34, and the buffers Bu4 and Bu
5 corresponds to the buffer 37, and the capacitor C ₄₃ corresponds to the capacitor C. The switches SW43 to SW45 correspond to the switch 35, and the resistors R41 and R42 correspond to the resistor R. An undershoot waveform is generated in the above section.

When the switch SW51 or SW62 is on, the p-channel MOS transistor t51 is n-channel M
A current mirror is formed with the OS transistor t35 or t44. The transistor t51 forms a current mirror with the p-channel MOS transistor t52, the transistor t52 forms a current mirror with the n-channel MOS transistor t53, and the transistor t53 forms a current mirror with the n-channel MOS transistor t54. Of the pulse or the undershoot of the negative pulse.

When the switch SW52 or SW61 is on, the p-channel MOS transistor t61 is n-channel M
A current mirror is formed with the OS transistor t35 or t44. The transistor t61 forms a current mirror with the p-channel MOS transistor t62, the transistor t62 forms a current mirror with the n-channel MOS transistor t63, and the transistor t63 forms a current mirror with the n-channel MOS transistor t64. , Or the undershoot of the positive polarity pulse. The switch S
W53 or SW63 is provided to turn on when the terminal 41 or 42 is off and to extract the gate charge of the transistor t54 or t64.

Here, as shown in FIG. 7A, after the switch SW34 is turned off, FIG. 7B, FIG.
As shown in (D), the switches SW35, SW36, SW
When the transistors 37 are sequentially turned on, the current i35 flowing through the transistor t35 has a pulse main portion waveform as shown in FIG. Similarly, after the switch SW43 is turned off as shown in FIG.
When the switches SW44 and SW45 are sequentially turned on as shown in FIG.
An undershoot portion waveform as shown in FIG.

The switches SW51, SW52, SW
When each of the switches 53 is switched as shown in FIGS. 7 (J), 7 (K) and 7 (L), the current i54 flowing from the terminal 41 becomes as shown in FIG. 7 (P). Switch SW
61, SW62 and SW63 respectively correspond to FIGS. 7 (M), (N),
By switching as shown in (O), the current i64 flowing from the terminal 42 becomes as shown in FIG. 7 (Q).

Before the switch SW53 or SW63 is turned off, the transistor t53 or t63 is ready for the current mirror operation of the transistor t54 or t64, and the variable current sources 27 and 29 can be used in the linear region. In other words, if the switch SW53 or SW63 is turned off and the current starts to flow to the transistor t53 or t63 at the same time, the delay occurs until the transistor t54 or t64 starts to flow the current due to the stray capacitance of the gate of the transistor t53 or t63. There is no delay. In addition, each of the resistors R31 to R42 uses a MOS transistor, and determines the resistance value according to each gate voltage.

Switches SW31 to SW63 used in FIG.
For example, an analog switch shown in FIG. 8 may be used. In FIG. 8, the drains and sources of an n-channel MOS transistor 47 and a p-channel MOS transistor 48 are connected between terminals 45 and 46, respectively, and control signals inverted to each other are supplied to the gates of the transistors 47 and 48.

FIG. 9 shows a principle diagram of a second embodiment of the waveform generator of the variable current source. In the figure, the constant current source 50 is a switch 5
1 is connected to one end of the first resistor R1, and the constant current source 52 is connected to one end of the first resistor R1 via the switch 53. The other end of the resistor R1 is grounded, and one end is connected to a non-inverting input terminal of an operational amplifier (op-amp) 54 having a limited slew rate. The output terminal of the operational amplifier 54 is connected to the gate of the n-channel MOS transistor 55, the drain of the transistor is connected to the output terminal 56, and the source is the operational amplifier 5
4 and is grounded via a second resistor R2. All circuits shown in FIG. 9 are formed on the same semiconductor chip.

Here, as shown in FIG. 10A, when only the switch 51 is on, the current i flowing through the resistor R1
Is only the current i01 from the constant current source 50. FIG.
As shown in FIG. 10B, when the switch 52 is turned on together with the switch 50, the current i flowing through the resistor R1 becomes the current (i01 + i0) from the constant current sources 50 and 52 as shown in FIG.
2). However, since the slew rate of the operational amplifier 54 is limited, the current i
The change of 2 is delayed as shown in FIG.

FIG. 11 shows a circuit diagram of the above slew rate limited operational amplifier. In the figure, p-channel MOS transistors t70 and t71 have a current mirror configuration, and transistor t71 has a current ibias flowing from constant current source 60.
The same amount of current flows through the differential circuit. The p-channel MOS transistors t72 and t73 form a differential circuit, and each gate is connected to an inverting input terminal 61 and a non-inverting input terminal 62.

N channel MOS transistors t74, t
75 respectively pass the drain currents of the transistors t72 and t73, and the n-channel MOS transistors t76 and t73
77 constitutes a current mirror with transistors t74 and t75, respectively, and a p-channel MOS transistor t7
8, t79 respectively allow the drain currents of the transistors t76, t77 to flow. The transistors t78, t79 form a current mirror, the drain of the transistor t77 is connected to the output terminal 63 is grounded through a capacitor C ₄₅ for phase compensation.

In this circuit, the slew rate ΔV / Δt = i
represented by the out / C _45. Here, ΔV is the voltage change of the terminal 63, Δt is time, and iout is the transistor t7.
9 is the drain current. FIG. 12 shows a circuit diagram of a modified example of the slew rate limiting type operational amplifier. In the figure, the same parts as those in FIG. 11 are denoted by the same reference numerals. The p-channel MOS transistors t70 and t71 have a current mirror configuration, and the transistor t71 has a current ibias flowing from the constant current source 60.
The same amount of current flows through the differential circuit. The p-channel MOS transistors t72 and t73 form a differential circuit, and each gate is connected to an inverting input terminal 61 and a non-inverting input terminal 62.

N channel MOS transistors t74, t
75 respectively pass the drain currents of the transistors t72 and t73, and the n-channel MOS transistors t76 and t73
77 constitutes a current mirror with transistors t74 and t75, respectively, and a p-channel MOS transistor t7
8, t79 respectively allow the drain currents of the transistors t76, t77 to flow. The transistors t78, t79 form a current mirror, the drain of the transistor t77 is connected to the output terminal 63 is grounded through a capacitor C ₄₅ for phase compensation.

Further, an n-channel MOS transistor t8
0 forms a current mirror with the transistor t75, and p
The channel MOS transistor t81 is a transistor t7
8 and a current mirror. Transistor t8
0 is connected to the transistor t7 through the switch 64.
7, and the drain of the transistor t81 is connected to the drain of the transistor t79 via the switch 65.

In this modification, when the switches 64 and 65 are open, the operation is the same as that in FIG. However, when the switches 64 and 65 are closed, the current iout flowing to the connection point between the switches 64 and 65 becomes twice as large as that in FIG. 11 and the slew rate can be changed. This makes it possible to change the rising and falling slopes. FIG. 13 is a circuit diagram of a second embodiment of the waveform generator. In the figure, constant current sources 70 to 74 are connected to one end of a resistor R71 via respective switches SW70 to 74, and the other end of the resistor R71 is grounded. Resistance R71
Is connected to the non-inverting input terminal 62 of a slew rate limited operational amplifier 75 having the same configuration as that of FIG. The above constant current sources 70, 71, 72 are for generating a pulse main part waveform of a positive polarity pulse, and the switches SW70, SW71,
SW72 is turned on and used. The constant current sources 73 and 74 are used to generate an undershoot waveform of a negative polarity pulse and are used by turning on the switches SW73 and SW74. The output terminal 63 of the operational amplifier 75 is connected to the gate of the n-channel MOS transistor t90, the source of which is connected to the resistor R72.
, And is connected to the inverting input terminal 61, and the drain is connected to the terminal 76.

The constant current sources 80 to 84 are connected to switches SW80 to
84 and one end of a resistor R81.
The other end of 81 is grounded. The other end of the resistor R81 is shown in FIG.
2 is connected to the non-inverting input terminal 62 of the slew rate limiting type operational amplifier 85 having the same configuration as that of the operational amplifier 85 of FIG. The above constant current source 8
Numerals 0, 81, and 82 are for generating a pulse main part waveform of a negative pulse, and are used by turning on the switches SW80, SW81, and SW82. The constant current sources 83 and 84 are for generating a waveform of an undershoot portion of a positive polarity pulse.
3. Turn on SW84 and use. The output terminal 63 of the operational amplifier 85 is connected to the gate of the n-channel MOS transistor t91, the source is grounded via the resistor R82 and connected to the inverting input terminal 61, and the drain is connected to the terminal 86.

Here, the switches SW70 to SW74 are switched as shown in FIGS. 14A to 14E, respectively.
The switches 64 and 65 in the operational amplifier 75 are connected as shown in FIG.
By switching as shown in FIG.
A constant current i71 having a waveform shown in FIG. Further, the switches SW80 to SW84 are set as shown in FIG.
14 (L), and switches 64 and 65 in the operational amplifier 85 are switched as shown in FIG. 14 (M), so that a current i81 having a waveform shown in FIG. Flow in.

[0047] Figure 11, so that the slew rate value varies the capacitance value of the capacitor C ₄₅ is varied by variations in the process of an operational amplifier as shown in FIG. 12. FIG. 15 shows a circuit that varies the current ibias in order to keep the slew rate constant even when the capacitance value varies.
FIG. 15 shows a PLL (Phase Locked Loop) for clock recovery, which is integrated on the same semiconductor chip as the line driver circuit of the present invention.

In FIG. 15, the phase comparator 91 is connected to the terminal 9
A phase comparison is made between a reference clock supplied from 0 and a clock output from a VCO (voltage controlled oscillator) 93, and the obtained phase error voltage is passed through a low-pass filter 92 to a V / I converter 94 in the VCO 93. Supplied to V / I
Converter 94 outputs a current corresponding to the phase error voltage, and this current is current mirrored from MOS transistor t100 to MOS transistors t101 and t102,
The current is mirrored from the MOS transistor t103 through which the drain current of the transistor t101 flows to the MOS transistor t104.

Each of the switches SW90 and SW91 is a VCO
To turn on / off alternately according to the output clock to charge / discharge the capacitor C _VCO . The voltage of the capacitor C _VCO is compared with the reference voltages V _ref1 and V _ref2 by comparators 95 and 96, respectively, and the flip-flop 97 is set / reset by the outputs of the comparators 95 and 96, and the clock is output from the flip-flop 97. .

In this circuit, the output clock of the VCO 93 operates so as to be phase-synchronized with the reference clock. Therefore, even if the capacitance of the capacitor C _VCO varies, the transistor t10
The gate potential of 0 changes to cancel the variation, and the transistor t100 and the MOS transistor t105
Is a current mirror configuration, and the transistor t105
Is the constant current source 60 in FIGS.

Here, the cycle of the reference clock is T0,
When the charge / discharge current of the capacitor C _VCO is ivco,
The following equation holds.

[0052]

(Equation 3)

Also, because of the current mirror configuration, iout @ ibias @ ivco @ iout = kivco (k is a constant). From this, the slew rate iout / C is expressed as follows.

[0054]

(Equation 4)

In this equation, C _VCO / C ₄₅ is always constant since it is an element in the same semiconductor chip, and k, V _ref1 and V
_{Since ref2} and T0 are also constant, the slew rate can be constant.

[0056]

According to a first aspect of the present invention, there is provided a line driver circuit for transmitting a digital signal to a transmission line, wherein one end of a primary winding of a transformer coupled to the transmission line, one of a power supply and one of a ground. A first switch connected between the other end of the primary winding, a first variable current source connected between the power supply and the other of the ground, and the other end of the primary winding. A second switch connected between one of the power supply and the ground, a second variable current source connected between the other end of the primary winding, and the other of the power supply and the ground. And the first
Activate the variable current source and the second switch, and activate the second variable current source and the first switch to transmit a digital signal.

For this reason, after activating the first variable current source and the second switch and outputting, for example, the main pulse waveform of the positive polarity pulse, the second variable current source and the first switch are activated. Can be activated to output an undershoot waveform of a positive polarity pulse, eliminating the need to provide a tertiary winding in the transformer to add undershoot.
Further, the circuit can be integrated into a semiconductor.

The invention described in claim 2 is the same as the claim 1.
In the line driver circuit described above, each of the first and second switches performs switching gradually in accordance with the current flowing from the second and first variable current sources. Therefore, generation of switching noise at the time of switching of the first and second switches is prevented.

Further, the invention described in claim 3 is the first invention.
3. The line driver circuit according to claim 2, wherein
The second variable current source includes a plurality of current mirror input units having different current values from each other, a first switch unit for switching and selecting one of the plurality of current mirror input units, and a first switch. A current mirror output unit connected to the current mirror input unit selected by the unit and outputting a current.

Thus, the main pulse waveform and the undershoot waveform can be formed by the first and second variable current sources. The invention according to claim 4 is the line driver circuit according to claim 1, wherein the first and second variable current sources output a low level of a digital signal.
Outputs a very small current.

For this reason, the delay when the digital signal changes from the low level output to the high level output can be reduced. According to a fifth aspect of the present invention, in the line driver circuit of the third aspect, the line driver circuit further includes a low-pass filter for suppressing a sudden change in a current value when the first switch is switched.

Therefore, the output current can be smoothly changed when the first switch is switched. According to a sixth aspect of the present invention, in the line driver circuit of the fifth aspect, a buffer for holding an output level of each of the plurality of current mirror input units is provided.

As a result, it is possible to prevent the output level of the current mirror input section from being lowered in order to charge the capacitance of the low-pass filter means when the first switch means is switched. According to a seventh aspect of the present invention, in the line driver circuit according to the sixth aspect, the buffer includes an input switch, a capacitor, and an output switch, and an output of the buffer is selected as an input of the current mirror output unit. When not present, the input switch is closed, the output switch is opened, and when the output of the buffer is selected as the input of the current mirror output unit, the input switch is opened, and the output switch is turned off. Close.

For this reason, it is possible to handle a low-level voltage between the current mirror circuits as compared with a buffer such as a voltage follower. The invention according to claim 8 is the line driver circuit according to claim 1 or 2, wherein the first and second variable current sources include a plurality of current sources and a current of each of the plurality of current sources. A second switch unit for selecting whether or not the current flows through the first resistor, a slew rate limited operational amplifier supplied with a voltage generated in the first resistor, and a converter for converting an output voltage of the operational amplifier into a current. And a voltage-current conversion means for outputting the output.

Thus, the main pulse waveform and the undershoot waveform can be formed by the first and second variable current sources. According to a ninth aspect of the present invention, in the line driver circuit of the eighth aspect, the slew rate value of the operational amplifier is variably controlled.

Therefore, the rising and falling slopes for forming the main pulse waveform and the undershoot waveform can be varied. According to a tenth aspect of the present invention, in the line driver circuit according to the eighth or ninth aspect, a slew rate value of the operational amplifier is limited by a capacity and a bias current, and a capacity that limits the slew rate value is The bias current is determined based on the charge / discharge current of the oscillation capacitor in a phase-locked loop using the oscillation capacitor formed in the same process.

For this reason, it is possible to prevent a change in the slew rate value due to the influence of the process variation, and to improve the accuracy of the output waveform of the line driver circuit. According to an eleventh aspect of the present invention, in the line driver circuit according to the eighth aspect, the voltage-current converting means includes a second resistor formed on the same semiconductor chip as the first resistor, and Means for causing the second resistor to generate a voltage proportional to the voltage generated at the resistor.

By using the first and second resistors having a small relative error on the same semiconductor chip, voltage-current conversion with a small amplitude error can be performed without using an external element.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of the present invention.

FIG. 2 is a signal waveform diagram of each part in FIG.

FIG. 3 is a circuit diagram of a main part of the present invention.

FIG. 4 is a principle diagram of a waveform generation unit.

FIG. 5 is a signal waveform diagram of each unit in FIG. 4;

FIG. 6 is a circuit diagram of a waveform generation unit.

FIG. 7 is a signal waveform diagram of each unit in FIG. 6;

FIG. 8 is a circuit diagram of an analog switch.

FIG. 9 is a principle diagram of a waveform generation unit.

FIG. 10 is a signal waveform diagram of each unit in FIG. 9;

FIG. 11 is a circuit diagram of an operational amplifier.

FIG. 12 is a circuit diagram of an operational amplifier.

FIG. 13 is a circuit diagram of a waveform generator.

14 is a signal waveform diagram of each part in FIG.

FIG. 15 is a circuit configuration diagram of a PLL.

FIG. 16 is a configuration diagram of a conventional circuit.

[Explanation of symbols]

T10 transformer 22 primary winding 23 secondary winding 26,28,35 switches 27, 29 a variable current source 38, 39 constant current source T11～t105 MOS transistor Bu1~Bu5 buffer C ₁₁ -C ₄₅ capacitor

Continuation of the front page (51) Int.Cl. ⁶ Identification code FI H04L 25/49 H03K 19/00 101F (72) Inventor Toshiyuki Sakai 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited ( 72) Inventor Yasuaki Takeuchi 2-1, Kita-Ichijo-Nishi, Chuo-ku, Sapporo-city, Hokkaido Inside Fujitsu Hokkaido Digital Technology Co., Ltd.

Claims (11)

[Claims] 1. A line driver circuit for sending a digital signal to a transmission line, comprising: one end of a primary winding of a transformer coupled to the transmission line;
A first switch connected between one of a power supply and the ground; a first end of the primary winding; a first variable current source connected between the power supply and the other of the ground; A second switch connected between the other end of the winding and one of a power supply and the ground; a second switch connected between the other end of the primary winding and the other of the power supply and the ground. A variable current source; activating the first variable current source and a second switch;
Further, the line driver circuit activates the second variable current source and the first switch to transmit a digital signal. 2. The line driver circuit according to claim 1, wherein each of said first and second switches performs switching gradually in accordance with a current flowing from said second and first variable current sources. Line driver circuit. 3. The line driver circuit according to claim 1, wherein the first and second variable current sources include: a plurality of current mirror input units having different current values; and a plurality of current mirror input units. A first switch unit for switching and selecting any one of the first switch units; and a current mirror output unit connected to the current mirror input unit selected by the first switch unit and outputting a current. Line driver circuit. 4. The line driver circuit according to claim 1, wherein said first and second variable current sources output a minute current when outputting a low level of a digital signal. . 5. The line driver circuit according to claim 3, further comprising a low-pass filter for suppressing a rapid change in a current value when the first switch is switched. 6. The line driver circuit according to claim 5, wherein a buffer for holding an output level of each of the plurality of current mirror input units is provided. 7. The line driver circuit according to claim 6, wherein the buffer includes an input switch, a capacitor, and an output switch, and when an output of the buffer is not selected as an input of the current mirror output unit, Closing the input switch, opening the output switch, and when the output of the buffer is selected as the input of the current mirror output unit, opening the input switch and closing the output switch. A line driver circuit characterized by the above-mentioned. 8. The line driver circuit according to claim 1, wherein the first and second variable current sources are connected to a plurality of current sources, and each of the plurality of current sources is connected to a first resistor. A second switch unit for selecting whether or not to flow; a slew rate limiting type operational amplifier to which a voltage generated in the first resistor is supplied; a voltage / current for converting an output voltage of the operational amplifier to a current and outputting the current A line driver circuit comprising: a conversion unit. 9. The line driver circuit according to claim 8, wherein a slew rate value of said operational amplifier is variably controlled. 10. The line driver circuit according to claim 8, wherein a slew rate value of the operational amplifier is limited by a capacitor and a bias current, and is formed in the same process as the capacitor that limits the slew rate value. A line driver circuit, wherein the bias current is determined based on a charge / discharge current of the oscillation capacitor in a phase-locked loop using the oscillation capacitor. 11. The line driver circuit according to claim 8, wherein the voltage-current conversion means is generated in a second resistor formed on the same semiconductor chip as the first resistor, and in the first resistor. A voltage proportional to the voltage
And a means for causing a resistance of the line driver circuit.