JPH10261703A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that has an element separation structure that can supress an intrusion into the element region of a separation region and can prevent the electrical characteristics of a field effect transistor from deteriorating. SOLUTION: A separation insulator includes upper insulators 4 and 7 being arranged at a side above a silicon substrate 1 and lower insulators 6 and 7 being arranged at a side under the silicon substrate 1. The widths of the lower insulators 6 and 7 are smaller than those of the upper insulators 4 and 7. The lower insulators contain a thermal oxide film 6 that is formed along the side wall and the bottom wall of a channel 5 being formed in the silicon substrate 1 and a silicon oxide film 7 that is formed on the thermal oxide film 6 and is filed into the channel 5. The width of the thermal oxide film 6 is smaller than that of the side wall insulating film 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having an element isolation structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as the degree of integration of a semiconductor integrated circuit device has been remarkably increased, miniaturization of elements has been rapidly advanced. In particular, in a dynamic random access memory (DRAM) as a semiconductor memory device, the degree of integration of the memory increases from 64 megabits (Mb) to 256 megabits (Mb), and further increases to 1 gigabit (Gb) as the storage capacity increases. It is being done. The field effect transistors and capacitors as active elements constituting such a highly integrated memory must each have a miniaturized structure. In order to electrically separate the miniaturized active elements, a fine element isolation structure is required.

One example of a conventional fine element isolation structure is Andre.
s Bryant et al., “Characteristics of CMOS Device I
solation for the ULSI Age ”, International Elect
ronDevices Meeting 1994, IEDM 94-pp.671-674. 33 to 38 are partial cross-sectional views sequentially showing the steps of manufacturing a conventional fine element isolation structure. With reference to these drawings, a conventional method for manufacturing an element isolation structure will be described.

[0004] First, as shown in FIG. 33, a thermal oxide film 2 and a silicon nitride film 3 are formed on a silicon substrate 1. Although not shown, a resist pattern exposed and developed by photolithography is formed on the silicon nitride film 3. The resist pattern has a design separation width W ₀ as shown in FIG. 33. According to the resist pattern, the thermal oxide film 2 and the silicon nitride film 3 are selectively removed by dry etching or the like. In this manner, the thermal oxide film 2 and silicon nitride film 3 is opening having a design separation width W ₀ is formed. The opening serves as a portion for electrically separating active elements such as a field effect transistor. The region of the semiconductor substrate 1 covered with the thermal oxide film 2 and the silicon nitride film 3 is a region for forming an active element such as a field effect transistor.

Next, using the thermal oxide film 2 and the silicon nitride film 3 as a mask, the silicon substrate 1 is selectively removed by dry etching or the like. As a result, as shown in FIG. 34, a groove 5 is formed in a portion to be an element isolation region.

Thereafter, as shown in FIG. 35, a thermal oxidation process is performed to form a thermal oxide film 6 on the inner wall of the groove 5, that is, on the surface of the side wall and the bottom wall. At this time, the thermal oxide film 6 is formed by the progress of thermal oxidation from the side walls and the bottom wall of the trench 5 to the inside of the silicon substrate 1. That is, the thermal oxide film 6
Is formed by converting silicon on the surface of the groove 5 into an oxide film by oxidation. Therefore, thermal oxide film 6 is formed below silicon nitride film 3 and thermal oxide film 2. As a result, in this case, as an insulating film for element isolation,
The thermal oxide film 6 will penetrate by a width indicated by W ₆ in a region where an active element such as a field effect transistor is formed.

[0007] Then, as shown in FIG.
C using (tetraethyl orthosilicate) as raw material
A silicon oxide film 7 is formed so as to fill groove 5 by VD method. At this time, the silicon oxide film 7 is formed so as to extend also on the silicon nitride film 3.

Thereafter, as shown in FIG. 37, the silicon oxide film 7 is removed by dry etching, mechanical chemical polishing (CMP) or the like using the surface of the silicon nitride film 3 as a stopper, so that a flattened surface is obtained. And has substantially the same surface as the surface of the silicon nitride film 3.

Finally, as shown in FIG. 38, silicon nitride film 3 and thermal oxide film 2 are removed. In this way,
A conventional trench-type element isolation structure is formed.

[0010]

FIG. 39 is a partial plan view showing the positional relationship between the element isolation region formed as described above and an element region in which a field effect transistor as an active element is formed. 39A is a partial sectional view taken along line AA in FIG. 39, and FIG. 40B is a partial sectional view taken along line BB in FIG. With reference to these figures, problems of the conventional trench-type element isolation structure will be described below.

The field effect transistors T ₁ and T ₂ have a gate electrode 11, a source region 12, and a drain region 13. Field effect transistor has a design channel width W _3. The design channel width W ₃ is defined by the silicon nitride film 3 in FIG. The two field effect transistors T ₁ and T ₂ are electrically separated by an element isolation region having a design isolation width W ₀ . The design separation width W ₀ is determined when designing the operation of the field effect transistors T ₁ and T ₂ .

However, due to the thermal oxidation step in FIG. 35, the width W ₆ of the design channel width W ₃ in the element region is reduced.
Only, since the effective channel width is eaten by the thermal oxide film, the actual channel width is W _7. Therefore, the channel width of the field effect transistor is reduced,
The electric characteristics of the field effect transistor, in particular, the amount of current flowing through the field effect transistor is reduced. This decrease in the amount of current acts, for example, to increase the time for accumulating charges in the capacitor in the DRAM, and thus causes the operating speed to deteriorate. In a semiconductor device having a logic circuit, a decrease in current flowing through a field effect transistor results in a decrease in signal delay time, which causes a reduction in operation speed, similarly to a DRAM.

Further, as the degree of integration of the semiconductor integrated circuit device increases, the design separation width W ₀ decreases. When designing separation width W ₀ is smaller, it is necessary to further reduce the width W ₆ entering the element region by thermal oxidation film.

In particular, in a DRAM, when the storage capacity becomes 1 gigabit (Gb), the design channel width W ₃ of the field effect transistor becomes 0.2 μm or less. With reduction in the design channel width W _3, designed separation width W ₀ is also 0.1
It is reduced to about 0.2 μm. As described above, when the design channel width W ₃ and the design isolation width W ₀ are reduced, if the trench type element isolation structure is formed as described above, the penetration width W ₆ into the element region is about 0.05 μm. Becomes As a result, it becomes extremely difficult to process the actual channel width W _7. As a result, in a DRAM having a highly integrated storage capacity of 1 gigabit (Gb), the actual decrease in the channel width of the field effect transistor due to the element isolation region being cut into the element region is caused by the drive current of the field effect transistor. And eventually increases the time for storing charge in the capacitor, which is a serious cause of deterioration of the operation speed.

An object of the present invention is to provide a trench-type element isolation structure which does not deteriorate the characteristics of active elements in a semiconductor integrated circuit device, particularly a DRAM having an integrated storage capacity of 1 gigabit (Gb). To provide.

It is another object of the present invention to provide a semiconductor device having an element isolation structure capable of preventing the isolation region from biting into the element region.

A further object of the present invention is to provide a semiconductor device having an element isolation structure which does not reduce the effective channel width of a field effect transistor.

[0018]

A semiconductor device according to one aspect of the present invention includes a semiconductor substrate having a main surface, and an isolation insulator formed on the semiconductor substrate and separating between active elements. . The isolation insulator includes an upper insulator disposed above the main surface of the semiconductor substrate, and a lower insulator connected to the upper insulator and disposed below the main surface of the semiconductor substrate. The width of the lower insulator is smaller than the width of the upper insulator.

In the semiconductor device configured as described above, the width of the lower insulator disposed below the semiconductor substrate is smaller than the width of the upper insulator disposed above the semiconductor substrate. In addition, it is possible to prevent the lower insulator from biting into the region of the active element. Therefore, it is possible to suppress a decrease in the effective channel width of the field effect transistor as the active element. As a result, the electric characteristics of the field effect transistor can be prevented from deteriorating, and the driving current of the field effect transistor can be increased as compared with the related art.

In the semiconductor device according to one aspect of the present invention as described above, the lower insulator includes a thermal oxide film formed along a side wall and a bottom wall of a groove formed in the semiconductor substrate; It is preferable to include a filling insulator layer formed on the thermal oxide film and filling the trench.

The above-mentioned filled insulator layer is preferably an oxide layer. Furthermore, in the semiconductor device according to one aspect of the present invention described above, the upper insulator preferably includes a sidewall insulating film extending above the main surface of the semiconductor substrate.

The sidewall insulating film is preferably made of an oxide film. The sidewall insulating film preferably includes a nitride film, and more preferably, includes an oxide film and a nitride film, or a silicon film and a nitride film.

When the side wall insulating film includes a nitride film as described above, if a contact hole is formed on the isolation region due to a shift such as overlapping in a photolithography process, an oxide for forming the contact hole is used. Etching of the insulating layer stops on the surface of the nitride film of the sidewall insulating film. Therefore, even if the formation position of the contact hole is shifted, the separation characteristics are not deteriorated.

Further, the semiconductor device according to one aspect of the present invention described above preferably further includes an impurity region formed in a region near the main surface of the semiconductor substrate in contact with the outside of the lower insulator. The impurity region contains an impurity of a conductivity type opposite to the conductivity type of the field effect transistor as the active element, and has a higher impurity concentration than the impurity concentration included in the channel region of the field effect transistor.

Since the semiconductor device of the present invention further includes the impurity region, it is possible to suppress the electric field concentration at the channel edge, which is one of the causes of the leak current of the field effect transistor. In other words, by forming the impurity region in contact with the outside of the lower insulator, an element isolation structure capable of effectively suppressing leakage occurring below the threshold value of the field effect transistor is formed. Can be.

A semiconductor device according to another aspect of the present invention includes a semiconductor substrate having a main surface, and an isolation insulator formed on the semiconductor substrate and separating active elements. The isolation insulator is connected to the upper insulator disposed above the main surface of the semiconductor substrate and the upper insulator,
A lower insulator disposed below the main surface of the semiconductor substrate. The width of the lower insulator is smaller than the width of the upper insulator. The lower insulator includes a thermal oxide film formed along a side wall and a bottom wall of the groove formed in the semiconductor substrate, and a filling insulator layer formed on the thermal oxide film to fill the groove. The upper insulator includes a sidewall insulating film extending above the main surface of the semiconductor substrate. The sidewall insulating film is formed on a peripheral side surface of the filled insulating layer. The thickness of the thermal oxide film on the main surface of the semiconductor substrate is smaller than the thickness of the sidewall insulating film.

Another embodiment of the present invention constructed as described above
In a semiconductor device according to one aspect, the present invention provides
As in the semiconductor device according to one aspect, the width of the lower insulator can be smaller than the width of the upper insulator,
Biting of the lower insulator into the field effect transistor can be suppressed. Therefore, a decrease in the effective channel width of the field-effect transistor can be suppressed.
As a result, the electric characteristics of the field effect transistor do not deteriorate, and the driving current can be increased as compared with the related art.

Further, in the semiconductor device according to another aspect of the present invention, the structure in which the width of the lower insulator is smaller than the width of the upper insulator is provided above the main surface of the semiconductor substrate as the upper insulator. This can be realized by forming the extending sidewall insulating film on the peripheral side surface of the filling insulating layer, and making the thickness of the thermal oxide film formed along the sidewall of the groove smaller than the thickness of the sidewall insulating film. Therefore, the structure of the isolation insulating film in which the isolation region does not enter the element region can be easily formed.

In the above-described semiconductor device according to another aspect of the present invention, the filled insulator layer is preferably an oxide layer.

In the above-described semiconductor device according to another aspect of the present invention, the sidewall insulating film is preferably made of an oxide film.

In the above-described semiconductor device according to another aspect of the present invention, the sidewall insulating film preferably includes a nitride film, and more preferably includes an oxide film and a nitride film or a silicon film and a nitride film. preferable.

As described above, since the sidewall insulating film includes the nitride film, the isolation region is displaced by a shift such as an overlap in a photolithography process, similarly to the semiconductor device according to one aspect of the present invention described above. Even if the position of the contact hole is shifted, the bottom wall of the contact hole is formed of the nitride film, so that the electrical characteristics of the isolation do not deteriorate.

Further, the semiconductor device according to another aspect of the present invention described above preferably includes an impurity region formed in a region near the main surface of the semiconductor substrate in contact with the outside of the lower insulator. The impurity region contains an impurity of a conductivity type opposite to the conductivity type of the field effect transistor as the active element, and has a higher impurity concentration than the impurity concentration included in the channel region of the field effect transistor.

By providing the impurity region as described above, one of the causes of the leak current of the field-effect transistor is the same as in the semiconductor device according to one aspect of the present invention.
The electric field concentration at the edge of the channel can be suppressed. An element isolation structure capable of suppressing leakage occurring below the threshold value of the field effect transistor can be formed.

A method of manufacturing a semiconductor device according to another aspect of the present invention includes the following steps. (A) forming a coating layer on the main surface of the semiconductor substrate;

(B) forming an opening in the covering layer to expose the main surface of the semiconductor substrate in a region separating the active elements by selectively removing the covering layer;

(C) forming a sidewall insulating film having a first thickness on the side surface of the opening; (D) forming a groove in the semiconductor substrate by removing a part of the semiconductor substrate using the coating layer and the sidewall insulating film as a mask;

(E) forming a thermal oxide film having a second thickness smaller than the first thickness along the side wall and the bottom wall of the groove;

(F) A step of forming an insulating layer filling the space between the sidewall insulating films and the trench so as to extend over the coating layer.

(G) a step of selectively removing the insulator layer formed on the coating layer. (H) removing the coating layer;

In the method of manufacturing a semiconductor device according to the present invention having the above-described structure, the width of the lower insulator disposed below the semiconductor substrate is larger than the width of the upper insulator disposed above the semiconductor substrate. It is possible to easily realize the structure of the isolation insulator in which the size is reduced. That is, by forming a sidewall insulating film on the side surface of the opening and forming a thermal oxide film thinner than the thickness of the sidewall insulating film along the sidewall of the groove,
The element isolation structure according to the present invention can be realized without using a complicated manufacturing process.

In the above-described method for manufacturing a semiconductor device according to another aspect of the present invention, the insulator layer is preferably formed of an oxide layer.

Further, in the method of manufacturing a semiconductor device according to another aspect of the present invention, it is preferable that the formation of the sidewall insulating film is performed by forming a sidewall oxide film on the side surface of the opening.

In the method of manufacturing a semiconductor device according to another aspect of the present invention, the formation of the sidewall insulating film includes forming an oxide film on the side surface of the opening, and forming a sidewall nitride film on the oxide film. Is preferably performed by forming

The above-mentioned step of forming the sidewall insulating film may be performed by forming a silicon film on the side surface of the opening and forming a sidewall nitride film on the silicon film.

By forming the side wall insulating film so as to include the side wall nitride film as described above, when a contact hole is located above the isolation region due to a shift such as a superposition of a photolithography process in a later step, oxidation may occur. By using etching having selectivity between the film or the silicon film and the sidewall nitride film, the etching can be stopped so that the bottom wall of the contact hole is formed from the surface of the sidewall nitride film. As a result, the separation characteristics do not deteriorate due to the displacement of the contact holes.

Further, in the method of manufacturing a semiconductor device according to another aspect of the present invention, in the step of forming the side wall insulating film, the side wall insulating film is formed so as to have a height lower than the top surface of the coating layer, and the groove is formed. After the forming step, the conductivity type opposite to the conductivity type of the field-effect transistor is used such that the impurity concentration is higher than the impurity concentration introduced into the channel region of the field-effect transistor as an active element using the coating layer as a mask. It is preferable that the method further includes a step of introducing the impurity into the region of the semiconductor substrate below the sidewall insulating film.

Alternatively, in the step of forming the side wall insulating film, the side wall insulating film is formed so as to have a height lower than the top surface of the covering layer, and after the step of forming the thermal oxide film, the active element is formed using the covering layer as a mask. An impurity of a conductivity type opposite to the conductivity type of the field effect transistor is provided in the region of the semiconductor substrate under the sidewall insulating film so as to have a higher impurity concentration than the impurity concentration introduced into the channel region of the field effect transistor. May be further provided.

Alternatively, after the step of forming the opening, the field effect transistor is formed so as to have a higher impurity concentration than the impurity introduced into the channel region of the field effect transistor as an active element by using the covering layer as a mask. The method may further include the step of introducing an impurity of a conductivity type opposite to the conductivity type into a region of the semiconductor substrate exposed through the opening.

By providing any one of the above three manufacturing steps in the method of manufacturing a semiconductor device according to another aspect of the present invention, one of the causes of the leakage current of the field effect transistor is provided.
An element isolation structure capable of suppressing concentration of an electric field at the edge of a channel can be easily realized without using a complicated manufacturing process.

[0051]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) FIGS. 1 to 9 show Embodiment 1 of the present invention.
This will be described with reference to FIG. 1 to 7 are partial cross-sectional views sequentially showing the steps of manufacturing a semiconductor device having an element isolation structure according to the first embodiment of the present invention. FIG. 8 is a partial plan view showing an arrangement relationship between an element region and an isolation region according to the first embodiment of the invention, FIG. 9A is a partial cross-sectional view taken along line AA of FIG. FIG. 9B is a partial sectional view taken along the line BB of FIG.

As shown in FIG. 1, a thermal oxide film 2 having a thickness of 5 to 20 nm is formed on a silicon substrate 1. A silicon nitride film 3 having a thickness of 80 to 200 nm is formed on the thermal oxide film 2.
Is formed using the CVD method.

Although not shown, a resist pattern having a design separation width W ₀ of 0.1 to 0.2 μm is formed on silicon nitride film 3. This design separation width W
₀ corresponds to 0.2μm or less as design the channel width W ₃ of the field effect transistor of the subject being separated. Such values of the design separation width and the design channel width are values adopted in a DRAM having a memory capacity of 1 gigabit (Gb).

The resist pattern having such a fine opening width is formed using a phase shift mask, for example, a Levenson type mask. The light beam used in the photolithography process is Krf line or Arf
Line excimer radar light is used. Alternatively, a resist pattern having a fine opening width as described above can also be formed by X-ray exposure.

Using the resist pattern as a mask, silicon nitride film 3 and thermal oxide film 2 are selectively removed by dry etching so as to have an opening width corresponding to design separation width W ₀ . The region covered by the thermal oxide film 2 and the silicon nitride film 3 corresponds to a region for forming an active element such as a field effect transistor.

The thicknesses of the thermal oxide film 2 and the silicon nitride film 3 need only be such that they are not removed in later steps (such as a groove forming step and a planarizing step). For example, the total thickness of the thermal oxide film 2 and the silicon nitride film 3 may be 100 nm or more. Also, the width of the opening, that is, the design separation width W
₀ is 0.1 to 0.2 μm in the case of a 1 gigabit (Gb) DRAM as described above, but is set as appropriate according to the type of semiconductor integrated circuit device such as a logic circuit.
In any case, the present invention provides that the minimum opening width is 0.2
It is suitable for a semiconductor integrated circuit device having a width of less than μm. The present invention is also applicable to a case where openings of various sizes are formed in the same chip.

Next, as shown in FIG. 2, an insulating film is formed on the entire surface by using the CVD method. By removing the insulating film by etch-back, the side wall insulating film 4 is formed on the side wall of the opening. In this case, the sidewall insulating film 4 is formed by depositing a silicon oxide film on the entire surface and etching back. Alternatively, after the thermal oxide film is formed on the surface of the silicon substrate 1 exposed by the opening, the silicon oxide film may be deposited on the entire surface by using the CVD method and etched back. As the material of the sidewall insulating film, any film having etching selectivity with respect to the silicon nitride film may be used, and examples thereof include a silicon oxide film and a silicon oxynitride film. Sidewall insulating film 4 has a thickness or width W ₁ as shown in FIG. An insulating film such as a silicon oxide film formed on the entire surface has a thickness of 30 to 70 nm.

Thereafter, as shown in FIG. 3, the silicon substrate 1 is selectively removed by dry etching using the silicon nitride film 3 and the side wall insulating film 4 as a mask, and a groove 5 is formed. A mixed gas of chlorine and oxygen is used as an etching gas. The depth of the groove 5 is 0.2 to 0.4 μ
m. The depth of the groove 5 depends on the minimum separation width, but is about 0.3 μm or less in a semiconductor integrated circuit device having a small separation width of 0.2 μm or less.

Next, as shown in FIG. 4, by performing a thermal oxidation process, a thermal oxide film 6 is formed on the inner wall, side walls and bottom wall of the groove 5. The heat treatment is performed so that the thickness W ₂ of the thermal oxide film 6, that is, the width of the region where the silicon substrate 1 is eroded by the thermal oxidation is smaller than the width W ₁ of the sidewall insulating film 4 (see FIG. 2). The thermal oxide film 6 is formed by converting silicon on the surface of the groove 5 into a silicon oxide film by oxidation. At this time, the conditions of the thermal oxidation treatment include controlling the thermal oxidation time, performing the thermal oxidation step in a diluted state by mixing nitrogen gas or the like in an oxidizing atmosphere, and setting the oxidation temperature to a low temperature. And so on. Thus, the thickness W ₂ of the thermal oxide film 6 is reduced to the thickness W _{1 of the} sidewall insulating film.
By setting it smaller than that, the finally formed isolation region does not enter the element region such as the field effect transistor. In other words, the actual separation region maintains the portion above the silicon substrate 1, that is, the design separation width W _0, which is set initially.

Thereafter, as shown in FIG. 5, TEOS (te
Using silicon (traethyl orthosilicate) as a raw material, the silicon oxide film 7 is formed by a CVD method so as to fill the trench 5 and extend over the surface of the silicon nitride film 3.

Then, as shown in FIG. 6, the silicon oxide film 7 is removed by performing a flattening process by dry etching, mechanical chemical polishing (CMP), or the like. At this time, the silicon oxide film 7 is removed using the surface of the silicon nitride film 3 as a stopper.

Finally, the silicon nitride film 3 exposed by flattening
Is removed by wet etching using hot phosphoric acid. Then, the thermal oxide film 2 is removed by wet etching using a hydrofluoric acid aqueous solution. Thus, the element isolation structure according to the present invention is completed as shown in FIG.

As shown in FIG. 8, the thermal oxidation step in FIG.
Therefore, the silicon in the element region is not eaten, and the electric field effect
Transistor design channel width W_ThreeIs maintained and designed
Separation width W₀Is also kept. In FIG. 8, two electric field effects
Transistor T₁And T_TwoOf the gate electrode 11
And a source region 12 and a drain region 13. this
These two field effect transistors T₁And T_TwoIs the design
Separation width W₀Electrically separated by a separation region having
You. Therefore, the field effect transistor T₁And T _TwoIs set
Channel width W as measured_ThreeThe driving current is
It is kept as designed and the electrical characteristics do not deteriorate.
Therefore, if the above element isolation structure is adopted,
Time to store charge in capacitor in DRAM
The cause of operating speed degradation is eliminated without increasing
You. In addition, the element isolation structure as described above is used in the logic circuit.
When applied, the drive current of the field effect transistor is designed
Value, and may reduce signal delay time.
Absent. Therefore, the operation speed of the logic circuit is low.
Does not occur.

As shown in FIG. 9, in the cross section taken along line AA of FIG. 8, the source region 1 made of an n-type impurity region is formed.
The two are electrically separated by a separation insulator.
As shown in FIG. 9B, in a cross section taken along line BB of FIG. 8, a gate electrode 11 and a gate oxide film 14 are formed so as to extend over the isolation insulator. . For example, a silicon oxide film having a thickness of 3 to 6 nm is used as gate oxide film 14, an amorphous silicon film having a thickness of about 50 nm as a lower layer, and a polycide film (for example, a tungsten silicide film) having a thickness of about 50 nm as an upper layer. Or a titanium silicide film).

In the element isolation structure formed in the above manufacturing process, as shown in FIG. 7, the width of the insulator disposed below the silicon substrate 1 is smaller than the width of the insulator disposed above the silicon substrate 1. It is smaller than the width.

When the element isolation structure of the present invention is manufactured in accordance with the first embodiment, the basis is the width of the sidewall insulating film 4. The width of the groove 5 decreases according to the width of the sidewall insulating film 4. When the width of the groove 5 decreases, it becomes difficult to form the groove 5. Therefore, the width of the sidewall insulating film 4, the width of the opening, i.e. not more than about one-third of the minimum dimension of the design separation width W ₀ is considered to be appropriate. For example, if the minimum width W ₀ of the opening is 0.2 μm, it is appropriate that the width of the sidewall insulating film 4 is about 70 nm or less. Therefore,
The thickness of the thermal oxide film 6 needs to be 70 nm or less.

If the width of the groove 5 is small, it is considered that the electrical characteristics of the element isolation structure deteriorate, but the actual isolation ability is determined by the width of the insulator in the final shape. Since the width of the final insulator is the sum of the width of the groove 5 and the width of the thermal oxide film 6, it is possible to cope with the decrease in the width of the groove 5 by increasing the thickness of the thermal oxide film 6. is there. Since the thermal oxide film 6 has better electrical characteristics than the silicon oxide film 7 buried in the groove 5, it is advantageous to increase the thickness of the thermal oxide film 6.
Further, even when the thermal oxide film 6 is thin, the separation capability can be improved by increasing the depth of the groove 5.

(Second Embodiment) A semiconductor device having an element isolation structure according to a second embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. 10 to 17 are partial cross-sectional views sequentially showing the steps of manufacturing the semiconductor device according to the second embodiment of the present invention. FIG. 18 is a partial sectional view (A) along line AA of FIG. 8 and a partial sectional view along line BB of FIG. 8 corresponding to the isolation region and the element region according to the second embodiment of the invention. (B).

As shown in FIG. 10, FIG.
Similarly, a thermal oxide film 2 and a silicon nitride film 3 are formed on a silicon substrate 1.

Next, as shown in FIG. 11, a silicon oxide film 8 having a thickness of 5 to 10 nm is formed on the entire surface by the CVD method.

Thereafter, after a silicon nitride film having a thickness of 20 to 60 nm is formed on the entire surface, the sidewall silicon nitride film 9 is left on the silicon oxide film 8 at the opening by the etch back. At this time, the silicon oxide film 8 is also removed on the silicon nitride film 3 and a part of the exposed surface of the silicon substrate 1. Silicon oxide film 8 may be formed by thermal oxidation. Sidewall silicon nitride film 9 may be a silicon oxynitride film. The material of the side wall silicon nitride film 9 is selected such that the etching ratio of the silicon oxide film to the side wall film is 2 or more so that the side wall silicon nitride film 9 remains when the silicon oxide film is etched.

Thereafter, as shown in FIG. 13, grooves 5 are formed in silicon substrate 1 in the same manner as in the first embodiment.

Then, as shown in FIG. 14, the thermal oxide film 6 is formed on the inner wall, side wall and bottom wall of the groove 5 in the same manner as in the first embodiment.
Is formed. At this time, the thickness W ₂ of the thermal oxide film 6 is the sum of the thicknesses of the silicon oxide film 8 and the side wall silicon nitride film 9,
Or it is set to be smaller than the sum W ₄ width. The thermal oxidation conditions for this are the same as those described in the first embodiment.

Thereafter, as shown in FIG. 15, a silicon oxide film 7 is formed to fill groove 5 in the same manner as in the first embodiment.

Next, as shown in FIG. 16, a flattening process is performed on silicon oxide film 7 in the same manner as in the first embodiment.

The silicon nitride film 3 and the thermal oxide film 2 exposed by the above-mentioned flattening process are removed by wet etching as in the first embodiment. Thus, FIG.
Is completed. In this etching step, a silicon oxide film 8 is formed to selectively remove silicon nitride film 3 from sidewall silicon nitride film 9. If the silicon nitride film 3 is removed by using highly selective etching such as hot phosphoric acid, the thickness of the silicon oxide film 8 can be reduced. Thereby, a thin silicon oxide film 8 may be formed by thermal oxidation.

Also in the second embodiment, since silicon in the element region is not eroded by thermal oxidation, the silicon nitride film 3
, The design channel width W ₃ (see FIG. 8) of the field effect transistor is maintained, and the design separation width W ₀ is also maintained. Therefore, similarly to the first embodiment, the electric characteristics of the field effect transistor do not deteriorate.

Further, in the second embodiment, sidewall silicon nitride film 9 is present at the outer peripheral end of the isolation insulator. In the case where a contact hole reaching the source region 12 or the drain region 13 of the field effect transistor is formed as shown in FIG. 18A, the position of the contact hole 17 is changed due to misalignment of a photolithography process or the like. May overlap. In this case, contact hole 1
7 is formed by etching the interlayer insulating film 15 made of an oxide film using the resist film 16 as a mask. If the sidewall silicon nitride film 9 does not exist, the contact hole reaches the lower part of the groove 5. As a result, the electrical characteristics of the isolation insulator deteriorate. However, since the side wall silicon nitride film 9 exists in the element isolation structure formed in the second embodiment, etching in which a selectivity exists between the silicon nitride film and the oxide film when the contact hole 17 is formed is employed. As a result, even if the silicon oxide film 7 is removed by the etching, it stops at the surface of the side wall silicon nitride film 9. Thereby, the bottom wall of contact hole 17 is formed from the surface of sidewall silicon nitride film 9. Therefore, it is possible to prevent the electrical characteristics of the element isolation structure from deteriorating. The sidewall silicon nitride film 9 can be replaced with another material such as a silicon oxynitride film as long as it is an insulating film having etching selectivity with respect to an oxide film. When the element isolation structure according to the second embodiment is formed by the above-described manufacturing method, the basic structure is the silicon oxide film 8.
And the width or thickness of the sidewall silicon nitride film 9.
The sum of the thickness of silicon oxide film 8 and the width or thickness of sidewall silicon nitride film 9 is the same as sidewall insulating film 4 in the first embodiment.
Corresponding to the width of It is appropriate that the total value is 70 nm or less (when the minimum design separation width is about 0.2 μm). Since the silicon oxide film 8 serves as a stopper for preventing the side wall silicon nitride film 9 from being simultaneously removed in the step of removing the silicon nitride film 3, the silicon oxide film 8 depends on the selectivity of the silicon nitride film and the silicon oxide film with respect to the etching. The thickness of the silicon oxide film 8 is determined.
If the silicon nitride film 3 is removed using hot phosphoric acid or the like, the etching selectivity can be increased, so that the thickness of the silicon oxide film 8 may be 10 nm or less. When the thickness of silicon oxide film 8 is 10 nm or less, the thickness or width of sidewall silicon nitride film 9 becomes 60 nm or more.
Therefore, even if the position of the contact hole is shifted to the separation region by about 60 nm in the formation of the above-described contact hole,
It is considered that the electrical characteristics of the element isolation structure do not deteriorate.

Third Embodiment A semiconductor device having an element isolation structure according to a third embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. 19 to 26 are partial cross-sectional views sequentially showing the manufacturing steps of the semiconductor device according to the third embodiment. 27A and 27B are a partial sectional view taken along line AA of FIG. 8 and a partial sectional view taken along line BB of FIG. 8, corresponding to the third embodiment.

As shown in FIG. 19, a thermal oxide film 2 and a silicon nitride film 2 are formed on a silicon substrate 1 in the same manner as in the first embodiment.

Next, as shown in FIG.
An amorphous silicon film 10 having a thickness of 5 nm is formed.

Thereafter, a silicon nitride film is formed on the entire surface in the same manner as in the second embodiment, and is etched back, so that the side wall silicon nitride film 9 becomes an amorphous silicon film 10.
Remains on At this time, the difference from the second embodiment is that the amorphous silicon film 10 remains without being removed by the etch back.

Next, as shown in FIG.
A groove 5 is formed in the silicon substrate 1 in the same manner as described above. At this time, since the amorphous silicon film 10 is the same silicon as the silicon substrate 1, it is etched and
The upper amorphous silicon film 10 is removed. On the other hand, the amorphous silicon film 10 under the sidewall silicon nitride film 9 forms a sidewall.

Thereafter, as shown in FIG. 23, by performing a thermal oxidation process, a thermal oxide film 6 is formed on the inner wall, the side wall, and the bottom wall of the groove 5 in the same manner as in the first embodiment. At this time, the thermal oxidation is performed such that the thickness W ₂ of the thermal oxide film 6 is smaller than the total value W ₅ of the width or thickness of the sidewall silicon nitride film 9 and the thickness of the amorphous silicon film 10 (see FIG. 21). Processing is performed. The thermal oxidation conditions are the same as those described in the first embodiment. Further, the surface of the amorphous silicon film 10 becomes an oxide film by this thermal oxidation treatment.

Then, as shown in FIG. 24, as in the first embodiment, a silicon oxide film 7 is formed so as to fill groove 5 using TEOS as a raw material.

As shown in FIG. 25, a flattening process is performed on silicon oxide film 7 in the same manner as in the first embodiment.

The silicon nitride film 3 and the thermal oxide film 2 exposed by this flattening process are removed by wet etching as in the first embodiment. Thus, FIG.
The element isolation structure is completed as shown in FIG.

Also in the third embodiment, since the silicon in the element region is not eroded by the thermal oxidation, the design channel width W ₃ (see FIG. 8) of the field effect transistor defined by the silicon nitride film 3 is maintained, and the design is continued. The separation width W _{0 is} also maintained. Therefore, the electric characteristics of the field effect transistor do not deteriorate.

Further, also in the third embodiment, since the side wall silicon nitride film 9 is present at the outer peripheral end of the isolation insulator, it is possible to prevent the deterioration of the electrical characteristics of the element isolation structure as in the second embodiment. Can be. As described in the second embodiment, sidewall silicon nitride film 9 can be replaced with an insulating film having selectivity in etching an oxide film. The amorphous silicon film 10 remaining on the side surface of the side wall silicon nitride film 9 becomes an oxide film by thermal oxidation at the time of forming a gate oxide film of the field effect transistor in a later step.

As shown in FIG. 27A, similarly to the second embodiment, even when the position of the contact hole 17 overlaps the isolation region, it is possible to prevent the electrical characteristics of element isolation from deteriorating. Can be.

When the element isolation structure shown in the third embodiment is formed by the above-described manufacturing method, the basic structure is as follows.
These are the thickness of the amorphous silicon film 10 and the thickness or width of the sidewall silicon nitride film 9. Since the amorphous silicon film 10 and the silicon oxide film 8 in the second embodiment correspond to each other, the silicon oxide film 8 in the second embodiment is replaced with the amorphous silicon film 10 in the third embodiment. In the third embodiment, since the selectivity of etching between the amorphous silicon film and the silicon nitride film can be larger than that of the silicon oxide film, the thickness of the amorphous silicon film 10 is set to 5 nm or less. be able to.

(Embodiment 4) Further, by adding a step of introducing an impurity to the manufacturing method described in Embodiments 1 to 3 above, an extra portion equal to or less than the threshold value of a field effect transistor to be separated is obtained. Leakage current can be reduced. The electric field tends to concentrate at the boundary between the field effect transistor and the isolation region. Leakage current occurs due to electric field concentration. The above-described electric field concentration can be suppressed by introducing an impurity at a higher concentration than the impurity introduced into the channel region of the field-effect transistor into the boundary between the field-effect transistor and the isolation region. In a fourth embodiment, a method for introducing this impurity will be described. Here, an n-type field effect transistor will be described as an example.

The impurity introduced into the channel of the n-type field effect transistor is usually boron, and is realized by implanting boron or boron fluoride (BF ₂ ) ions in the manufacturing process. Further, the concentration of the electric field can be suppressed whether the high concentration impurity region is formed at the edge of the field effect transistor or at the edge of the isolation region.

Since it is difficult for a current to flow in an impurity region having a high concentration, an effective channel width of the field effect transistor is reduced when formed at the edge of the field effect transistor, and the drive current of the field effect transistor is reduced. Therefore, it is more advantageous to form it at the edge of the separation region.

In the present invention, since the width of the isolation insulator disposed below the silicon substrate is smaller than the width of the isolation insulator disposed above the silicon substrate, the width of the isolation insulator below the silicon substrate is reduced. There is a region of the silicon substrate on the outside and below the upper isolation insulator. By introducing an impurity into a region of the silicon substrate below the upper isolation insulator, a high-concentration impurity region can be formed not in the field effect transistor region but in the isolation region.

Hereinafter, the step of introducing impurities will be described with reference to the drawings. An impurity introduction step applicable to the first embodiment will be described.

As shown in FIG. 28, after the groove 5 is formed in the silicon substrate 1, boron is ion-implanted at an acceleration voltage of 40 to 60 keV in an amount of 3 × 10 ^{13 to} 5 × 10 ¹³ / cm ² . The boron ion implantation is indicated by arrow 18. Thus, a boron element-introduced region 19 is formed in the region of the silicon substrate 1 under the sidewall insulating film 4 and outside the trench 5.

Further, as shown in FIG.
After forming the thermal oxide film 6 on the side wall and the bottom wall, 40 to 60 ke
By implanting boron as shown by an arrow 18 at an acceleration voltage of 3 × 10 ^{13 to} 5 × 10 ¹³ / cm ² at an acceleration voltage of V, the outside of the thermal oxide film 6 is formed under the sidewall insulating film 4. The boron element introduction region 19 is formed in the region of the silicon substrate 1.

In any of the steps shown in FIG. 28 or FIG. 29, by setting the height of side wall insulating film 4 lower than the total thickness of silicon nitride film 3 and thermal oxide film 2, boron can be reduced to an electric field. It can be implanted only into the end of the isolation region without being implanted into the region where the effect transistor is formed. At this time, boron is also injected into the bottom wall or the side wall of the groove 5.

Alternatively, as shown in FIG. 30, after the thermal oxide film 2 and the silicon nitride film 3 are formed on the silicon substrate 1, boron may be implanted into the openings. At this time, the boron implantation condition is 3 × 10 ¹³ at an acceleration voltage of 5 to 10 keV.
The injection amount is about 5 × 10 ¹³ / cm ² . After this step, since the trench 5 and the thermal oxide film 6 are formed, the impurities in the portion of the trench 5 and the thermal oxide film 6 disappear, but the boron element introduction region 19 remains at the edge of the isolation region.

In all the above-described examples, the amount of boron implanted is set at least three times the amount of boron implanted into the channel region of the field effect transistor. For example, implantation conditions of boron into the channel region of the field effect transistor is an acceleration voltage 20 keV, implantation of 1 × 10 ¹³
/ Cm ² .

In all of the above-described manufacturing steps, boron introduced to the edge of the isolation region acts to suppress the extension of the depletion layer from the source region or the drain region and to improve the isolation characteristics.

FIGS. 28 to 30 show the first embodiment.
Has been described, but the present invention can be easily applied to the second and third embodiments.

FIG. 31 is a partial plan view showing an arrangement relationship between an isolation region and an element region. (A) of FIG. 32 shows A of FIG.
FIG. 32B is a partial cross-sectional view taken along the line A. FIG.
FIG. 4 is a partial cross-sectional view taken along line -B. As shown in FIG.
An electric field concentration occurs in a portion 20 which is in contact with the separation region between the field effect transistors T ₁ and T ₂ . The high-concentration impurity regions formed in the above manufacturing steps are shown in FIGS.
As shown in FIG.
Is formed as The boron diffusion region 21 is the side wall insulating film 4
Under the silicon substrate 1. By providing the boron diffusion region 21, electric field concentration in the region 20 can be suppressed. As a result, a leak current generated below the threshold value of the field effect transistor can be suppressed.

[0105]

As described above, according to the semiconductor device according to one aspect of the present invention, the width of the lower insulator disposed below the semiconductor substrate is equal to the width of the upper insulator disposed above the semiconductor substrate. Since the isolation insulator is formed so as to be smaller than the width of the body, a decrease in the channel width of the field-effect transistor can be suppressed, whereby a decrease in the drive current can be suppressed. There is no deterioration in characteristics. As a result, when the element isolation structure of the present invention is applied to a highly integrated semiconductor device, for example, a 1 gigabit (Gb) class DRAM, it is possible to suppress a decrease in operation speed.

In the semiconductor device according to one aspect of the present invention, the sidewall insulating film is formed to include the silicon nitride film, so that the position of the contact hole is shifted and overlaps with the isolation region. In this case, the electrical characteristics of the element isolation structure do not deteriorate.

In the semiconductor device according to one aspect of the present invention, by providing a high concentration impurity region in a region near the main surface of the semiconductor substrate in contact with the outside of the lower insulator,
Leakage current generated below the threshold value of the field effect transistor can be suppressed.

Further, according to the semiconductor device according to another aspect of the present invention, the width of the lower insulator disposed below the semiconductor substrate is made larger than the width of the upper insulator disposed above the semiconductor substrate. In order to reduce the thickness, a sidewall insulating film extending above the main surface of the semiconductor substrate is provided, and the thickness of the thermal oxide film formed on the sidewall of the groove is made smaller than the thickness of the sidewall insulating film. Can be.

In the semiconductor device according to another aspect of the present invention, by including the silicon nitride film in the side wall insulating film, the electrical characteristics of the element isolation structure are not deteriorated due to the displacement of the contact hole. .

In a semiconductor device according to another aspect of the present invention, a high-concentration impurity region formed in a region near a main surface of a semiconductor substrate in contact with an outer side of a lower insulator is provided. Leakage current generated below the threshold value of the effect transistor can be suppressed.

Further, according to the method of manufacturing a semiconductor device according to another aspect of the present invention, the structure of the semiconductor device according to the present invention as described above can be realized without using a complicated process. .

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view showing a first step in a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a partial cross sectional view showing a second step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a partial cross-sectional view showing a third step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a partial cross sectional view showing a fourth step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a partial cross-sectional view showing a fifth step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a partial cross-sectional view showing a sixth step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a partial cross-sectional view showing a seventh step in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a partial plan view showing an arrangement relationship between an element region and an isolation region formed according to the first, second, and third embodiments of the present invention.

9 is a partial sectional view (A) along the line AA in FIG. 8 and a partial sectional view (B) along the line BB in FIG. 8 according to the first embodiment of the present invention;

FIG. 10 is a partial cross-sectional view showing a first step in a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 11 is a partial cross-sectional view showing a second step in the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 12 is a partial cross-sectional view showing a third step in the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 13 is a partial cross-sectional view showing a fourth step in the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 14 is a partial cross-sectional view showing a fifth step in the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 15 is a partial cross-sectional view showing a sixth step in the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 16 is a partial cross-sectional view showing a seventh step in the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 17 is a partial cross-sectional view showing an eighth step in the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 18 is a sectional view taken along line AA of FIG. 8 according to the second embodiment of the invention;
FIG. 9 is a partial cross-sectional view (A) along a line, and a partial cross-sectional view (B) along a BB line in FIG. 8.

FIG. 19 is a partial cross-sectional view showing a first step in the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 20 is a partial cross-sectional view showing a second step in the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 21 is a partial cross-sectional view showing a third step in the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 22 is a partial cross-sectional view showing a fourth step in the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 23 is a partial cross-sectional view showing a fifth step in the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 24 is a partial cross-sectional view showing a sixth step in the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 25 is a partial cross-sectional view showing a seventh step in the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 26 is a partial cross-sectional view showing an eighth step in the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 27 is a sectional view taken along line AA of FIG. 8 according to the third embodiment of the invention;
FIG. 9 is a partial cross-sectional view (A) along a line, and a partial cross-sectional view (B) along a BB line in FIG. 8.

FIG. 28 is a partial cross-sectional view showing one example of a boron ion implantation step in Embodiment 4 of the present invention.

FIG. 29 is a partial cross-sectional view showing another example of the boron ion implantation step in Embodiment 4 of the present invention.

FIG. 30 is a partial cross-sectional view showing another example of the boron ion implantation step in Embodiment 4 of the present invention.

FIG. 31 is a partial plan view showing an electric field concentration region.

32 is a partial cross-sectional view (A) along the line AA in FIG. 31 and a partial cross-sectional view (B) along the line BB in FIG. 31;

FIG. 33 shows a first example of a conventional semiconductor device manufacturing method.
It is a fragmentary sectional view showing a process.

FIG. 34 shows a second example of a conventional method for manufacturing a semiconductor device.
It is a fragmentary sectional view showing a process.

FIG. 35 illustrates a third method of manufacturing a conventional semiconductor device.
It is a fragmentary sectional view showing a process.

FIG. 36 illustrates a fourth method of manufacturing a conventional semiconductor device.
It is a fragmentary sectional view showing a process.

FIG. 37 shows a fifth example of the conventional semiconductor device manufacturing method.
It is a fragmentary sectional view showing a process.

FIG. 38 shows a sixth example of a conventional semiconductor device manufacturing method.
It is a fragmentary sectional view showing a process.

FIG. 39 is a partial plan view showing a conventional arrangement relationship between an isolation region and an element region.

40 is a partial cross-sectional view (A) along the line AA in FIG. 39 and a partial cross-sectional view (B) along the line BB in FIG. 39.

[Explanation of symbols]

Reference Signs List 1 silicon substrate, 2 thermal oxide film, 3 silicon nitride film, 4 sidewall insulating film, 5 grooves, 6 thermal oxide film, 7 silicon oxide film, 8 silicon oxide film, 9 sidewall silicon nitride film, 10 amorphous silicon film, 18 boron element ion implantation, 19 boron element introduction region, 21 boron diffusion region, T ₁ , T ₂ field effect transistor, W ₀ design separation width, W ₁ sidewall insulating film thickness, W ₂ thermal oxide film thickness.

Claims (24)

[Claims] A semiconductor substrate having a main surface; and a separation insulator formed on the semiconductor substrate and separating between active elements, wherein the separation insulator is disposed above a main surface of the semiconductor substrate. And a lower insulator connected to the upper insulator and disposed below the main surface of the semiconductor substrate, wherein the width of the lower insulator is greater than the width of the upper insulator. Small, semiconductor devices. 2. The semiconductor device according to claim 2, wherein the lower insulator is formed on the thermal oxide film along a sidewall and a bottom wall of the trench formed in the semiconductor substrate, and fills the trench. The semiconductor device according to claim 1, further comprising a filling insulator layer. 3. The filled insulator layer is an oxide layer.
The semiconductor device according to claim 2. 4. The semiconductor device according to claim 1, wherein said upper insulator includes a sidewall insulating film extending above a main surface of said semiconductor substrate. 5. The semiconductor device according to claim 4, wherein said sidewall insulating film is made of an oxide film. 6. The semiconductor device according to claim 4, wherein said sidewall insulating film includes a nitride film. 7. The semiconductor device according to claim 6, wherein said sidewall insulating film comprises an oxide film and a nitride film. 8. The semiconductor device according to claim 6, wherein said sidewall insulating film comprises a silicon film and a nitride film. 9. The semiconductor device according to claim 1, further comprising an impurity region formed in a region near a main surface of said semiconductor substrate in contact with an outer side of said lower insulator, wherein said impurity region has a conductivity type of a field effect transistor as said active element. 9. The semiconductor device according to claim 1, further comprising an impurity of an opposite conductivity type and having a higher impurity concentration than an impurity included in a channel region of said field effect transistor. 10. A semiconductor substrate having a main surface, and a separation insulator formed on the semiconductor substrate and separating between active elements, wherein the separation insulator is disposed above the main surface of the semiconductor substrate. And a lower insulator connected to the upper insulator and disposed below the main surface of the semiconductor substrate, wherein the width of the lower insulator is greater than the width of the upper insulator. The lower insulator is formed on a side wall and a bottom wall of a groove formed in the semiconductor substrate, and a thermal oxide film is formed on the thermal oxide film to fill the groove. The upper insulator includes a sidewall insulating film extending above a main surface of the semiconductor substrate, and the sidewall insulating film is formed on a peripheral side surface of the filled insulator layer. And at the main surface of the semiconductor substrate, The thickness of the oxide film is smaller than the thickness of the sidewall insulating film, a semiconductor device. 11. The semiconductor device according to claim 10, wherein said filled insulator layer is an oxide layer. 12. The sidewall insulating film is made of an oxide film.
The semiconductor device according to claim 10. 13. The semiconductor device according to claim 10, wherein said sidewall insulating film includes a nitride film. 14. The semiconductor device according to claim 13, wherein said sidewall insulating film comprises an oxide film and a nitride film. 15. The semiconductor device according to claim 13, wherein said sidewall insulating film comprises a silicon film and a nitride film. 16. The semiconductor device according to claim 16, further comprising an impurity region formed in a region near a main surface of said semiconductor substrate in contact with an outer side of said lower insulator, wherein said impurity region is of a conductivity type of a field effect transistor as said active element. 16. The semiconductor device according to claim 10, further comprising an impurity of an opposite conductivity type and having a higher impurity concentration than an impurity included in a channel region of said field effect transistor. 17. A step of forming a coating layer on a main surface of a semiconductor substrate, and selectively removing the coating layer to expose a main surface of the semiconductor substrate in a region separating active elements. Forming an opening in the cover layer; forming a side wall insulating film having a first thickness on a side surface of the opening; and forming the side wall insulating film as a mask using the cover layer and the side wall insulating film as a mask. Forming a groove in the semiconductor substrate by removing a part thereof; and forming a thermal oxide film having a second thickness smaller than the first thickness along a side wall and a bottom wall of the groove. Forming an insulating layer between the sidewall insulating films and filling the groove so as to extend over the coating layer; and selectively forming the insulating layer formed on the coating layer. Removing, and removing the coating layer With a method of manufacturing a semiconductor device. 18. The method according to claim 17, wherein the step of forming the insulator layer includes forming an oxide layer. 19. The method of manufacturing a semiconductor device according to claim 17, wherein said step of forming a sidewall insulating film includes forming a sidewall oxide film on a side surface of said opening. 20. The step of forming the sidewall insulating film includes forming an oxide film on a side surface of the opening and forming a sidewall nitride film on the oxide film.
19. A method for manufacturing a semiconductor device according to item 18. 21. The method according to claim 17, wherein the step of forming the sidewall insulating film includes forming a silicon film on a side surface of the opening and forming a sidewall nitride film on the silicon film. 19. The method for manufacturing a semiconductor device according to item 18. 22. A step of forming the sidewall insulating film, forming a sidewall insulating film so as to have a height lower than a top surface of the coating layer, and masking the coating layer after the step of forming the groove. An impurity of a conductivity type opposite to the conductivity type of the field effect transistor is added to the side wall insulating film so as to have a higher impurity concentration than the impurity concentration introduced into the channel region of the field effect transistor as the active element. 2. The method of claim 1 further comprising the step of introducing into a region of said semiconductor substrate below.
22. The method for manufacturing a semiconductor device according to any one of 7 to 21. 23. A step of forming the side wall insulating film, forming a side wall insulating film so as to have a height lower than a top surface of the coating layer, and forming the thermal oxide film after the step of forming the thermal oxide film. Is used as a mask to remove impurities of the conductivity type opposite to the conductivity type of the field effect transistor so as to have an impurity concentration higher than the impurity concentration introduced into the channel region of the field effect transistor as the active element. 22. The method of manufacturing a semiconductor device according to claim 17, further comprising a step of introducing the semiconductor device into a region of the semiconductor substrate below a film. 24. After the step of forming the opening, using the coating layer as a mask, the impurity concentration is higher than the impurity concentration introduced into the channel region of the field effect transistor as the active element. 22. The semiconductor device according to claim 17, further comprising a step of introducing an impurity having a conductivity type opposite to a conductivity type of the field-effect transistor into a region of the semiconductor substrate exposed by the opening. Production method.