JPH10261288A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a synchronization accuracy while expanding a synchrinizable clock frequency band by generating pulses whose duties of input pulse width are made small while providing a pulse generating circuit at the input part of a synchronous mirror delay circuit SMD. SOLUTION: A pulse generating circuit constituted of a delay circuit Pw, an inverter N1 and a NAND gate G1 is provided in this device. The delay time in an input part from an buffer B1 to an inverter N3 is made to be the same d1 as that of a buffer circuit B2 and the delay time of inverter circuits N4, N5 is made to be the same d2 as that of a buffer circuit B3 and also these delay times are set in accordance with the delay time of edges of pulses to be transmitted from a forward delay array FDA to a backward delay array BDA via a mirror control circuit MCC and, moreover, the delay time of output circuit inverters N6, N7 is also made to be d2. At this time, the period from an external clock CLKin till an internal clock CLKout just becomes the double period of that of the CLKin .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device which operates in synchronization with a clock signal, for example, a synchronous dynamic type R device.
The present invention relates to a technique effective for use in a clock input circuit of an AM (random access memory).

[0002]

2. Description of the Related Art A synchronous mirror delay circuit (SMD) is a circuit for synchronizing an external clock and an internal clock. Such a synchronous mirror delay circuit is described in ISSCC DIGIST OF TECHNICAL PAPERS, February 1996.
On March 10, there are pages 374 to 375.

[0003]

FIG. 11 is a circuit diagram of a synchronous mirror delay circuit previously studied by the present inventors, and FIG. 12 is a waveform chart for explaining the operation. The figure is shown. In this circuit, it is assumed that the rising of the internal clock CLKout and the rising of the external clock CLKin are synchronized. The external clock CLKin is input to a forward delay array circuit (hereinafter, referred to as FDA) through three delay circuits having delay times d1, d2, and d1, respectively. The rising edge of the n-th clock propagating in the FDA is common (hereinafter referred to as COMMON).
The propagation in the FDA is stopped by the rising edge of the clock of the (n + 1) th cycle, and the backward delay array (hereinafter referred to as BDA) at the position exactly symmetrical to the position where the propagation is stopped at the same time. Rising edge is forwarded to the node.

The rising edge propagates through the BDA for exactly the same time as the propagation time tDA during the FDA, and is output as an internal clock CLKout through a delay circuit (corresponding to an internal clock driver) with a delay time d2. . Since the propagation of the rising edge of the n-th cycle in the FDA is stopped by the rising edge of COMMON in the (n + 1) -th cycle, the following equation (1) is established. Here, tCK is the clock CL
This is the Kin cycle time (one cycle). d2 + d1 + tDA = tCK (1)

The propagation time of the rising edge from the external clock CLKin to the internal clock CLKout is
When the calculation is performed along the propagation path as described above, the following equation (2) is established. That is, the period from the external clock CLKin to the internal clock CLKout is exactly equal to 2tCK, and the external clock CLKin and the internal clock CL
Kout is synchronized. d1 + d2 + d1 + tDA + tDA + d2 = 2 (d1 + d2 + tDA) = 2tCK (2)

Several conditions are required to realize the synchronous operation. First, d1 for the clock cycle
If + d2 is too small, the input signal FDAin of the FDA also becomes high level (H) by the clock of the nth cycle during the period when COMMON is high level (H) by the clock of the nth cycle, and the mirror control circuit (hereinafter, referred to as “mirror control circuit”). MMC
FDA by the NAND gate
The propagation of the rising edge of the clock within is stopped. In this case, the above equation (1) does not hold.

Therefore, after COMMON goes low (L) by the clock of the n-th cycle, the FDAin needs to go high (H) by the clock of the n-th cycle. If this condition is shown on the operation waveform diagram of FIG. 12, the condition is that the period τ1 indicated by shading must be positive. This is represented by equation (3). However, it is assumed that the external clock CLKin has a pulse width duty of 50%. Also, tD is the above FDA
And a delay time of a basic delay unit (a signal path including one 2-input NAND gate circuit and one inverter circuit) constituting the BDA. tCK <2 (d1 + d2 + tD) (3)

Further, the rising edge of the clock in the n-th cycle is F until the common (COMMON) becomes high level (H) by the clock in the (n + 1) -th cycle.
Must be in DA. That is, n +
Until COMMON becomes high level (H) by the clock of the first cycle, the clock of the nth cycle is FDA
Do not pass through. This condition is expressed by the following equation (4). Here, n is the number of repetitions of the basic delay unit. The lower limit of the synchronizable clock frequency is determined by the two conditions represented by the above equations (3) and (4). tCK <ntD + d1 + d2 (4)

Conversely, d1 + d with respect to the clock cycle
If 2 is too large, tDA becomes short, and when the FDAin is still at the high level (H) by the nth cycle clock, the rising edge of the nth cycle clock transferred from FDA to BDA is the BDA output. The input to the NAND gate circuit b before the two basic delay units. At this time, since COMMON is still at the high level (H) by the clock of the (n + 1) th cycle, the NAND gate circuit b is inactive by the MCC, and the propagation of the rising edge of the clock of the nth cycle transferred from the FDA to the BDA is performed. I will stop. In this case as well, the above equation (1) does not hold, so that FDA
After in becomes low level (L) and the NAND gate circuit b is activated, the rising edge of the clock in the nth cycle transferred from FDA to BDA is the BDA output 2
In order to reach the NAND gate circuit b corresponding to one basic delay unit before, tDA must be lengthened to some extent. When this condition is shown on the operation waveform in FIG. 12, the condition is that the period τ2 indicated by shading must be positive. This can be expressed by the following equation (5). However, the pulse width duty of the clock CLKin is 50
%. Under these conditions, the upper limit of the clock frequency that can be synchronized is determined. tCK = 4/3 (d1 + d2 + tD) (5)

From the above three conditional expressions (3), (4) and (5), the result of calculating the delay time d2 dependence of the synchronizable clock frequency using a 0.3 μm process and a power supply voltage of 3.3 V as an example. Is shown in FIG. Where F
The number of repetitions n of DA and BDA was assumed to be 50. In the figure, a shaded area is a frequency band of a clock that can be synchronized. In an actual circuit, since d2 is fixed, the actual synchronizable clock frequency band is
The larger the cut in the vertical axis direction of the shaded area, the wider the area. From the figure, it can be seen that the clock frequency band that can be synchronized is limited to a very narrow range. The maximum value of the clock cycle that can be synchronized is 1.5 times or less of the minimum value, and it is difficult to limit the clock frequency to this band, including process variations of elements and fluctuations in power supply voltage.

Further, it has been found that there is a delay component which is ignored in the calculation of the above equation (2). It is FDA
Is the delay time δ required to transfer the rising edge of the clock from the clock to the BDA. That is, as shown in FIG. 13, it is assumed that COMMON is at the low level (L), the rising edge of the clock propagates through the FDA, and reaches just before the input of the basic delay unit at the right end in FIG.
The signal level of the main node in this case is shown in the figure as H or L.

When COMMON goes high (H) in the above state, first, the NAND gate circuit (a) of the MCC
After the low level (L) is output to the BDA, the low level (L) output by the NAND gate circuit (b) two stages before is output by the NAND gate circuit (a) to the NAND gate circuit (c) and the inverter circuit (d) of the FDA. And the output of the NAND gate circuit (a) is inverted from low level (L) to high level. The L → H inversion of the output of the last NAND gate circuit (a) is changed from FDA to B
This is the rising edge of the clock transferred to DA. Therefore, the transfer is performed via the four gates of the NAND gate circuit (b) → (c) → the inverter circuit (d) → the NAND gate circuit (a), and the resolution of the FDA [the basic delay unit (c, d Delay time), which appears as a synchronization error.

An object of the present invention is to provide a semiconductor integrated circuit device provided with a synchronous mirror delay circuit in which a synchronizable clock frequency band is expanded. Another object of the present invention is to provide a semiconductor integrated circuit device provided with a synchronous mirror delay circuit in which a synchronizable clock frequency band is expanded and the synchronization accuracy is improved. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, an input stage circuit that receives a clock input from an external terminal with a delay, and an AND gate circuit that constitutes a basic delay unit that receives a pulse signal passed through the input stage circuit and sequentially propagates an output signal thereof Receiving the pulse passed through the input stage circuit and the output signal of each AND gate circuit, and transmitting the output as a gate control signal of a predetermined AND gate of the forward delay array. A mirror control circuit, and a logical product gate forming a basic delay unit supplied with a corresponding output signal from the mirror control circuit and propagating a pulse edge passing through the mirror control circuit in a direction opposite to the forward delay array Synchronous pulse including a backward delay array comprising a circuit and a driver for outputting the same In generating circuit, providing a pulse generating circuit for generating a pulse obtained by reducing the pulse width duty cycle of the input pulse to the input stage circuit.

[0015]

FIG. 1 shows a synchronous mirror delay circuit (synchronous pulse generation circuit) according to the present invention.
The circuit diagram of one embodiment is shown. Each circuit in the figure is
Although not particularly limited, it is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique together with other circuits constituting the synchronous DAM.

As described above, the synchronous mirror delay circuit of this embodiment comprises an input section for receiving an external clock, an FDA, MCC and BDA, a load circuit, and an output section as a driver for the internal clock. In this embodiment, a pulse signal generating circuit is provided in an input buffer of the external clock CLKin in the input unit, and a clock CL
A pulse signal having a constant pulse width independent of the frequency of the clock CLKin from the rising edge or falling edge of Kin is generated.

That is, the external clock CLKin input from the external terminal is supplied to the pulse generation circuit via the input buffer B1. The pulse generation circuit includes a delay circuit Pw for delaying an output signal of the input buffer B1 and setting a pulse width, an inverter circuit N1, and the input buffer B
1 and a NAND gate circuit G1 receiving the delay signal of the inverter circuit N1. The output signal of the NAND gate circuit G1 is transmitted to COMMON through inverter circuits N2 and N3.

The output signal of the pulse generation circuit passing through the inverter circuits N2 and N3 is, on the other hand, output from the inverter circuits N4 and N5 and the buffer circuit B2 constituting a delay circuit.
And B3 to the FDA. The FDA includes a basic delay unit including a NAND gate circuit and an inverter circuit. The NAND gate circuits G11 and G21 of the first stage circuit and the second stage circuit of the FDA have a logic 1
Are constantly supplied. An output signal is formed from the inverter circuit N11 of the first-stage circuit, and one of the output signals is supplied to the other input of the second-stage NAND gate circuit G21. An output signal from the inverter circuit N11 is supplied to one input of a NAND gate circuit G12 of the MCC on the other side. The input of the NAND gate circuit G12 is connected to COMMON.

One input of the NAND gate circuit constituting the third-stage basic delay unit of the FDA is connected to the NAND gate circuit G12 of the MCC corresponding to the first-stage circuit which is two stages before.
Are supplied. Similarly, one input of a NAND gate circuit constituting a basic delay unit of the fourth and subsequent stages is connected to the same NAND gate of the MCC provided corresponding to the output signal of the basic delay unit of the two preceding FDA. The output signals of the circuits are supplied sequentially. Although not particularly limited, the FDA is configured by connecting the basic delay units as described above in a 50-stage cascade. Each of the signal propagation delay times in the one basic delay unit is similarly formed like tD.

The MCC is composed of NAND gate circuits that receive an output signal of the basic delay unit of each stage of the FDA and COMMON. Each of the NAND gate circuits G12, G22, etc. forming the MCC is supplied to one input of the NAND gate circuits G13, G23, etc. forming the BDA. The NAND gate circuits G13 and G23 propagate signals in a direction opposite to that of the FDA. That is, the output signal of the NAND gate circuit G23 is transmitted to the other input of the NAND gate circuit G13 via the inverter circuit N22. In order to make the basic delay unit of the BDA equivalent to the basic delay unit of the FDA, a load is provided as a dummy circuit. That is, the output signal of the inverter circuit N22 is supplied to the NAND gate circuit G24 as a dummy circuit corresponding to MCC. This NAND gate circuit G24
The other input is commonly connected to the similar input of another similar NAND gate circuit G14 and the like, and although not shown in the figure, a high level or a low level is fixedly supplied.

BDA has a signal propagation direction as described above.
The direction is opposite to that of the FDA, and is substantially the same as that of the FDA. Therefore, the edges of the clock transmitted through the FDA are transmitted by the BDA in the opposite direction with the same signal delay time. The BDA output signal BDAou
t is an inverter circuit N as an internal clock driver.
6 and N7 to form an internal clock CLKout.

In this embodiment, the delay time d1 at the input section is the signal propagation delay time at the input buffer B1, clock generation circuit, inverter circuits N2 and N3, and buffer circuit B2. The delay time d2 is a signal propagation delay time in the inverter circuits N4 and N5. Then, the buffer circuit B3 converts the FDA to M
The delay time corresponding to the delay time δ of the pulse edge transmitted to the BDA through the CC is set. Thereby, S
The synchronization accuracy of the MD can be improved. The signal propagation delay time in the inverter circuits N6 and N7 as the internal clock driver is set to the delay time d2 corresponding to the inverter circuits N4 and N5.

FIG. 2 shows a synchronous circuit according to the present invention.
An operation waveform diagram for explaining a mirror delay circuit is shown. Also in this embodiment, similarly to the above, the rising edge of the clock propagates through the BDA for exactly the same time as the propagation time tDA during the FDA, and passes through a delay circuit (corresponding to an internal clock driver) with a delay time d2. It is output as the internal clock CLKout. The rising edge of the n-th cycle in the FDA is n + 1
Since the propagation is stopped by the rising edge of COMMON in the cycle, the following equation (6) holds. d2 + d1 + δ + tDA = tCK (6)

The propagation time of the rising edge from the external clock CLKin to the internal clock CLKout is
When the calculation is performed along the propagation path as described above, the following equation (7) is established. That is, the period from the external clock CLKin to the internal clock CLKout is exactly equal to 2tCK, and the external clock CLKin and the internal clock CL
Kout is synchronized. d1 + d2 + d1 + δ + tDA + δ + tDA + d2 = 2 (d1 + d2 + δ + tDA) = 2tCK (7)

Looking at the synchronization conditions, it can be seen that τ1 and τ2 are longer than those in FIG. 12, and the upper limit is moderate. The condition corresponding to the above equation (3) is given by the following equation (8). Here, Pw is a pulse width of a pulse formed by the pulse generation circuit. It can be seen that tCK is not included in this equation, which is no longer the condition for the external clock frequency. Pw <d1 + d2 + δ + tDA (8)

The condition on the long-period side in this embodiment is a conditional expression for preventing a pulse from passing through the FDA as shown in the following expression (9). tCK <ntD + d1 + d2 + δ (9) Here, as a result of the elimination of the restriction by the condition corresponding to the equation (3), the longest cycle can be extended by increasing the number of repetitions n of the basic delay unit. The condition on the short cycle side is not different from the above case, but the form of the equation is slightly changed and becomes as shown in equation (10). tCK> d1 + d2 + tD + (Pw + δ) / 2 (10)

FIG. 3 shows the result of calculating the d2 dependency of the synchronizable clock frequency for the same example as described above under the above two conditions. As can be seen from FIG. 14, the frequency band is widened.

FIG. 4 shows a synchronous system according to the present invention.
A circuit diagram of another embodiment of the mirror delay circuit is shown. In this embodiment, the pulse generated by the pulse generation circuit is transmitted to COMMON. That is, MCC
It is intended to be conveyed only to the side. However, in order to make the delay time equal to the external clock CLKin input to the FDA, a NAND gate circuit or an inverter circuit corresponding to the pulse generation circuit is provided in the input section, and the same delay time d1 is set.

The synchronization condition of this embodiment is the same as that of the above embodiment on the long cycle side, and is given by equation (9).
On the short cycle side, another condition is added to the conditions of the above-described embodiment. This is a condition necessary for the pulse width duty of COMMON to be smaller than the pulse width duty of FDAin. In the operation waveform diagram shown in FIG. 5, τ3> 0, that is, given as the following equation (11). tCK> 2 (d1 + d2 + δ−Pw) (11)

It is assumed that the pulse width duty of the external clock CLKin is 50% as described above. τ
When 3 <0, when FDAin is still at the high level (H) in the nth cycle, COMMON goes to the low level (L) in the (n + 1) th cycle, so that the high level (H) starts to propagate through the FDA. . Then, FDAin temporarily goes low (L) and goes high again (H) in the next clock cycle (n + 1).
Since OMMON remains at the low level (L) of the (n + 1) th cycle, two rising edges propagate during FDA, and the external clock CLKin and the internal clock CLKout are not synchronized. )Is required.

FIG. 6 shows the result of calculating the d2 dependency of the clock frequency that can be synchronized in the same example as described above. Also in this embodiment, it can be seen that a sufficiently wide frequency band is secured as compared with FIG. In this embodiment, when the condition of the following equation (12) is satisfied, the external clock CLKin having the pulse width duty of 50% is
Similarly, an internal clock CL having a pulse width duty ratio of 50%
Another feature is that Kout can be formed. tCK> 2 (d1 + d2 + δ) (12)

FIG. 7 is a block diagram showing a main part of an embodiment of a dynamic RAM (synchronous DRAM) to which the present invention is applied. FIG. 1 exemplarily shows an input / output buffer and an internal circuit related to the input / output buffer in the synchronous DRAM.

A clock input buffer (Clock Input)
Buffer) 1 is a chip select signal / CS and a row address strobe signal / RA in addition to the external clock CLK.
In response to control signals such as S, column address strobe signal / CAS and write enable signal / WE, various control signals necessary for internal operation are formed. External clock C
LK is input to a synchronous clock generation circuit composed of a synchronous mirror delay circuit as shown in FIG. 1 or FIG. 4, where an internal clock synchronized with the external clock CLK is formed.

That is, the external clock CLK is input to the above-described synchronous clock generating circuit, where an internal clock synchronized with the external clock is formed. In this configuration, as compared with using the external clock CLK as the internal clock as it is, the signal delay in the input buffer can be substantially eliminated, and the time margin can be increased. Be prepared to respond.

Address input buffer (Address Input)
Buffer 2 captures address signals input in time series as described later. This address input buffer 2
Thus, in addition to the row address signal and the column address signal, code information Code used for mode setting is also taken in. This code information Code is set in a mode register included in a mode decoder (Mode Decoder) 5 and is decoded by the mode decoder 5 to form a control signal for realizing an operation corresponding thereto.

Data input buffer (Data Input Buf)
fer) 3 captures a write signal supplied from the input / output terminal I / O, and outputs a memory array (Memory Arra) (not shown).
y) is transmitted as write data Data. The data output buffer (Data Output Buffer) 4 stores the read data D read from the memory array (Memory array).
Ata is sent from the external terminal I / O.

Las system control circuit (RAS system Contr
ol) 6 is a row address counter (Row address counter) 7 and a row address predecoder (Row address pre-Decod) 7 based on the output of the mode decoder 5.
er) 10 to control the row-related address selection operation. A row address signal (Row Address) is input to the row address counter 7 as an initial value.
The row address predecoder 10 decodes the address signal and sends out the predecoded address signal (Row Address') to banks 0 and 1 (Bank-0 and Bank-1).

Bank control circuit (Bank Control)
l) Reference numeral 9 denotes a column-based address counter (Column-based address dress) based on an output signal from the mode decoder 5.
er) 8 and a column address predecoder (Column A)
ddress pre-Decoder) 12 to control row-related address selection operations. Column address counter 8
, A column address signal (Column Address) is input as an initial value. This column address counter 8
Is also called a burst counter (Burst Counter). The column address predecoder 12 decodes the address signal and sends the predecoded address signal (Column Address') to a memory array.

The row address predecoder 10 is provided with a redundancy circuit (Redundancy) 11, and a defective word line is replaced with a redundant word line. Similarly, a redundant circuit (Redundancy) is provided in the column address predecoder 12.
13, a defective data line is replaced with a redundant data line.

FIG. 8 shows an overall block diagram of an embodiment of the synchronous DRAM (hereinafter simply referred to as SDRAM). Although not particularly limited, the SDRAM shown in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. In the figure, in order to facilitate understanding of the entire circuit of the synchronous DRAM, even the same circuit blocks as those in FIG. 7 are represented by different circuit symbols in order to unify the whole circuit.

The SDRAM of this embodiment includes a memory array 200A forming a memory bank A (BANKA),
Memory array 2 forming memory bank (BANKB)
00B. Each of the memory arrays 200A and 200A
00B includes dynamic memory cells arranged in a matrix. According to the drawing, select terminals of memory cells arranged in the same column are coupled to a word line (not shown) for each column.
The data input / output terminals of the memory cells arranged in the same row are connected to complementary data lines (not shown) for each row.

One word line (not shown) of the memory array 200A is driven to a selected level in accordance with the result of decoding a row address signal by the row decoder 201A. Complementary data lines (not shown) of memory array 200A are coupled to sense amplifier and column selection circuit 202A. The sense amplifier in the sense amplifier and column selection circuit 202A is an amplifier circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from a memory cell. The column switch circuit in this case is a switch circuit for selecting complementary data lines individually and conducting to the complementary common data line 204. The column switch circuit is selectively operated according to the result of decoding the column address signal by the column decoder 203A.

Similarly, the row decoder 201B, the sense amplifier, and the column selection circuit 20 are provided on the memory array 200B side.
2B and a column decoder 203B are provided. The complementary common data line 204 is connected to the output terminal of the input buffer 210 and the input terminal of the output buffer 211. The input terminal of the input buffer 210 and the output terminal of the output buffer 211 are 16-bit data input / output terminals I / O0 to I / O.
15 is connected.

The row address signal and the column address signal supplied from the address input terminals A0 to A9 are taken into the column address buffer 205 and the row address buffer 206 in an address multiplex format. The supplied address signal is held in each buffer. The row address buffer 206 takes in the refresh address signal output from the refresh counter 208 as a row address signal in the refresh operation mode. The output of the column address buffer 205 is supplied as preset data of a column address counter 207. The column address counter 207 outputs a column address signal as the preset data or the column address thereof according to an operation mode specified by a command described later. The value obtained by sequentially incrementing the signal is output to the column decoders 203A and 203B.

The controller 212 includes, but is not limited to, a clock signal CLK and a clock enable signal CK.
E, a chip select signal / CS, a column address strobe signal / CAS (symbol / means that a signal attached thereto is a row enable signal), a row address strobe signal / RAS, a write enable signal / WE, etc. External control signals and address input terminals A0
A9 is supplied with the control data from A9, and forms an internal timing signal for controlling the operation mode of the SDRAM and the operation of the circuit block based on the level change and timing of those signals. Logic (not shown) and mode register 30 are provided.

The clock signal CLK is input to the synchronous clock generation circuit as described above, and is synchronized with the internal clock formed here. This internal clock is SD
The master clock of the RAM is used, and other external input signals are made significant in synchronization with the rising edge of the internal clock signal. The chip select signal / CS instructs the start of a command input cycle by its low level.
When the chip select signal / CS is at a high level (chip is not selected) and other inputs have no meaning. However,
Internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state. / RAS, / CAS and / WE signals are normal D
The function is different from that of the corresponding signal in the RAM, and is defined as a significant signal when defining a command cycle described later.

The clock enable signal CKE is a signal for indicating the validity of the next clock signal.
If E is at the high level, the next rising edge of the clock signal CLK is valid, and if it is at the low level, it is invalid. Further, although not shown, in the read mode, an external control signal for controlling output enable for the output buffer 211 is also supplied to the controller 212. When the signal is at a high level, for example, the output buffer 211 is set to a high output impedance state.

The row address signal is a clock signal C
It is defined by the levels of A0 to A8 in a later-described row address strobe / bank active command cycle synchronized with the rising edge of LK (internal clock signal).

The input from A9 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input of A9 is at a low level, the memory bank BANKA is selected, and when the input of A9 is at a high level, the memory bank BANKB is selected. The selection control of the memory bank is not particularly limited, but only the row decoder of the selected memory bank is activated, all the column switch circuits of the unselected memory bank are not selected, the input buffer 210 and the output buffer of the selected memory bank only. 2
11 and the like.

The input of A8 in a precharge command cycle described later indicates a mode of a precharge operation for a complementary data line or the like, and its high level indicates that the precharge target is both memory banks, and its low level. Indicates that one of the memory banks indicated by A9 is to be precharged.

The column address signal is defined by the levels of A0 to A7 in a read or write command (to be described later, column address / read command, column address / write command) cycle synchronized with the rising edge of the clock signal CLK (internal clock). Is done.
The column address defined in this way is used as a start address for burst access.

Next, the SDR specified by the command
The main operation mode of the AM will be described. (1) Mode register set command (Mo) This command is for setting the mode register 30. The command is specified by / CS, / RAS, / CAS, / WE = low level, and the data to be set (register set data ) Are given via A0-A9. Although the register set data is not particularly limited,
Burst length, CAS latency, write mode, and the like are set. Although not particularly limited, the settable burst length is 1, 2, 4, 8, and full page, the settable CAS latency is 1, 2, 3, and the settable write modes are burst write and Single light.

The above-mentioned CAS latency is determined by the output operation of the output buffer 21 from the fall of / CAS in a read operation specified by a column address read command described later.
This indicates how many cycles of the internal clock signal are to be consumed before the output operation of 1. Until the read data is determined, an internal operation time for data read is required, and this is set in accordance with the operating frequency of the internal clock signal. In other words, when using a high-frequency internal clock signal, set the CAS latency to a relatively large value, and when using a low-frequency internal clock signal, set the CAS latency to a relatively small value. I do.

(2) Row address strobe / bank active command (Ac) This is a command for validating a row address strobe instruction and selecting a memory bank by A9.
S, / RAS = low level, / CAS, / WE = high level. At this time, the address supplied to A0 to A8 is taken as a row address signal, and the signal supplied to A9 is taken as a memory bank selection signal. .
The fetch operation is performed in synchronization with the rising edge of the internal clock signal as described above. For example, when the command is specified, a word line in the memory bank specified by the command is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary data lines.

(3) Column Address Read Command (Re) This command is a command necessary for starting a burst read operation and a command for giving an instruction of a column address strobe, and / CS, / CAS =
Instructed by low level, / RAS, / WE = high level. At this time, column addresses supplied to A0 to A7 are taken in as column address signals. The fetched column address signal is supplied to the column address counter 207 as a burst start address. In the burst read operation designated thereby, the memory bank and the word line in the memory bank are selected in the row address strobe / bank active command cycle, and the memory cell of the selected word line is supplied with the internal clock signal. Are sequentially selected in accordance with the address signal output from the column address counter 207 and are successively read out. The number of data to be continuously read is the number specified by the burst length. The start of reading data from the output buffer 211 is performed after waiting for the number of cycles of the internal clock signal defined by the CAS latency.

(4) Column Address Write Command (Wr) When a burst write is set in the mode register 30 as a mode of the write operation, this is a command necessary to start the burst write operation, and is used as a command for the write operation. As a mode, when the single write is set in the mode register 30, the command is a command necessary to start the single write operation. Further, the command gives an instruction of a column address strobe in single write and burst write. The command is / C
S, / CAS, / WE = low level, / RAS = high level. At this time, the addresses supplied to A0 to A7 are captured as column address signals.
The column address signal thus captured is supplied to the column address counter 207 as a burst start address in burst write. The procedure of the burst write operation instructed in this way is performed in the same manner as the burst read operation. However, CAS operation is required for the write operation.
There is no latency, and the capture of write data is started from the column address / write command cycle.

(5) Precharge command (Pr) This is a command to start a precharge operation for the memory bank selected by A8 and A9, and / C
S, / RAS, / WE = low level, / CAS = high level.

(6) Auto-refresh command This command is a command required to start auto-refresh, and includes / CS, / RAS, / CA
Instructed by S = low level, / WE, CKE = high level.

(7) Burst stop in full page command This command is required to stop the burst operation for a full page for all memory banks, and is ignored in burst operations other than the full page. This command is for / CS, / WE = low level, / RAS, / CA
Indicated by S = high level.

(8) No operation command (No
p) This is a command instructing that no substantial operation is performed, / CS = low level, / RAS, / CAS, / W
It is indicated by the high level of E.

In the SDRAM, when a burst operation is being performed in one memory bank, another memory bank is designated in the middle of the burst operation and a row address strobe / bank active command is supplied. The row address operation in the other memory bank is enabled without affecting the operation in one memory bank. For example, the SDRAM has means for internally holding data, addresses, and control signals supplied from the outside, and the held contents, particularly addresses and control signals, are not particularly limited, but may be held for each memory bank. It has become. Alternatively, data for one word line in a memory block selected by a row address strobe / bank active command cycle is latched in advance by a latch circuit (not shown) for a read operation before a column operation. I have.

Therefore, data input / output terminals I / O0 to I / O0
Unless data collision occurs in the I / O 15, during execution of a command whose processing has not been completed, a precharge command and a row address strobe bank active command for a memory bank different from the memory bank to be processed by the command being executed. To start the internal operation in advance.

The SDRAM 22 receives the clock signal CLK
Since data, addresses, and control signals can be input and output in synchronization with the (internal clock signal), a large-capacity memory similar to a DRAM can operate at a high speed comparable to that of an SRAM. By specifying the number of data accesses to the word line by the burst length, the built-in column address counter 20 can be used.
It will be understood that a plurality of data can be read or written continuously by sequentially switching the selection state of the column system at 7.

FIG. 9 is a timing chart for explaining an example of the read cycle of the SDRAM according to the present invention. The row address R: a is fetched from the low levels of / CS and / RAS. Also, address A11
(Bank select BS) low level,
0 is activated, and a row-related address selecting operation is started for bank-0. After three clocks, / CA
S is set to low level, the column address C: a is fetched, and the column-related selecting operation is started.

Assuming that the CAS latency is 3, an output signal a is output after three clocks. If the burst read is designated, data a + 1, a + 2, and a + 3 are sequentially output in synchronization with the clock. In parallel with such a read operation, the active bank
The designation of 1, the corresponding row address R: b, and the column address C: b are input three clocks later. Thus, after three clocks, data b, b + 1,
b + 2 and b + 3 are sequentially read.

When the column address C: b 'is inputted by designating the read bank-1, the data b' and b '+ 1 are subsequently output three clocks later. Two clocks later, when the column address C: b "is input by designating the readback -1 and b 'is replaced by b", the data b "and b" +1,
b ″ +2 and b ″ +3 are output.

FIG. 10 is a timing chart for explaining an example of a write cycle of the SDRAM according to the present invention. The row address R: a is fetched from the low levels of / CS and / RAS. Also, address A1
The low level of 1 (bank select BS) activates bank-0, and starts row-related address selection operation for bank-0. After three clocks, / C
AS is set to the low level, the column address C: a is taken in, the column-based selection operation is started, and at the same time, the input write signal a is written to the selected memory cell. The column address is updated, and data a + 1, a + 2, and a + 3 are written in synchronization with the clock.

In parallel with such a burst write operation, the designation of the active bank-1, the corresponding row address R: b, and the column address C: b delayed by three clocks are input, and the write data b is Written. Hereinafter, b + 1, b + 2, and b + 3 are sequentially written in synchronization with the clock in the same manner as described above. Hereinafter, the column address C: b ′ is inputted by designating the write bank-1.
When write data b ′ and b ′ + 1 are input, readback −1 is specified, and a column address C: b ″ is input,
Since the column address is changed from b 'to b ",
The corresponding data b "and b" +1, b "+2,
b ″ +3 are sequentially written.

The operation and effect obtained from the above embodiment are as follows. (1) An input stage circuit that delays and takes in a clock input from an external terminal, and an AND gate circuit that constitutes a basic delay unit that receives a pulse signal passed through the input stage circuit and sequentially propagates an output signal thereof And a pulse passed through the input stage circuit and an output signal of each AND gate circuit, and the output is used as a gate control signal for a predetermined AND gate of the forward delay array. A mirror control circuit for transmitting a signal, and a logical product constituting a basic delay unit that receives a corresponding output signal from the mirror control circuit and propagates a pulse edge passing through the mirror control circuit in a direction opposite to the forward delay array. Synchronization pulse generation including a backward delay array comprising a gate circuit and a driver for outputting the same In the raw circuit, by providing the input stage circuit with a pulse generation circuit that generates a pulse with a reduced pulse width duty of the input pulse, an effect that the frequency band of the external clock that can be synchronized can be widened is obtained. .

(2) Logic constituting an input stage circuit which delays and takes in a clock input from an external terminal and a basic delay unit which receives a pulse signal passed through the input stage circuit and sequentially propagates the output signal. A forward delay array comprising a product gate circuit; a pulse passing through the input stage circuit and an output signal of each logical product gate circuit; receiving the output thereof as a gate of a predetermined logical product gate of the forward delay array; A mirror control circuit for transmitting a control signal and a corresponding output signal supplied from the mirror control circuit, and a basic delay unit for transmitting a pulse edge passing through the mirror control circuit in a direction opposite to the forward delay array. Delay array comprising a logical AND gate circuit and a driver for outputting the same In the synchronous pulse generating circuit, by providing a pulse generating circuit and reducing the pulse width duty of the input pulse to the mirror control circuit as compared with the external clock, the frequency band of the external clock that can be synchronized can be widened. Is obtained.

(3) The input circuit or the first and second input stage circuits correspond to a delay time during which a pulse edge is transmitted from the forward delay array to the backward delay array through the mirror control circuit. By inserting a delay circuit having a delay time, there is an effect that the synchronization accuracy can be increased.

(4) By mounting the synchronous pulse generation circuit in a synchronous dynamic RAM, the effect that the operation speed can be further increased can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the synchronization between the input pulse and the internal pulse may be such that the falling edge of the pulse is synchronized. The basic delay unit may be any unit that substantially performs a logical product operation. INDUSTRIAL APPLICABILITY The synchronous pulse generating circuit according to the present invention can be widely used in various types of semiconductor integrated circuit devices requiring an internal clock signal synchronized with a clock signal input from the outside, in addition to a synchronous DRAM.

[0074]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, an input stage circuit that receives a clock input from an external terminal with a delay, and an AND gate circuit that constitutes a basic delay unit that receives a pulse signal passed through the input stage circuit and sequentially propagates an output signal thereof Receiving the pulse passed through the input stage circuit and the output signal of each AND gate circuit, and transmitting the output as a gate control signal of a predetermined AND gate of the forward delay array. A mirror control circuit, and a logical product gate forming a basic delay unit supplied with a corresponding output signal from the mirror control circuit and propagating a pulse edge passing through the mirror control circuit in a direction opposite to the forward delay array Synchronous pulse including a backward delay array comprising a circuit and a driver for outputting the same In generating circuit, by providing a pulse generating circuit for generating a pulse obtained by reducing the pulse width duty cycle of the input pulse to the input stage circuit, it is possible to widen the frequency band of synchronizable external clock.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a synchronous mirror delay circuit (synchronous pulse generation circuit) according to the present invention.

FIG. 2 is an operation waveform diagram for explaining the synchronous mirror delay circuit of FIG. 1;

FIG. 3 is a characteristic diagram showing an external clock frequency band that can be synchronized with the circuit of FIG. 1;

FIG. 4 is a circuit diagram showing another embodiment of the synchronous mirror delay circuit according to the present invention.

FIG. 5 is an operation waveform diagram for explaining the synchronous mirror delay circuit of FIG. 4;

FIG. 6 is a characteristic diagram showing an external clock frequency band that can be synchronized with the circuit of FIG. 4;

FIG. 7 is a main part block diagram showing an embodiment of a synchronous dynamic RAM to which the present invention is applied;

8 is an overall block diagram showing one embodiment of the synchronous DRAM of FIG. 7;

FIG. 9 is a timing chart for explaining an example of a read cycle of the synchronous DRAM according to the present invention.

FIG. 10 is a timing chart for explaining an example of a write cycle of the synchronous DRAM according to the present invention.

FIG. 11 is a circuit diagram of a synchronous mirror delay circuit studied prior to the present invention.

FIG. 12 is an operation waveform diagram for explaining the operation of the circuit in FIG. 11;

FIG. 13 is a partial circuit diagram of a synchronous mirror delay circuit studied prior to the present invention.

FIG. 14 is a characteristic diagram showing an external clock frequency band that can be synchronized with the circuit of FIG. 11;

[Explanation of symbols]

B1 to B3 buffer circuits, N1 to N6, N11 to N2
2: inverter circuit, G1, G11 to G24: NAND gate circuit, FDA: forward delay array, M
CC: mirror control circuit, BDA: backward delay array, 1: clock input buffer, 2 ... address input buffer, 3 ... data input buffer, 4 ... data output buffer, 5 ... mode decoder, 6 ... lath control circuit, 7 ... row address counter, 8 ... column address counter, 9 ... bank control circuit, 10 ...
Row address predecoder, 11... Row redundancy circuit,
12 column address predecoder, 13 column redundancy circuit, 22 SDRAM, 30 mode register,
200A, 200B ... memory array, 201A, 201
B: row decoder, 202A, 202B: sense amplifier and column selection circuit, 203A, 203B: column decoder, 205: column address buffer, 206: row address buffer, 207: column address counter,
208: refresh counter, 210: input buffer, 211: output buffer, 212: controller.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI G11C 11/34 362S

Claims (6)

[Claims] An input stage circuit including a pulse generation circuit for delaying a clock input from an external terminal and forming a pulse having a pulse width with a reduced pulse width duty with respect to the external clock; A forward delay array comprising AND gate circuits constituting a basic delay unit for receiving the passed pulse signal and sequentially transmitting an output signal thereof; a pulse passing through the input stage circuit and an output of each AND gate circuit A mirror control circuit that receives the signal and transmits the output as a gate control signal of a predetermined AND gate of the forward delay array; and a corresponding output signal is supplied from the mirror control circuit.
A synchronous pulse generating circuit including a backward delay array comprising an AND gate circuit constituting a basic delay unit for propagating a pulse edge having passed through the mirror control circuit in a direction opposite to the forward delay array. A semiconductor integrated circuit device comprising: 2. An input stage circuit comprising: a first delay circuit, a second delay circuit, and a second delay circuit for delaying a signal by a first delay time.
And a third delay circuit for delaying the signal by a delay time of (d), wherein the output signal of the backward delay array is output through a clock driver having the second delay time. The semiconductor integrated circuit device according to claim 1. 3. A first input stage circuit including a pulse generation circuit for delaying a clock input from an external terminal and forming a pulse having a pulse width with a reduced pulse width duty with respect to the external clock; A second input stage circuit having the same delay time as the delay time of the first input stage circuit, and a basic circuit for receiving a pulse signal passed through the second input stage circuit and sequentially transmitting an output signal thereof A forward delay array comprising a logical product gate circuit constituting a delay unit; a pulse which has passed through the first input stage circuit and an output signal of each logical product gate circuit;
A mirror control circuit for transmitting as a gate control signal of a predetermined AND gate of the delay array, and a corresponding output signal supplied from the mirror control circuit;
A synchronous pulse generating circuit including a backward delay array comprising an AND gate circuit constituting a basic delay unit for propagating a pulse edge having passed through the mirror control circuit in a direction opposite to the forward delay array. A semiconductor integrated circuit device comprising: 4. A first delay circuit and a second delay circuit for performing a signal delay of a first delay time, and a signal delay of a second delay time, respectively, in the first and second input stage circuits. 4. The semiconductor integrated circuit according to claim 3, further comprising a third delay circuit for performing the operation, wherein the output signal of the backward delay array is output through a clock driver having the second delay time. apparatus. 5. A delay circuit having a delay time corresponding to a delay time for transmitting a pulse edge from a forward delay array to a backward delay array through a mirror control circuit is inserted into the input stage circuit. 4. The semiconductor integrated circuit device according to claim 1, wherein: 6. The semiconductor integrated circuit device comprises a synchronous dynamic RAM, and the synchronous clock generation circuit is used for a clock input circuit thereof. Claim 3
Semiconductor integrated circuit device.