JPH10260911A - Semiconductor device and information processing system containing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain a stable opeartion for a long time by providing a state monitoring part which monitors operation environments such as the state of a semiconductor, the power supply voltage of the semiconductor, power supply current and ambient temperature and an information notifying part which externally notifies the supervisory result to an inside of a semiconductor device. SOLUTION: A CPU 2 sets threshold to a power supply voltage monitoring part 25 with a threshold setting signal 202. The part 25 transmits a monitor result of a memory power supply 21 as a power supply monitor result signal 201 to a memory information notifying part 26. The state of a DRAM 20 is notified by a memory information signal 203 from the part 26 to a system. The signal 203 is inputted to the CPU 2 and a battery changeover switch 22 and controls other devices 28, the switch 22 switches a main battery 23 with a backup battery 24. An output A of the switch 22 is connected to a memory power supply 21 through a power supply line 206 to the source 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of providing stable operation and an information processing system incorporating the semiconductor device.

[0002]

2. Description of the Related Art At present, semiconductor devices are indispensable for realizing high performance, miniaturization, low cost, and high reliability of information equipment. Semiconductor devices are classified into various types according to their internal structures, but it is necessary to select an optimal memory according to the purpose of use of the device. In addition, the control method of the selected memory is determined within the range of the specification of the LSI such as the CPU other than the memory.

FIG. 1 is a block diagram of a memory control method in a conventional memory mounting system. 1 is ROM, 2
Denotes a CPU (arithmetic processing unit), 3 denotes a memory to be controlled, 4 denotes a setting information storage unit, 5 denotes a setting register, 6 denotes a memory control unit,
100 is a memory control setting information signal, 101 is a memory control information signal, and 102 is a memory control signal.

[0004] In order to optimally control the mounted memory, the designer determines various settings of the control method based on the characteristic values guaranteed by the memory product. This guaranteed characteristic value assumes a general operating environment as a general-purpose storage medium. The determined settings are stored in advance in the setting information storage unit 4 in the ROM 1. The setting contents are not changed in the system and are always read as the same setting value.

When the system starts up, the CPU 2
The setting information is read from the internal setting information storage unit 4 as a memory control setting information signal 100. The CPU 2 reflects the read setting information in the setting register 5 inside the CPU 2. The contents of the setting register 5 are notified to the memory control unit 6 by the control information signal 101. The memory control unit 6
The memory control corresponding to the contents of the setting register 5 is executed. Thus, the memory control method determined by the designer is reflected in the actual system.

[0006]

The present and future information devices are required to have higher performance and lower power consumption.
Therefore, in configuring a system, it is necessary to maximize the performance of semiconductor components.

[0007] However, semiconductors have variations in physical characteristics. Generally, a guaranteed characteristic value is set for a commercialized semiconductor component, and this is a value in which a margin is provided for the characteristic variation. Therefore, the conventional method cannot achieve the maximum optimization as a system.

In addition, variations in the operating environment such as the power supply voltage and the ambient temperature cause variations in the characteristics such as the operating speed and the data holding ability of individual semiconductor devices.

In particular, in information equipment that drives a system from a battery, the power supply voltage fluctuates as the battery is consumed. In general, when the power supply voltage decreases, for example, information in the memory may be lost. However, a threshold value of the power supply voltage for the information loss differs depending on each memory. It is clear that long-term operation of the device can be realized by combining a memory having a low threshold value of a power supply voltage for information loss and a control method corresponding to the memory.

[0010]

In order to achieve the above object, the present invention provides a state monitor for monitoring an operating environment such as a state of a semiconductor, a power supply voltage of a semiconductor, a power supply current, and an ambient temperature inside a semiconductor device. And an information notifying unit for notifying the monitoring result of the status monitoring unit to the outside.

The status monitor can compare the result of the comparison with a preset threshold value and output the result of the comparison as a monitor result.

The threshold value can be freely changed by an external instruction.

The state monitor monitors the power supply voltage and detects a malfunction of the semiconductor device. In detecting a malfunction of the semiconductor device, the power supply voltage can be changed, or the power supply voltage can be fluctuated in a pseudo manner. The power supply voltage is changed by, for example, lowering the power supply voltage by a predetermined value to reproduce a pseudo voltage drop and a battery exhaustion state, and detecting a malfunction to monitor and detect the voltage drop state in advance. Let it. As a result, the limit voltage at which a malfunction occurs is detected in advance, and the semiconductor device and the information processing system incorporating the same are stably operated and controlled up to the detected limit voltage.

By notifying the information from the information notifying unit to the information processing system incorporating the semiconductor device,
This semiconductor device is optimally controlled. The information processing system is optimally controlled according to the notification from the information notification unit.

The above-mentioned optimum control includes, for example, switching of a power supply source, provision of a stabilizing power supply in a semiconductor device to stabilize a supply voltage, stopping operation of unnecessary parts of this information processing system, Warning or warning to urge the user to turn off the battery or replace the battery.

When a memory is used as the semiconductor device, the malfunction detection is realized by detecting a data error in a memory cell in, for example, writing / reading data to / from the memory.

In addition, as a semiconductor device, Dynamic
When a RAM (DRAM) is used, a memory cell and a logic cell of the DRAM are mixedly mounted on the same chip, and the processing of the state monitoring unit and the information notification unit is executed in the logic cell.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. The present invention relates to a semiconductor device. Here, a semiconductor memory will be described as an embodiment.

FIG. 2 is a block diagram showing a first embodiment of a semiconductor memory mounting system according to the present invention suitable for achieving the first object of the present invention. In FIG. 2, reference numeral 20 denotes a dynamic RAM (DRAM);
Is a memory power supply, 22 is a battery changeover switch, 23 is a main battery, 24 is a backup battery, 28 is another device including a display device 29, 200 is a memory power supply line, 201 is a memory power monitoring result signal, 202 is CPU
A threshold setting signal of 2, a memory information signal 203, an output line of a main battery 204, an output line of a backup battery 205, a power supply line 206 to the memory power supply 21, and a control unit 207 from the CPU 2 for other devices 28 Control signal. The DRAM 20 has a memory cell 27
And a power supply voltage monitoring unit 25 and a memory information notifying unit 26. The DRAM 20 is accessed mainly by the CPU 2 and stores information in the memory cell 27. The description is made on the assumption that the stored information needs to be backed up because it is generally a DRAM.

First, the CPU 2 sets a threshold value in the power supply voltage monitoring unit 25 according to the threshold value setting signal 202. The power supply voltage monitoring unit 25 transmits the monitoring result of the memory power supply 21 to the memory information notification unit 26 as a memory power supply monitoring result signal 201. Then, the memory information notifying unit 26 notifies the system of the state of the DRAM 20 by the memory information signal 203. The memory information signal 203 is input to the CPU 2 and the battery changeover switch 22, and the CPU 2 controls other devices 28, and the battery changeover switch 22 switches between the main battery 23 and the backup battery 24. The output A of the battery switch 22 is connected to the memory power supply 21 through a power supply line 206 to the memory power supply 21.

The internal structure of each block will be described in detail.

A memory power 21 is supplied to the DRAM 20, and the DRAM 2 is connected through a main power line 200.
0 is input to the memory cell 27 and the power supply voltage monitoring unit 25 inside. In the power supply voltage monitoring unit 25, the memory power supply 2
1 is monitored, and the result is transferred to the memory information notification unit 26.

Here, the power supply voltage monitoring unit 25
This embodiment is a feature of the first embodiment, and will be described in detail below.

FIG. 3 is a block diagram showing a specific example of the configuration of the power supply voltage detector 25. 30 is a threshold voltage generator,
31 is a threshold voltage comparison unit, 32 is a threshold voltage, 300 and 3
01 is a threshold voltage line. When the threshold setting signal 202 is input to the threshold voltage generator 30 by the CPU 2, the threshold voltage generator 30 generates the threshold voltage 32 in a stable manner based on the setting information. Generally, the threshold voltage 32 can be stabilized using a down converter. Then, the threshold voltage 32 and the memory power supply line 200 are input to the threshold voltage comparison unit 31, and the magnitude comparison is performed.
The result of the magnitude comparison is output as a memory power monitoring result signal 201. That is, the memory power supply 21
When it becomes lower than the threshold voltage 32 set by PU2,
This is reflected in the memory power supply monitoring result signal 201.

FIG. 4 is a block diagram showing a specific example of the configuration of the memory information notifying section 26. As shown in FIG. 40 is a memory information storage unit, 41 is an internal register of the memory information storage unit 40,
Reference numeral 42 denotes a backup bit in the register 41. The memory information storage section 40 stores various kinds of information inside the DRAM 20. In the first embodiment, particularly,
Information about the internal power state of the RAM 20 is stored. First, the memory power supply monitoring result signal 201 is output from the power supply voltage detection unit 25 described above. The result is stored in register 41
Is reflected in the backup bit 42 of Memory power supply 2
When 1 is lower than the threshold voltage 32, the backup bit 42 becomes “1”. This indicates that the voltage of the memory power supply 21 of the DRAM 20 is lower than the normal state. Further, the contents of the backup bit 42 are notified to the outside of the DRAM 20 as a memory information signal 203. Therefore, the system recognizes that the power inside the memory has dropped, and can stop the normal operation of the DRAM 20 and determine to shift to “backup control” in which the information inside the DRAM 20 is kept. Specifically, when the backup bit 42 becomes “1”, the CPU 2 sends a control signal 207 to the device 28 other than the DRAM 20.
The operation of the system is stopped or the supply of power is stopped to save the power of the system. In addition, in order to warn the user that the voltage of the memory power supply 21 has dropped, the display device 29 is particularly controlled to display a message. FIG. 8 is a specific example of this user interface. In FIG. 8, 80
Is a display device, and 81 is a warning message. By this warning display, the user can recognize the time to replace the battery, and the operability of the information device can be improved.

The memory information signal 203 is connected to the battery switch 22. As shown in FIG. 2, the battery switch 22 includes a mechanism for switching between a main battery 23 and a backup battery 24. The main battery 23 is mainly used as a power supply source when the system normally operates, and the backup battery 24 is used as a memory backup power source when the system stops. Here, the memory information signal 203 is the same as the content of the backup bit 42 inside the DRAM 20. Therefore, when the memory information signal 203 is at the low level, the DRAM 20
Is in a normal operation state, and the battery switch 22 selects the main battery 23. Conversely, when the memory information signal 203 is Hi
In the case of the gh level, the DRAM 20 is in the backup state, and the battery switch 22 selects the backup battery 24. As described above, the system recognizes the internal state of the DRAM 20, selects the most suitable battery as the power supply source, and can extend the life of the information device.

As described above, in the first embodiment, by comparing the memory power supply 21 inside the DRAM 20 with the preset threshold voltage 32, the DRAM 2
The system can recognize the time when 0 is changed to the backup state. Therefore, the backup battery 24 can be used to the maximum extent, the other devices 28 not used under control of the CPU 2 can be stopped, and a warning message can be displayed on the display device 29 for the user. In addition, since the threshold voltage 32 is programmable, optimization according to the load of the system can be realized.

In the embodiment shown in FIG.
Although the RAM 20 and the CPU 2 are shown separately,
It is clear that the present invention is also effective for an LSI incorporating a RAM. In particular, in a DRAM-embedded LSI, it is possible to suppress a decrease in the DRAM power supply by incorporating a stabilized power supply into the chip.

Although a DRAM to be controlled is taken as an example of a memory to be controlled, the present invention is not limited to this. For example, a volatile memory whose internal information holding state varies according to a power supply voltage, a ferroelectric memory (FRAM) It can also be applied to

Further, the warning message shown in FIG. 8 is not limited to this, and a user interface using a lamp display such as an LED may be used. Further, a message relating to various states of the information device itself such as an operation error may be displayed. Can also be applied.

FIG. 5 is a block diagram showing a second embodiment of a semiconductor memory according to the present invention, which is suitable for achieving the second object of the present invention. In FIG. 5, reference numeral 50 denotes a memory error detection unit, 51 denotes a memory information notification unit, 501 denotes a memory error detection result signal, and 502 denotes a memory information signal.

The DRAM 20 has a memory error detector 5
0 and a memory information notification unit 51 are built in. The memory error detection unit 50 has a mechanism for detecting a bit error of a memory cell in the DRAM 20, and outputs a detection result to the memory information notification unit 51 as a memory error detection result signal 501. Then, the memory information notifying section 51 uses the memory error state inside the DRAM 2 as a memory information signal 502 as C
Notify PU2. The second embodiment is characterized in that a bit error in the DRAM 20 due to a change in the memory power is detected in advance.

Here, the memory error detection unit 50 determines that the second
This embodiment is a feature of the first embodiment, and will be described in detail below.

In the memory error detecting section 50, the DRAM 2
A mechanism for determining whether a read / write operation of a memory cell inside 0 is possible is provided so that the system can recognize whether or not the DRAM 20 can operate with a low power supply voltage.

FIG. 6 is a block diagram showing a specific example of the configuration of the memory error detection section 50. In FIG. 6, 60
Is a memory cell, 61 is a power supply voltage controller, 62 is a read / write (R / W) controller, 63 is an address counter, 64 is a cycle counter, 65 is an information comparator, 66
Is a write information storage unit, 600 is a memory power supply line controlled by the power supply voltage control unit 61, 601 is a memory access signal, 602 is a read information signal, 603 is a write information signal, 603 is a detection cycle control signal, and 605 is a detection address. This is a control signal.

In the second embodiment, the memory cell 60 is divided into a total of (N + 1) memory cells from 0 to N. The detection of a memory error for one memory cell will be described below.

First, an arbitrary address of a memory cell is determined by the address counter 63, and the detected address signal 6
05 is notified to the R / W control unit 605. Similarly,
The cycle counter 64 notifies the R / W control unit 605 of the detection cycle control signal 604 so as to perform the memory error detection at regular intervals. The R / W control unit 62 includes a write information storage unit 66 and outputs a memory access signal 601 to each of the memory cells 0 to N. Then, predetermined test information is written in the memory cell, and information at the same address is read again as a read information signal 602. Here, the read information signal 602 and the write information signal 603
Are compared by the information comparing unit 65. If the matching results do not match, the corresponding memory cell is determined to be a memory error, and the memory information notifying unit 51 is used as a memory error detection result signal 501.
Is transmitted to

Generally, it is considered that the aforementioned memory error hardly occurs in the voltage range of the memory power supply 21 in which the DRAM can normally operate. However, when the memory power supply 21 is at a low voltage, the operation inside the memory becomes unstable, so that the possibility of occurrence of a memory error increases. Obviously, it is very effective for the information equipment to be able to lower the voltage of the memory power supply 21 to the limit at which this memory error occurs. Therefore, the power supply voltage control unit 61
Is provided with a mechanism for reducing the voltage of the memory power supply 21 in advance when a memory error is detected.
The system can recognize whether or not the voltage value is close to the limit of the operable voltage of the DRAM 2. That is,
If no memory error occurs even when the memory power supply is forcibly reduced, it is considered that there is a margin up to the limit of the operable voltage of the DRAM 2.

FIG. 7 is a block diagram showing a specific example of the configuration of the memory information notifying section 51. 75 is a memory information storage unit, 70 is an internal register of the memory information storage unit 75,
71 to 74 are error bits in the register 70.
The memory information storage unit 75 stores various types of information inside the DRAM 20, and in the second embodiment, particularly stores information regarding the memory cell state of the DRAM 20. First, a memory error detection result signal 501 is output from the memory error detection unit 50 described above, and the result is reflected in the error bits 71 to 74 of the register 70. Since each error bit corresponds to a divided memory cell inside the DRAM 20, the memory information signal 50
2 that has received the error 2 can recognize in which area of the memory cell inside the DRAM 20 the error has occurred. Here, since the CPU 2 itself can grasp the internal state of the DRAM 20, similarly to the first embodiment, the operation of unnecessary peripheral devices and the supply of power are stopped, and a warning message is issued to the user. Can be displayed.

As described above, in the second embodiment, the error detection of the memory cell is performed in a state where the voltage value of the memory power supply 21 is lowered in advance, and the detection result is notified to the system. The system can recognize the limit value of the power supply voltage that can actually operate. That is, DR
Until the AM20 limit is reached, the system will run on memory power 2
1 can be kept low, and a longer life and higher reliability of the information equipment can be realized. Note that, in the second embodiment, not only information devices but also DR
The present invention can also be applied to other types of RAM-mounted systems such as an LSI with embedded AM and a ferroelectric memory (FRAM).

In the embodiment shown in FIG. 6, the description has been made assuming that the power supply voltage control section 61 lowers the voltage of the memory power supply 21 in advance, but the control method of the memory power supply 21 according to the present invention is as follows. It is not limited. For example, adding random noise to the memory power line,
By periodically fluctuating the power supply voltage, it is possible to more accurately approach the limit value of the memory power supply voltage.

Here, in the first and second embodiments of the present invention, the voltage of the memory power supply 21 is mainly monitored. However, the power supply can be monitored also by detecting the current value of the memory power supply 21. Can be.

[0043]

According to the present invention, it is possible to provide a semiconductor device capable of maintaining stable operation for a long time and an information processing system incorporating the semiconductor device.

Further, for example, data protection can be performed more reliably, the battery can be replaced at the optimal time, and the operability of the information processing system is improved.

That is, according to the present invention, a state monitor for monitoring an operating environment such as a state of a semiconductor, a power supply voltage of a semiconductor, a power supply current, an ambient temperature, and the like, and a monitoring result of the state monitor are externally provided in the semiconductor device. Is provided, the state monitoring unit can detect a drop in the power supply voltage, etc., and is notified to the outside via the information notifying unit. As a result, the information processing system incorporating the semiconductor device can stabilize the supply voltage by, for example, switching the power supply source or providing a stabilized power supply inside the semiconductor device. Can stabilize the operation of the information processing system in which is incorporated. Or
Since a message warning of a drop in power supply voltage can be displayed, it is possible to prompt the user to replace the battery.

Further, since the state monitoring unit can detect not only the operation environment but also the malfunction of the semiconductor device itself, the state of the semiconductor device can be monitored in more detail.
In the detection of the malfunction of the semiconductor itself, the limit voltage at which the malfunction occurs can be detected in advance by lowering the power supply voltage and simulating the battery consumption state to detect the malfunction. As a result, there is an advantage that the semiconductor device and the information processing system incorporating the same can operate stably up to the detected limit voltage.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a conventional memory control method.

FIG. 2 is a block diagram for explaining a first embodiment of the present invention.

FIG. 3 is a block diagram for explaining a specific example of a power supply voltage monitoring unit;

FIG. 4 is a block diagram for explaining a first specific example of a memory information notification unit;

FIG. 5 is a block diagram for explaining a second embodiment of the present invention.

FIG. 6 is a block diagram for explaining a specific example of a memory error detection unit;

FIG. 7 is a block diagram for explaining a second specific example of the memory information notification unit;

FIG. 8 is a view for explaining a specific example of a method for displaying a warning message of battery replacement.

[Explanation of symbols]

2 CPU, 20 DRAM, 21 memory power supply, 22
... Battery changeover switch 23 ... Main battery, 24 ... Backup battery, 25 ... Power supply voltage monitoring unit, 26 ... Memory information notification unit, 27 ... Memory cell, 28 ... Other devices 29 ... Display device

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] October 13, 1997

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction contents]

[0016] As the semiconductor device, when using the memory, the malfunction detection, for example, in the data write / read to the memory, the detection of data error of the memory cell, is implemented.

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 21/822 H01L 27/04 F 27/10 461 T

Claims (18)

[Claims] 1. A semiconductor device comprising: a semiconductor device; a status monitor for monitoring the status of the semiconductor or the operating environment of the semiconductor; and an information notification unit for notifying the monitoring result of the status monitor to the outside. Semiconductor device. 2. The semiconductor device according to claim 1, wherein said state monitoring unit is capable of comparing with a preset threshold value and outputting the comparison result as a monitoring result. 3. The semiconductor device according to claim 2, wherein the threshold value of said status monitor can be freely changed. 4. The semiconductor device according to claim 1, wherein said state monitor monitors a power supply voltage. 5. The semiconductor device according to claim 1, wherein the state monitoring unit detects a malfunction of the semiconductor device. 6. The semiconductor device according to claim 5, wherein the power supply voltage is changed in the malfunction detection. 7. The semiconductor device according to claim 5, wherein the power supply voltage is changed by an arbitrary predetermined value in the malfunction detection. 8. The semiconductor device according to claim 5, wherein in the malfunction detection, the fluctuation of the power supply voltage is made random. 9. The semiconductor device according to claim 5, wherein in the malfunction detection, the power supply voltage fluctuates periodically. 10. An information processing system incorporating a semiconductor device according to claim 1, wherein said semiconductor device is optimally controlled based on information from said information notifying unit. Processing system. 11. An information processing system incorporating the semiconductor device according to claim 1, wherein the information processing system is optimally controlled based on information from the information notification unit. Information processing system. 12. The information processing system according to claim 10, wherein switching control of a power supply source of the semiconductor device is performed. 13. The information processing system according to claim 10, wherein stabilization control of a supply voltage of the semiconductor device is performed. 14. The information processing system according to claim 10, wherein control for stopping operation of unnecessary parts of the information processing system is performed. 15. The information processing system according to claim 11, wherein the power of the information processing system is turned off. 16. An information processing system incorporating the semiconductor device according to claim 1, wherein control for displaying information on an operation state of the semiconductor device is performed based on information from the information notification unit. The information processing system according to claim 11. 17. The semiconductor device according to claim 5, wherein when the semiconductor device is a memory, the malfunction detection detects a data error in a memory cell in writing / reading data to / from the memory. 18. A Dynamic R as a semiconductor device.
2. When an AM (DRAM) is used, a memory cell and a logic cell of the DRAM are mixedly mounted on the same chip, and the processing of the state monitoring unit and the information notification unit is executed in the logic cell. 13. The semiconductor device according to claim 1.