JPH10260907A - Bus interface system and bus interface diagnostic system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable secure adaptation to the format of the bus of a host machine as to the bus interface system which serves for an interface needed to back up the main storage of an information and the diagnostic system which diagnoses whether its state is proper or not. SOLUTION: This system is equipped with a storage means 11 which stores information written in a 1st memory, a decision means 12 which decides whether or not information has a feature, a compressing processing means 13 which generates a compressed information sequence by removing a redundant part from a string giving truth, a sending-out means 14 which divides pieces of identification information of the compressed information sequence and information precedent to it in the time serial order and sends transferred information out serially, a separating means 15 which extracts the compressed information sequence from the transferred information according to the identification information, an expanding process means 16 which expands the compressed information sequence according to the format and feature, and a backup means 17 which finds composition information while making them correspond to the time serial and backs up the information in a 2nd memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is arranged between a bus of two information processing devices to which a standby redundancy system or a normal redundancy system is applied. The present invention relates to a bus interface method for backing up a memory and a bus interface diagnosis method for diagnosing the status of the bus interface method.

[0002]

2. Description of the Related Art In a switching system constituting a public communication network or a system requiring unmanned operation for a long time, load distribution and function distribution are achieved by a plurality of processors in order to secure desired reliability. Redundant configuration applies. Further, in such a system, the current operation is performed through a bus interface applied between the buses of these processors, with the aim of maintaining the operation smoothly and accurately in the case of system switching due to a failure or the like. Important information generated during the processing of the system is backed up.

FIG. 6 shows a conventional bus interface system. In the figure, a processor (CPU) 92 ₁ , a random access memory (RAM) 93 ₁ , a read-only memory (ROM) 94 connected to a bus 91 _1
A system 95 ₁ composed of 1 and a system 95 ₂ composed of a processor 92 ₂ , a random access memory 93 ₂ , and a read-only memory 94 ₂ connected to a bus 91 ₂ are connected via a bus interface 96.

[0004] The bus interface 96 is opposed to a connecting portion 97 made of a combination of not-shown connecting electric parts (connectors, electric wires, etc.) via the connecting portion 97.
And bus corresponding parts 98 ₁ and 98 ₂ having the same configuration.

[0005] Bus corresponding section 98₁Then, bus 91₁Is
Buffa gate 99₁Control unit 100 via₁The first ba
Terminal and latch circuit 101₁Input and buffer game
To 102₁Of the control unit 100₁Second
Main terminal 103 ₁Is connected. Also,
Gobe 100₁The first through fifth outputs of
Buffer gate 99₁Have two direction control terminals
And the latch circuit 101₁Gate and control terminals
And the buffer gate 102₁Connected to the control terminals of
Continued. Also, the latch circuit 101₁Output and buffer
Gate 102₁Are connected to one end of the connection portion 97.
Continued.

[0006] The bus corresponding section 98_Two About the configuration
Is the bus corresponding unit 98 as described above.₁Is the same as
Therefore, the same reference numeral as “2” is attached to each corresponding component.
The same reference numerals are given and the description is omitted here. This
In a conventional example of such a configuration, for example, a system configuration circuit (not shown) is used.
From the road 0 series 95 ₁ Is the active system and the first system is 95_Two But
If an instruction to reserve is given,
100₁ Is the buffer gate 99₁ Bus 91 via₁ 
To the latch circuit 101₁ And buffer gate 102₁ Contact with
And the buffer gate 102₁ Close setting
And bus 91₁ Main memory 103₁ Connect. one
One, control unit 100_Two Is the buffer gate 99_Two The two-way
And the buffer gate 102_Two Opened
By setting the other end of the connection unit 97 to the main memory 103_Two of
Connect to bus terminal.

That is, the bus 91 ₁ is connected to the main memory 103 ₁ via the buffer gate 99 ₁ and the control unit 100 ₁ , and connects the latch circuit 101 ₁ , the connection unit 97, the buffer gate 102 ₂ and the control unit 100 ₂ . since the extended to the main memory 103 ₂ via the backup of information written to the processor 92 ₁ is the main memory 103 ₁ is taken into the main memory 103 ₂ via a bus which is extended in this manner.

[0008]

By the way, in such a conventional example, since the bus is extended from the working system to the standby system without changing its basic configuration, the connection portion 97
Adapts to the large bus width of recently developed processors, because the number of connector pins and the number of electric wires are greatly increased and the shape and dimensions of applicable circuit boards are hindered by restrictions. It was difficult.

Further, in such a processor, a shared bus for transmitting addresses and transmitting and receiving data in a time-division manner in order to achieve a desired large throughput is not applied, and the bus cycle is remarkable. Because of the shortening, it was actually difficult to apply the same time division method to the connection unit 97. In addition, along with the development of such processors, the supply of many previously developed processors is generally not performed one after another even from a second source, so that not only existing systems but also newly developed ones are developed. It is also required to apply the latest model processor to the system.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus interface system and an interface diagnostic system capable of inexpensively and surely adapting to a bus model of a higher-order model and enabling a redundant configuration of a processor.

[0011]

FIG. 1 is a block diagram showing the principle of the present invention.

According to a first aspect of the present invention, information written in a first memory connected to a first bus via the first bus and an address indicating a storage destination of the information are stored in a time series. The storage means 11 for storing in the order of the first-in first-out method, and the monitored information sequence composed of the information and / or the address stored in the storage device 11 and having a predetermined characteristic. Determining means 12 for determining whether or not the compressed information string is given as a result of the determination performed by the determining means 12 from the information and addresses stored in the storage means 11; A compression processing unit 13 for generating a compressed information sequence by removing a redundant portion from the sequence under a predetermined feature; a compression information sequence generated by the compression processing unit 13; Of the information and addresses stored in the compressed information sequence extracted by the compression processing means 13 and preceding the compressed information sequence, and the identification information of the two. The transmission unit 14 divides the sequence in order to generate transferred information having a word length smaller than the width of the first bus, and transmits the transferred information serially. The separating means 15 for taking in and separating the compressed information sequence and the non-compressed information included in the transferred information based on the correlation with the identification information, and the format of the compressed information sequence separated by the separating means 15 is predetermined. Expansion processing means 16 for expanding the compressed information sequence based on the characteristics and restoring the compressed information sequence
And assembling the uncompressed information separated by the separating means 15 and the compressed information string restored by the decompression processing means 16 while associating the time series with the uncompressed information and the compressed information string. And backup means 17 for obtaining addresses and information individually included in the second bus and backing up the information in a second memory connected to the second bus via the second bus. And

According to a second aspect of the present invention, in the bus interface system according to the first aspect, the information is written into the first memory by the information processing device connected to the first bus, and And / or the information and / or the address in a fetch cycle of an instruction executed by the information processing apparatus and including the information and / or the address and requesting that the information be written. It is characterized in that it is determined whether or not one of the monitored information strings has a predetermined characteristic.

According to a third aspect of the present invention, in the bus interface system according to the first or second aspect, the judging means 12 divides the monitored information sequence into a plurality of fields, and has a predetermined feature. It is characterized in that the determination as to whether or not there is a data is made in the field unit.

According to a fourth aspect of the present invention, in the bus interface system according to any one of the first to third aspects, the predetermined feature is a sequence of addresses given in a chronological order or a sequence of the addresses. Are provided as conditions for forming a predetermined word sequence. According to a fifth aspect of the present invention, in the bus interface system according to any one of the first to fourth aspects, the predetermined feature is a sequence of information or a sequence of information given in chronological order. A different sequence is provided as a condition for forming a predetermined sequence of words.

According to a sixth aspect of the present invention, in the bus interface system according to any one of the first to fifth aspects, the storage means 11 is predetermined in a storage area of the first memory. The information is stored only for the information written in the specific storage area and the address indicating the specific storage area. According to a seventh aspect of the present invention, in the bus interface system according to any one of the first to sixth aspects, information to be written to the second memory by the backup means 17 or a sequence of these information is provided. A criterion for determining normality is given in advance, and monitoring means 21 is provided for monitoring information written to the second memory at a predetermined frequency or a sequence of these information based on the criterion. And

FIG. 2 is a block diagram showing the principle of the present invention. The invention according to claim 8 is applied bidirectionally between two different buses, and the two bus interface systems 31 ₁ and 31 _{2 according} to any one of claims 1 to 7, Bus interface method 3
1 _1, 31 of the _two, delivery means constituting either 14
Loopback means 32 forming a folded transmission path extending from the output end of the first section to the input end of the separation section 15 constituting the other side; information and addresses stored by the storage section 11 forming one bus interface system; A correctness determining means for correlating the information and the address returned via the return transmission line formed by the means to determine the correctness of the latter.

According to the ninth aspect of the present invention, the two bus interface systems according to any one of the first to seventh aspects are applied bidirectionally between two different buses.
1, 31 and two bus interface systems 31 ₁ , 3
Of 1 _2, a loop-back means 41 for forming a folded transmission path extending from the input end of the separating means 15 forming either the output end of the delivery means 14 constituting the other, constituting one of the bus interface system The information and address stored by the storage unit 11 and the loopback unit 41
And a correct / incorrect determination unit 33 for determining whether the information is correct or not by correlating the information returned via the return transmission path formed by the method with the address.

(Operation) According to the first aspect of the present invention, the discriminating means 12 judges whether or not the information and addresses stored by the storage means 11 in chronological order have predetermined characteristics. The processing unit 13 removes the redundancy from the compressed information sequence for which the result is true to generate a compressed information sequence. The transmitting means 14 merges the non-compressed information which has not been subjected to compression into the compressed information sequence and divides it in a time series to generate transferred information having a word length shorter than the width of the first bus. , And transmits the transferred information in series.

On the other hand, the separating means 15 and the decompression processing means 16 restore the compressed information sequence and the non-compressed information by tracing the above-described steps in reverse according to the identification information indicating the above-mentioned compression format. Further, the backup means 17 assembles the compressed information sequence and the non-compressed information thus decompressed in the above-described chronological order to obtain information to be written to the second memory and the address of the information. Is written in the corresponding area of the second memory.

Further, the amount of information to be transferred sent from the sending means 14 to the separating means 15 is smaller than the information and address information given from the first bus by the amount of uncompressed information. Therefore, the number of signal lines used for transmitting the transferred information is smaller than the width of the first bus, and the backup to the second memory is performed efficiently.

According to a second aspect of the present invention, in the bus interface system according to the first aspect,
Since the determination means 12 performs the determination in the fetch cycle preceding the execution cycle of the information processing device connected to the first bus, the responsiveness of the processing to be performed in accordance with the result of the determination is ensured to be high. Is done. According to the third aspect of the present invention, in the bus interface system according to the first or second aspect of the present invention, the determining unit 12 determines the monitored information sequence in units of fields, and thus determines the monitored information sequence. Although the monitoring information sequence is long, the amount of information to be compressed is large, so that the efficiency of the processing performed by the determination means 12 is high, and the responsiveness is improved.

According to a fourth aspect of the present invention, in the bus interface system according to any one of the first to third aspects, the predetermined features are arranged in chronological order. Is given as a condition for forming a predetermined word string, and therefore the discrimination means 12
Can determine whether or not the feature exists by a simple correlation process. Therefore, the configuration is simplified and the responsiveness is improved.

According to a fifth aspect of the present invention, in the bus interface system according to any one of the first to fourth aspects of the present invention, the predetermined characteristic is a sequence of information in a time-series order or Since the different columns of such information are given as conditions for forming a predetermined word column, the determination means 12 can determine whether or not the feature exists by a simple correlation process. Therefore, the configuration is simplified and the responsiveness is improved.

According to a sixth aspect of the present invention, in the bus interface system according to any one of the first to fifth aspects, the storage means 11 is predetermined in the storage area of the first memory. Since the storage is limited to the information written in the specific area and the address indicating the specific storage area, the size of the storage area to be backed up is reduced.

That is, since the information amount of the information to be transferred transferred from the first bus to the second bus is reduced, even if the information amount of the compressed information sequence to be compressed by the compression means is small, the speed is low. The backup is reliably performed using the hardware described above. According to a seventh aspect of the present invention, in the bus interface system according to any one of the first to sixth aspects of the present invention, the monitoring unit 21 controls the backup unit 17 to write data to the second memory. Since the monitoring information sequence is monitored based on a predetermined normality determination criterion, the confidentiality of a failure occurring in the second memory is avoided.

According to the eighth aspect of the present invention, the correctness / incorrectness determination means 33 determines whether the information and the address stored in the storage means 11 constituting one of the bus interface methods and the output end of the transmission means 14 of the bus interface method. Since the information and the address returned via the loopback transmission path formed by the loopback means 32 are correlated to determine whether the latter is correct, the sending means 14 and the separating means 15 are used.
It can be surely diagnosed whether or not each stage except for the signal line connecting the two is normally operating.

According to the ninth aspect of the present invention, the object to be judged by the right / wrong judgment means 33 is from the output end of one of the bus interface type separation means 15 to the loop back means 41.
The information and the address returned via the return transmission path formed by the above are used. Since such information and addresses are obtained through the signal lines connecting the sending means 14 and the separating means 15, it is ensured that each stage including these signal lines is operating normally. Can be diagnosed.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a diagram showing an embodiment corresponding to the first to seventh aspects of the present invention. In the figure, components having the same functions and configurations as those shown in FIG. 6 are denoted by the same reference numerals, and description thereof is omitted here.

Difference between this embodiment and the conventional example shown in FIG.
Is the connection part 97 and the latch circuit 101 ₁ , 101_Two And
Fagate 102₁ , 102_Two Confounding provided in place of
In section 51. The confounding part 51 is a bus 91₁ Connected to
Bus buffer gate 52₁ And bus 91 _Two Connected to
Sbuffer gate 52_Two Along with these
Fagate 52₁ , 52_Two Delay times cascaded between
Road 53, analysis processing unit 54, FIFO 55, demultiplexing
Kusa 56, transmission interface 57, connection unit 58, reception
Interface 59, multiplexer 60, FIFO6
1 and an analysis processing unit 62.

[0031] As to the correspondence relationship between the block diagram shown in Figure 1, the bus buffer gate 52 ₁ and the delay circuit 53 corresponds to the storage means 11, the analysis processing unit 54 corresponds to the determining means 12 and the compression processing unit 13 The demultiplexer 56, the transmission interface 57, and the connection unit 58 correspond to the transmission unit 14, the reception interface 59, the multiplexer 60, and the FIFO 61 correspond to the separation unit 15, and the analysis processing unit 62 and the bus buffer gate 52 ₂
Corresponds to the expansion processing means 16 and the backup means 17.

FIG. 4 is an operation flowchart of an embodiment corresponding to the first, third to sixth aspects of the present invention. Less than,
The operation of the present embodiment will be described with reference to FIGS. Analysis processing unit 54 and the delay circuit 53 is supplied via the bus buffer gate 52 _1, and decodes the status signal indicating the state of the bus 91 _1, the bus 91 ₁
For bus cycle processor 92 ₁ to write some information into the main memory 103 ₁ (hereinafter, simply referred to as. "Write cycle") monitors the start of (FIG. 4
(1)).

In this write cycle, the delay circuit 53
Stores addresses and data supplied via the bus 91 ₁ in the order of time series. Further, the analysis processing unit 54
Is obtained by determining whether or not the delay circuit 53 is full (FIG. 4 (2)), and adding "1" to an address newly stored in the delay circuit 53 preceding the address. (Hereinafter simply referred to as “increment address”) is determined (FIG. 4 (3)). If the former result is true and the latter result is false, the following processing is performed. I do.

While analyzing the area of the delay circuit 53, the analysis processing unit 54 extracts untransmitted addresses and data from the addresses and data stored in the delay circuit 53 (FIG. 4).
(4)). Further, the analysis processing unit 54 sets a column consisting only of the increment address (hereinafter, referred to as “increment address sequence”) among such untransmitted addresses.
For the address that does not correspond to the increment address in advance, the first transmission information including the control information indicating the fact and the corresponding data is generated without performing any processing. In this case, the data is converted into second transmission information including control information indicating the head address and the number of words and corresponding data (FIG. 4).
At the same time as (5)), the transmission information is stored in the FIFO 55 in correspondence with the time series (FIG. 4 (6)).

The demultiplexer 56 transfers the transmission information thus accumulated in the FIFO 55 to the buses 91 ₁ and 91 _2.
Is divided into transmission units of a word length (for example, 16 bits) smaller than the width of
Are transmitted in series. On the other hand, the multiplexer 60 connects these transmission unit columns to the connection unit 58.
, Through the receiving interface 59, and by performing a process opposite to the process performed by the demultiplexer 56, the above-described transmission information is restored and the FIFO 6
Accumulate in 1.

The analysis processing unit 62 sequentially fetches the transmission information stored in the FIFO 61, classifies it into first transmission information and second transmission information based on the difference in the control information described above, and for information, it gives to the bus 91 ₂ through the respective address and data bus buffer gate 52 ₂ included based on the format. However, for the second transmission information, the analysis processing unit 62 performs the expansion processing opposite to the processing performed by the analysis processing unit 54 based on the head address and the number of words included in the included control information, in a similar manner to restore the column of the address and data applied to the bus 91 _2.

As described above, according to the present embodiment, the bus 91
₂ are compressed based on the characteristics of the address, and are efficiently connected to the bus 58 via a connection portion 58 comprising a set of signal lines smaller than the bus width of the buses 91 ₁ and 91 _2. 91 ₂ is transmitted to. Therefore,
Even if the widths of the buses 91 ₁ and 91 ₂ are extremely large or the bus cycle is extremely short, the increase in the number of signal lines required for connection between the 0-system and the 1-system is minimized, and the efficiency is improved. The backup of the main memory from the active system to the standby system is realized.

In the above-described embodiment, determination of a feature that constitutes an increment address for all bits indicating an address and compression transmission corresponding to the feature are performed. May be limited to only the specific field that constitutes.
Further, in the above-described embodiment, the compression transmission is performed only for the address, but may be performed similarly for the data.

Further, when the same data is stored at different addresses arranged in time series, the data need not be transferred. In the above-described embodiment, the backup target is the entire area of the main storage. However, the present invention is not limited to such a configuration, and the backup should be performed in the standby system prior to system switching. When the amount of information is small, the backup may be performed only in the storage area in which the information is stored. In such a configuration, the delay circuit 53 uses the address and data of the corresponding storage area. The delay circuit 53 accumulates addresses and data related to all write cycles, and the analysis processing unit 54 processes only addresses and data related to the same storage area. You can also.

Hereinafter, referring to FIG. 3 and FIG.
An embodiment corresponding to the invention described in (1) will be described. Analysis processing unit 54, a processor 9 which is connected to the bus 91 ₁
By 2 ₁ a status signal to be output to the bus 91 ₁ uptake via the bus buffer gate 52 _1, and decodes to identify the instruction code of the instruction such processors 92 ₁ is fetching, the instruction code Is an instruction code of an instruction requesting writing to the main memory. Further, the analysis processing unit 5
If the result of the determination is true, the address 4 fetches an address (and data, if possible) that is subsequently fetched as part of the instruction code. It performs feature identification and compression processing based on the procedure.

Such a column of addresses is defined in claims 1 and 3
Unlike the embodiments corresponding to the inventions described in (1) to (6), the analysis processing unit 54 is provided in the fetch cycle preceding the above-described execution cycle, so that the analysis processing unit 54 generates transmission information and writes the transmission information in the FIFO 55 Can be started prior to the execution cycle. Therefore, according to the present embodiment, the responsiveness is improved as compared with the embodiments corresponding to the first, third to sixth aspects of the present invention, and when there is no request to increase the responsiveness, the analysis processing unit 54
The lower limit of the propagation delay time required for each subsequent stage is relaxed.

Hereinafter, an embodiment corresponding to the invention described in claim 7 will be described with reference to FIG. Differences of the configuration of the embodiment of the invention according to the present embodiment Claim 1,3～6, the bus buffer gate 52 ₂ via the monitoring circuit 63 is connected to the bus 91 _2, and the monitoring The point is that the control output of the circuit 63 is connected to the corresponding control input of the analysis processing unit 62.

The correspondence between the present embodiment and the block diagram shown in FIG.
Corresponding to Hereinafter, the operation of the present embodiment will be described. Monitoring circuit 63, requests pending outputting the address and data subsequent to the analysis processing unit 62 at a predetermined frequency, and the main memory 103 ₂ of a predetermined area, normally by actually reading , And outputs the result of the determination via a man-machine interface (not shown). Therefore, the main memory 103 provided in the first system 95 ₂
Avoiding the confidentiality of obstacles for ₂

[0044] In the present embodiment, main memory 103 ₂ normally data is written, and is not described at all for the criteria of whether it is held, for such criteria, desired Main memory 103 _{2 with} accuracy of
If the correctness can be determined, for example, a parity check or any other method may be used. FIG. 5 is a view showing an embodiment corresponding to the eighth and ninth aspects of the present invention.

The components of the confounding portions 51a and 51b are indicated by the same reference numerals as those shown in FIG. 3 with the addition of the suffixes "a" and "b", and the description and illustration thereof are omitted here. . In the figure, between the bus 91 ₁ and the bus 91 _2, two intertwined portion 51a, 51b are arranged in opposite directions to each other. Transmission interface 5 of confounding part 51a
7a and the receiving interface 5 of the confounding part 51b.
Between the input end of 9b, the loopback circuit 64 is arranged, one of the stages, the output and bus receiving interface 59b sandwiched between the output of the bus buffer gate 52 ₁ a and the input of the transmission interface 57 Buffer gate 52 ₂ b
A discriminating circuit 66 is connected between any one of the stages sandwiched between.

The operation of this embodiment will be described below. Address and data supplied via the bus 91 ₁ After the process described above is performed in each unit disposed in the preceding stage of the transmission interface 57a constituting the entangled portions 51a, the loop back circuit 64, the intertwined portions 51b The signal is returned to the discriminating circuit 66 via the receiving interface 59a. The determination circuit 66 sends the returned address and data and the bus 91 corresponding to the address and data.
Intertwined portions 51a by comparing the address and data given from _1, among the components of 51b, connecting portions 58a, each part of the bus 91 ₁ side from 58b to whether the discrimination is operating normally.

Hereinafter, an embodiment corresponding to the ninth aspect of the present invention will be described with reference to FIG. The difference between the present embodiment and the embodiment according to the eighth aspect is that the loopback circuit 6 replaces the loopback circuit 64.
5 is located between the other end of the connecting portion 58a and one end of the connecting portion 58b.

As for the correspondence between the present embodiment and the block diagram shown in FIG. 2, the loop-back circuit 65 corresponds to the loop-back means 41, and the discrimination circuit 66 corresponds to the correct / incorrect judgment means 33. In the present embodiment, the address and data supplied through the bus 91 ₁ After the process described above is performed in the preceding stage until the arranged respective units of the receiving interface 59a of the entangled portions 51a, a loopback circuit 6
5. Returned to the discriminating circuit 66 via the connecting portion 58b constituting the confounding portion 51b. The discriminating circuit performs the discrimination in the same manner as in the embodiment according to the eighth aspect of the present invention.
a, 58b, so that the entangled portions 51a, 5b
Among 1b, the connecting portion 58a, a determination is made whether each part of the bus 91 ₁ side is operating normally containing 58b is performed.

In each of the above embodiments, the control unit 1
00 ₁ , 100 ₂ and the confounding unit 51 and the processor 92
However, the present invention is not limited to such a configuration.
2 may directly request the processor 92 to release the bus 91. In each of the above embodiments, the size of the delay circuit 53 is not described at all.
It can be appropriately determined based on the widths of the buses 91 ₁ and 91 ₂ , the number of signal lines constituting the connection unit 58, the processing speed of the analysis processing units 54 and 62, and other factors.

Further, in each of the above-described embodiments, the control information includes the word length of the compressed address. However, the present invention is not limited to the format of the transmission information including such control information, If the transmission efficiency is ensured, for example, the word length of the transmission information may be fixedly set to a predetermined value. Further, in each of the above-described embodiments, the difference between the address and data characteristics and the preceding characteristics is “1”. However, the present invention is not limited to such characteristics, and a desired response can be obtained. If the backup of the memory is ensured while the performance is ensured, these address and data strings constitute a sequence of known words, or a bit operation based on a predetermined algorithm (for example, division by a generator polynomial). , Convolution operation, etc.) may be applied.

[0051]

As described above, according to the first aspect of the present invention, the amount of information transferred between buses is reduced, and the number of signal lines used for the transfer is reduced. Furthermore, according to the second aspect of the present invention, since the period during which the specific processing is performed is limited, the responsiveness to the information processing device connected to the bus is enhanced.

According to the third aspect of the present invention, since the information to be subjected to the compression processing is determined on a field basis, the processing efficiency is improved. Further, in the inventions according to the fourth and fifth aspects, since the feature serving as the reference for the above-described determination is given in advance as a column or a column of differences, the determination is performed by a simple correlation process, and the configuration is simplified. It is planned.

Further, in the invention according to claim 6, since the processing is performed with the storage area to be backed up being limited, the backup is performed reliably using low-speed hardware. Further, according to the invention of claim 7, since the addresses and information to be backed up are monitored, the confidentiality of the failure of the standby memory is avoided.

According to the present invention, the operation status of each stage except for the signal line connecting the working system and the protection system is diagnosed by forming a loop-back circuit. Further, according to the ninth aspect of the present invention, it can be diagnosed whether or not the connection of the signal line is normal. Therefore, in a system to which these inventions are applied, it is possible to ensure that an optimal processor is applied to a required function or performance, and to flexibly adapt to various specifications such as load distribution, function distribution, and the like. Become.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention.

FIG. 2 is a principle block diagram of the invention according to claims 8 and 9;

FIG. 3 is a diagram showing an embodiment corresponding to the first to seventh aspects of the present invention.

FIG. 4 is an operation flowchart of an embodiment corresponding to the first, third, and sixth aspects of the present invention.

FIG. 5 is a diagram showing an embodiment corresponding to the inventions according to claims 8 and 9;

FIG. 6 is a diagram showing a configuration example of a conventional bus interface system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Accumulation means 12 Judgment means 13 Compression processing means 14 Sending means 15 Separation means 16 Expansion processing means 17 Backup means 21 Monitoring means 31 Bus interface method 32, 41 Loopback means 33 Correctness judgment means 51 Entanglement part 52 Bus buffer gate 53 Delay circuit 54, 62 Analysis processing unit 55, 61 FIFO 56 Demultiplexer 57 Transmission interface 58, 97 Connection unit 59 Reception interface 60 Multiplexer 63 Monitoring circuit 64, 65 Loopback circuit 66 Discrimination circuit 91 Bus 92 Processor 93 Random access memory 94 Read-only memory 950 system, 1 system 96 bus interface unit 98 bus corresponding unit 99, 102 buffer gate 100 control unit 101 latch circuit 103 main memory

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hidetoshi Iwasa 4-1-1 Kamikadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Ryoji Takano 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 in Fujitsu Limited

Claims (9)

[Claims] 1. A first-in, first-out method in which information written to a first memory connected to a first bus via the first bus and an address indicating a storage location of the information are chronologically ordered. Storage means for accumulating the information, and discrimination means for discriminating whether or not a monitored information sequence comprising at least one of the information and the address stored in the storage device has a predetermined characteristic. Extracting, from the information and addresses stored in the storage means, a compressed information sequence that gives true as a result of the determination performed by the determination means, and extracting the predetermined characteristic of the predetermined characteristic from the compressed information sequence. Compression processing means for removing a portion which is redundant below to generate a compressed information sequence; a compressed information sequence generated by the compression processing means; information stored in the storage means; Among the dresses, the non-compressed information that is not included in the compressed information sequence extracted by the compression processing means and that precedes the compressed information sequence, and the identification information of both of them are divided in the time series order and Sending means for generating transferred information having a word length smaller than the width of the first bus, transmitting the transferred information in series, and taking in the transferred information transmitted by the transmitting means; Separating means for separating the included compressed information sequence and non-compressed information based on the correlation with the identification information, based on the format of the compressed information sequence separated by the separating means and the predetermined feature, Expansion processing means for expanding the compressed information sequence and restoring the compressed information sequence; and extracting the uncompressed information separated by the separation unit and the compressed information sequence restored by the expansion processing unit in the time series. By assembling while taking correspondence of the above, the address and information individually included in these uncompressed information and the compressed information sequence are obtained, and the second bus connected to the second bus via the second bus is obtained. And a backup means for backing up such information in a memory. 2. The bus interface system according to claim 1, wherein the information is written to a first memory by an information processing device connected to the first bus, and the determining unit is executed by the information processing device. And a monitored information sequence including both or one of the information and the address in a fetch cycle of an instruction including the information and / or the address and requesting the writing of the information. A bus interface method for determining whether or not there is a predetermined characteristic. 3. The bus interface system according to claim 1, wherein the determining means divides the monitored information sequence into a plurality of fields, and determines whether or not there is a predetermined characteristic. Bus interface method characterized by performing on a field-by-field basis. 4. The bus interface system according to claim 1, wherein the predetermined feature is that a sequence of addresses given in chronological order or a sequence of differences between those addresses is used. A bus interface system provided as a condition for forming a predetermined word sequence. 5. The bus interface system according to claim 1, wherein the predetermined characteristic is a sequence of information given in a time series or a sequence of different information. The bus interface method is provided as a condition for forming a predetermined word sequence. 6. The bus interface system according to claim 1, wherein the storage means writes the data to a predetermined specific storage area in the storage area of the first memory. A bus interface method wherein information is stored only in an address and an address indicating a specific storage area. 7. The bus interface system according to claim 1, wherein the information to be written to the second memory by the backup means or the sequence of the information is determined by the backup means. A bus interface provided with a reference provided in advance, and monitoring means for monitoring the information written in the second memory at a predetermined frequency or a sequence of these information for normality based on the reference; method. 8. The two bus interface schemes according to claim 1, wherein the two bus interface schemes are applied bidirectionally between two different buses, and any one of the two bus interface schemes. Loopback means for forming a folded transmission path from the output end of the sending means constituting one of them to the input end of the separating means constituting the other, and the information stored by the storage means constituting the one bus interface method and Bus interface diagnostics, comprising: a correlation unit between an address, information and an address returned via the loopback transmission line formed by the loopback unit, and a determination as to whether the address is correct or not. method. 9. The two bus interface schemes according to claim 1, wherein the two bus interface schemes are applied bidirectionally between two different buses. Loopback means for forming a folded transmission path from the input end of the separating means constituting one of them to the output end of the sending means constituting the other, and information stored by the storing means constituting the one bus interface method and Bus interface diagnostics, comprising: a correlation unit between an address, information and an address returned via the loopback transmission line formed by the loopback unit, and a determination as to whether the address is correct or not. method.