JPH10260881A - Cache device, and entry managing method applied to the device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cache device that can perform LRU management of mass cache area with little management data/management load. SOLUTION: In a cache data area 14, storage areas (1 to 8) are managed in a ring shaped, and rotation delay counters, which hold the counts, which are passed by a pointer that detects an empty area are provided, corresponding to each storage area. A cache registration processing part 12 rewrites data in a new storage area even if the data is stored in any of the storage areas, for instance, when a host cache device generates cache out. Then, in the area 14, a rotation delay counter whose value is the larger is the older. About rotation delay counters which have the same value, the smaller index number shows newer data. It is possible to realize LRU management with a small number of management data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of hierarchically connecting a storage device having a high speed but a small storage capacity and a storage device having a relatively low speed but a large storage capacity, for example, so that a portion frequently accessed is provided. The present invention relates to a cache device suitable for application to a hierarchical storage device for high-speed access to data by selectively recording data in a high-speed storage device, and an entry management method applied to the device.

[0002]

2. Description of the Related Art With the recent increase in the amount of data due to the spread of networks and the increase in image data, the demand for large-capacity storage devices is generally increasing.
If the entire mass storage device of the class is composed of a high-speed semiconductor memory or a hard disk device, it becomes extremely expensive compared with other devices constituting the system, which has been an obstacle to the spread of the mass storage device. .

Therefore, in general, attention is paid to the locality of access that most of recorded data is hardly accessed, and only a part of frequently accessed data is stored in a semiconductor memory or a hard disk device. Hierarchical storage in which data is recorded in a high-speed storage device, and most of the other data that is not accessed much are recorded in a library device of portable media that can realize a large capacity at a relatively low speed but at a low cost. The device is getting attention. In this hierarchical storage device, taking advantage of the low cost-to-capacity of portable media, multiple media are combined inside the library storage device, and a storage medium having the capacity of several media is stored in the host system in the host system. It appears to be a large-capacity storage device.

Accessing data recorded on a portable medium stored in a library device requires exchange of media in the library device and spin-down / spin-up processing in a drive device. It takes several hundred to several thousand times as long as the access time of hard disk drives and other devices.However, since the majority of accesses are concentrated on high-speed storage devices, this difference in access time can be hidden on average. Thus, the data throughput of the entire apparatus can be kept high.

Since the performance of a library storage device depends on how much the number of media exchange processes that occur in the library device can be reduced, it is important how much access can be concentrated on the upper storage hierarchy. . In a cache device using a conventional semiconductor memory as a cache such as a hard disk device, the management of data in the cache requires a long time when the data in the cache was last accessed because of the simplicity of the mechanism and the high effect. LRU control that manages in a bidirectional list in order from the one used is often used.

[0006] In the hierarchical storage device, a plurality of cache devices are used in which a plurality of storage devices having different access performances are combined and an upper hierarchy is used as a lower hierarchy cache. For example, in a hierarchical storage device using a library device of a semiconductor memory, a hard disk device, and a magneto-optical disk, all data is recorded on a medium in the library device, and the data of the semiconductor memory and the hard disk are sequentially stored in descending order of access probability. A configuration is used in which a plurality of layers are used to operate as a multi-stage cache, such as recording in a device (in addition, a media loaded in a drive device is stored in a storage slot of a library device in a media cache). Conventionally, the cache area is managed by following the cache device combining a semiconductor memory and a hard disk device with the data recorded in each storage hierarchy. LRU for each layer
Although a method of managing data in a list has been adopted, the LRU list for managing a data area having a capacity of several GB, such as a hard disk device, is updated because the data becomes large in size. As a result, access to the hard disk frequently occurs, and the processing load for managing the list increases to a non-negligible degree.Therefore, normal access is hindered and the merit of caching data is diminished. Was.

[0007]

As described above, conventionally, there is a problem that the load for managing the LRU of the cache area impairs the efficiency of the normal access. The present invention has been made in view of such circumstances, and provides a cache device capable of performing LRU management of a large-capacity cache area with a small management data / management load, and an entry management method applied to the cache device. The purpose is to:

[0008]

According to the present invention, in order to achieve the above-described object, in a cache device in which a plurality of entries are managed in a ring shape, a plurality of entries are passed by a free area search pointer for searching for a free entry. A round delay mark indicating whether or not the cache hit has been provided for each entry, and entry management for newly rewriting the cache hit data with another entry is executed. In other words, according to the present invention, the entry is divided into two types, one with no delay and one with delay, and only the data that the LRU has meaning is correctly entered in the entry without delay. Since the data is held in the order of the index numbers, appropriate LRU management can be realized with a small amount of data such as an index number and a round delay mark.

In addition, when a cache hit without updating occurs, appropriate LRU management can be realized only by clearing the round delay mark without rewriting data. Can be further reduced.

Further, according to the present invention, in a cache device in which a plurality of entries are managed in a ring shape, a circulation delay counter for holding the number of times passed by a free area search pointer for searching for a free entry corresponds to each entry. On the other hand, entry management for rewriting the cache hit data to another entry is executed. That is, according to the present invention, an entry having a smaller value of the loop delay counter holds new data, and in an entry having the same value of the loop delay counter, newer data has a smaller index number. You are holding it. Therefore, also in the present invention, it is possible to realize appropriate LRU management with a small amount of data such as an index number and a circulation delay counter.

Also in the case of the present invention, when a cache hit involving no update occurs, appropriate LRU management can be realized only by decreasing the value of the round delay counter without rewriting data. Therefore, the load for the LRU management can be further reduced. Furthermore, when the value of the circulation delay counter is decreased, if the value indicates the lowest value, the data is newly rewritten with another entry, thereby avoiding the cache-out of frequently accessed data as much as possible. LRU management can be realized with more appropriate names.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a system configuration of a storage device according to the present invention. In the present invention, a library device is used as a back storage. The medium in the library device is a magneto-optical disk, which can not only add data but also delete and change data.

The CPU 1 controls the operation of the entire apparatus, reads out a program recorded on the hard disk 3 onto the main memory 2 and performs control according to the contents. The main memory 2 stores programs and data. A part of an area for recording data is used for recording management information, and the rest is used as a high-speed cache area. The hard disk 3 stores the control program and the contents of the management table at the start of the processing of the system, and the rest is used as a cache for data recorded in the library device.

The input / output control unit 4 is connected to a data bus or a LAN, receives an access request transmitted from an external device, and transmits a processing result and data. The library device 6 is driven and controlled by the library device control unit 5, and has a plurality of magneto-optical disk drive devices 7, a plurality of storage slots 8, and an accessor for transporting the magneto-optical disk between the magneto-optical disk drive device 7 and the storage slots 8. 9 is comprised. The storage slot 8 is for storing a magneto-optical disk. Numbers such as 1 to 10 are sequentially assigned to each magneto-optical disk in the library device, and a storage area in the library device includes:
A unique address in the system is assigned by the magneto-optical disk number and the block address on the magneto-optical disk. These components are connected by a system bus.

FIG. 2 shows a block configuration of a storage device having such a system configuration. The high-order cache device 11 is a high-speed storage device with a small capacity, and when data is accessed, first searches the high-order cache, and then searches the lower-order cache. The inside of the upper cache device 11 is managed by an LRU list or the like, and performs a cache-out process when a cache overflow occurs. In a normal cache device, the data to be cached out is overwritten on the cache,
The data is reflected in the lower storage device only when the data has the dirty attribute, and the data without the dirty attribute is simply deleted. The outdated data is reflected in the lower cache device.

The cache registration processor 12 registers data cached out of the upper cache device 11 in the lower cache data area 14. When the same data as the data to be cached out of the upper cache device 11 is stored in the lower cache data area 14, the cache registration processing unit 12 deletes the data and leaves an empty area in the lower cache data area 14. Secure and register again.

When there is data that does not exist in the upper cache device 11, the cache read processing unit 13
First, the lower cache data area 14 is searched, and when data is found, the data is transferred to the upper cache device 11. If there is no data in the lower cache data area 14, the data is directly transferred from the back storage 16 to the upper cache device 11.

The cache data area 14 is a lower-level cache area managed in a ring shape, and index numbers are sequentially assigned to the recording areas in the rotation direction. Then, it has a cache-out search pointer and an empty area search pointer indicating any specific storage area.

The cash-out processing section 15 performs a cache-out process for creating an empty area in the lower cache data area 14. The cache-out processing unit 15 first searches the lower cache data area 14 for data that has not been accessed for a long time (LRU), reflects the data in the back storage 16 if necessary, and then reads the lower cache data area. 14 to delete the data.

The back storage 16 compares the upper cache device 11 and the lower cache data area 14 with each other.
It is a storage device having a large capacity and a relatively low speed. All data in the device has a unique address in the back storage 16.

FIG. 3 shows the contents of a management table for managing the lower cache data area 14.
In FIG. 3, the cache index is an index number of the lower cache data area 14. The used / unused flag indicates whether data is stored in the lower cache data area 14 indicated by the index, and the dirty flag indicates whether data has been updated in the cache.

The data address indicates the address of the data on the cache on the back storage 16. The round delay counter is an attribute of data in the cache. When the data is registered in the cache, the value of the circulation delay counter is 0, and the larger the value, the longer the data has not been accessed in the cache.
The procedure for changing the value of the counter will be described with reference to FIGS.

FIG. 4 shows changes in the contents of the management table when an operation is performed on the lower cache data area 14 based on the cache management table in the state shown in FIG.

In the cache state shown in FIG. 3, when a cache out occurs from the upper cache device 11, first,
It is searched whether data cached out from the upper cache device 11 exists in the lower cache data area 14, and if found, is deleted from the lower cache data area 14.

Next, a search for an empty area for recording data is performed. In the search of the empty area, the data having the larger index is searched in order from the data of the index indicated by the empty search pointer. FIG. 4 shows a state in which data is recorded in a free area (index 6) found first by searching in a direction in which the index increases (ring rotation direction). The value of the circulation delay counter of newly recorded data is 0. The empty search pointer points to the next index after the used index.

FIG. 5 shows a state after a further cache-out from the upper cache device 11 in the state of FIG. When an empty area is searched from the index 6, no empty area is found up to the maximum index number. Therefore, the search pointer is set to the index 1 and the search is started again. The data remaining in the cache when the empty search pointer is set to 1 increases the value of the round delay counter of each data by one as the number of times that the empty search pointer has passed. At the same time, the maximum number of circuit delays is also increased by one. When the search for an empty area is advanced from the index 1, data is recorded in the area of the index 2 because the area is an empty area.

FIG. 6 shows a state after data is cached out from the cache data area 14 in the state of FIG. As the data to be cached out, the one with the oldest access time in the cache data area 14 is selected. In comparison with the method of securing a free area, it can be understood that the data in the cache is older as the value of the circulation delay counter is larger, and that the data with the same counter value is older as the cache index is smaller.

To search for data to be cached out, first, the data having the largest round delay counter value at that time is read from the cache index indicated by the data search pointer in the direction in which the index increases (the direction of rotation of the ring). Perform search processing. When the data having the maximum round delay counter value 3 is searched from the index 1, the data of the index 5 is found first, so that the data of the index 5 is cached out.

Since the dirty flag of the data of the index 5 is OFF, the data has the same contents as the data recorded in the back storage 16, and there is no need to reflect the data in the back storage 16.
It is sufficient to simply change the used / unused flag of the index 5 to “empty”. At this point, the data search pointer points to index 6, which is the point where the next search starts.

FIG. 7 shows a state after further performing a cashout process from the state of FIG. When the data having the maximum number of round delays of 3 is searched from the index 6, the data is not found even if the search is performed up to the maximum index. Therefore, the index is returned to 1, and the search is further advanced in the index increasing direction. When the search is performed up to the maximum index, all data having the same maximum number of round delays is cached out. When the data search pointer returns to the index 1, the maximum number of round delays is reduced by one.

When the search for the data of the number of rotation delays 2 is advanced from the index 1, the data of the index 3 is found. Therefore, the data is cached out. No) and a free area.

When a cache out from the upper cache device 11 occurs, data having the same address is deleted from the lower cache data area 14 so that the data cached out from the upper cache device 11 does not have the dirty attribute. Even if there is, the LR in the lower cache data area 14 is always reflected in the new free area of the lower cache data area 14.
The order of U is preserved appropriately.

Next, the processing contents of the present apparatus will be described in detail for each embodiment. (First Embodiment) FIG. 8 is a diagram showing a main flow of a first embodiment of the present invention.

When the process is started, first, an initialization process for reading out management data recorded on a hard disk into a memory is performed (step A1). When the system is initialized, a request is accepted (step A2). If the request is access to data (Y in step A3), data read / write processing is performed, and the request is a termination request. If there is (Y in step A11), an end process of saving the management data to the hard disk is performed.

When an access to data is requested, it is first checked whether or not the requested data exists in the memory cache (step A4). If there is data (Y in step A4), the request is processed. Perform On the other hand, if the data does not exist in the memory (N in step A4), an area for data registration is secured in the memory cache. If there is no free area (N in step A5), a cache-out process of the memory cache shown in FIG. 9 is performed.

If the data exists in the hard disk cache (Y in step A7), the data is read out to the secured area on the memory (step A8), and the request is processed. On the other hand, if the data does not exist in the memory cache or the hard disk cache (N in step A7), the data is read from the magneto-optical disk of the library device to an area on the memory (step A9), and the request is processed.

FIG. 9 is a flow chart of a process for caching out data on a memory. First, data to be cached out is determined according to the memory cache management method (step B1). The hard disk cache is searched (step B2), and if data to be cached exists in the hard disk cache (Y in step B2), the data is deleted from the hard disk cache (step B3).

Next, a free area is secured in the hard disk cache by the procedure shown in FIG. 10, and the data cached out of the memory is recorded on the hard disk (step B4). Here, when the free space of the hard disk cache falls below the minimum specified value (here, 20% of the total hard disk cache capacity) (step B).
5), a hard disk cache-out process (to be described later with reference to FIG. 11) for increasing the free space up to the maximum specified value (40% in this case) is performed.

FIG. 10 is a flowchart of a process for securing a free area in the hard disk cache. Get_fr
An empty area is searched from ee_pointer (empty search pointer) to the maximum index of the cache area (steps C1 to C4). If a free area is found (Y in step C3), the free search pointer is set to the index next to the found index (step C10), and the free area is returned (step C1).
1).

On the other hand, if no free area is found up to the maximum index number (Y in step C2), the rounding delay count of all in-use data on the hard disk cache is increased by one, and the maximum rounding delay is set to one. Increase (step C5).

Then, a free area between the index 0 and the free search pointer is searched (step C).
6 to Step C9). If a free area is found (Y in step C8), the free search pointer is set to the index next to the found index (step C10), and the free area is returned (step C11).

On the other hand, if a free area is not found even after searching the entire cache area (Y in step C7), a hard disk cache out process for creating a free area in the cache is performed (step C12).

FIG. 11 is a flow chart of a process for caching out data in the hard disk cache. First, from the Get_used_pointer (data search pointer) to the maximum index of the cache area, an in-use area having the maximum number of round delays as the round delay attribute is searched (Step D1 to Step D4). If an area is found (Y in step D3), the data search pointer is set to the index next to the found index (step D11), and the data is deleted (if the found data has a dirty attribute, (After data is reflected in the library device) to make a free area (step D12).

On the other hand, if no data is found in the search up to the maximum index (Y in step D2), the maximum number of round trip delays is reduced by 1 (step D5). If the maximum number of round trip delays is smaller than 0 (Y in step D6),
Since there is no data area in use, the process ends.

Next, a search is made from the index 0 to the data search pointer for a used area having the maximum number of round delays as the round delay attribute (step D7 to step D1).
0). If an area is found (Y in step D9), the data search pointer is set to the index next to the found index (step D11), and the data is deleted (if the found data has a dirty attribute, (After data is reflected in the library device) to make a free area (step D12).

By processing according to such a procedure, it is possible to greatly reduce the amount of data for performing LRU management, such as only the index number and the circulation delay counter.

(Second Embodiment) FIG. 12 shows a configuration of a cache management table according to a second embodiment when a 1-bit round delay mark is used instead of a counter as a round delay attribute. .

Hereinafter, a cache management procedure using the round delay mark will be described. FIG. 13 is a flowchart of a process of searching for a free area in the case where the circuit delay mark is used. First, an empty area is searched from Get_free_pointer (empty search pointer) to the maximum index of the cache area (steps E1 to E4). If a free area is found (Y in step E3), the free search pointer is set to the index next to the found index (step E11), and the free area is returned (step E12).

On the other hand, if no empty area is found up to the maximum index number (Y in step E2), the round delay mark of all the data in use on the hard disk cache is set to 1 (step E5).

Next, an empty area between the index 0 and the empty search pointer is searched (steps E6 to E9). If a free area is found (Y in step E8), the free search pointer is set to the index next to the found index (step E11).
The free area is returned (step E12).

If no free area is found even after searching the entire cache area (Y in step E7), a hard disk cache out process for creating a free area in the cache is performed (step E10).

FIG. 14 is a flowchart of a cash-out processing of the hard disk cache when the round delay mark is used. First, Get_used_pointer
From the (data search pointer) to the maximum index of the cache area, a search is made for a used area with a loop delay mark (steps F1 to F5). If an area is found (Y in step F4), the data search pointer is set to the index next to the found index (step F10), and the data is deleted (if the found data has a dirty attribute, (After reflecting the data in the library device) to make it a free area (step F11).

Next, a search is made from the index 0 to the data search pointer for an in-use area with a loop delay mark (steps F6 to F9). If an area is found (Y in step F8), the data search pointer is set to the index next to the found index (step F10), and the data is deleted (if the found data has the dirty attribute, (After reflecting the data in the library device) to make it a free area (step F11).

On the other hand, if the in-use area with the circuit delay mark cannot be found (Y in step F7), the data without the circuit delay mark is started from the data search pointer (step F12, step F2 to step F2).
5) Search in the rotation direction of the ring cache.

When the loop delay mark is used, the loop delay attribute of the data is classified into two types, that is, whether the round search pointer is delayed or not with respect to the empty search pointer. In this case, the new data that has not been delayed is arranged in the order of the LRU, and the old data for which the LRU does not make much sense retains the incorrect order. Therefore, expressing the counter value with one bit has the effect of further reducing the amount of management data.

(Third Embodiment) FIG. 15 is a flowchart illustrating a processing procedure when data is present in a hard disk cache when data is cached out of a memory cache according to a third embodiment.

First, data to be cached out is determined according to the memory cache management method (step G1). The hard disk cache is searched (step G2). If the data to be cached exists in the hard disk cache (Y in step G2), the round delay value of the data in the hard disk cache is reduced (step G3). Examples of the reduction method include the following.

(1) Decrement the circulation delay counter by one. If the circulation delay counter is already 0, set the counter value to 0
Leave as is. (2) Clear the orbit delay counter.

(3) Clear the circuit delay mark. If the data on the memory cache has the dirty attribute, the data on the memory is reflected in the area of the hard disk cache where the data is recorded, and the cache area on the memory is released (step G4).

On the other hand, if the data to be cached out does not exist in the hard disk cache (N in step G2), a free area of the hard disk cache is secured, and the data cached out of the memory is recorded on the hard disk (step G5). ). Here, when the free space of the hard disk cache falls below the minimum specified value (here, 20% of the total hard disk cache capacity) (Y in step G6), the free space is increased to the maximum specified value (here, 40%). Hard disk cache-out processing is performed (step G7).

In this manner, when data cached out of the memory does not have a dirty attribute, the load of data reflection on the hard disk cache can be suppressed. In addition, data that has just been cached out of the memory has a low circulation delay value in the hard disk cache, and the possibility of being cached out of the hard disk cache can be reduced.

(Fourth Embodiment) FIG. 16 is a flowchart for explaining a processing procedure when data is present in a hard disk cache when data is cached out of a memory cache according to a fourth embodiment.

First, data to be cached out is determined according to the memory cache management method (step H1). The hard disk cache is searched (step H2), and if the data to be cached out exists in the hard disk cache (Y in step H2), the round delay attribute of the data on the hard disk cache is checked (step H3), and the round delay attribute is checked. Is already cleared (the circulation delay counter is 0 or there is no circulation delay mark) (Y in step H3), the data is deleted from the hard disk cache (step H4).

On the other hand, when the circulation delay attribute can be reduced (N in step H3), the circulation delay value of the data in the hard disk cache is reduced (step H5). Examples of the reduction method include the following.

(1) Decrement the circulation delay counter by one. (2) Clear the orbit delay counter. (3) Clear the lap delay mark.

If the data in the memory cache has the dirty attribute, the data in the memory is reflected in the area of the hard disk cache where the data is recorded, and the cache area in the memory is released (step H6). .

On the other hand, if the data to be cached out does not exist in the hard disk cache (N in step H2), a free space in the hard disk cache is secured, and the data cached out of the memory is recorded on the hard disk (step H7). ). Here, when the free space of the hard disk cache falls below the minimum specified value (here, 20% of the total hard disk cache capacity) (Y in step H8), the free space is increased to the maximum specified value (here, 40%). Hard disk cache-out processing is performed (step H9).

By doing so, when data cached out of the memory does not have a dirty attribute, the load of data reflection on the hard disk cache can be suppressed. In addition, data that has just been cached out of the memory has a low circulation delay value in the hard disk cache, and the possibility of being cached out of the hard disk cache can be reduced. Further, data that is frequently accessed (accessed as soon as it is cached out of the memory cache) is located at the lowest LRU of the hard disk cache, and such data is cached out. Can be prevented.

[0069]

As described above in detail, according to the present invention, the management data amount of the large-capacity cache device can be reduced (for example, the LRU is stored in the cache index bidirectional list).
Requires a management area of 4 MB with an index of 16 bits and a cache capacity of 1 mega index. According to the present invention, a cache having the same capacity is searched according to an index number and a round delay counter. It is sufficient that there is at least a 1/16 256 KB management area. The cache data can be updated at a high speed by suppressing the capacity of the management data.

Also, if a round delay mark is applied instead of the round delay counter, new data that does not have a round delay will be correctly arranged in the order of LRU, and old data for which the LRU does not make much sense will be used. Since the incorrect order is maintained, and the counter value is represented by one bit, the amount of management data can be further reduced.

When the data cached out of the memory does not have the dirty attribute, by updating only the round delay attribute, the load of reflecting the data to the hard disk cache can be suppressed, and Data that has just been cached out will have a low circulating delay value in the hard disk cache, and the likelihood of being cached out of the hard disk cache can be reduced.

Even if data cached out of the memory does not have the dirty attribute, frequently accessed data is rewritten to reduce the load of data reflection on the hard disk cache. Can be. That is, data that has just been cached out of the memory has a low circulating delay value in the hard disk cache, so that the possibility of being cached out of the hard disk cache can be reduced, and frequently accessed data can be stored in the hard disk cache. The LRU can be positioned at the lowest position, and it is possible to prevent such data from being cached out.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system configuration of a storage device of the present invention.

FIG. 2 is a diagram showing a block configuration of a storage device of the present invention.

FIG. 3 is a diagram showing contents of a management table for managing a lower cache data area according to the present invention;

FIG. 4 is a diagram showing a change in the contents of a management table when an operation is performed on a lower cache data area based on the cache management table in the state shown in FIG. 3;

FIG. 5 is a diagram showing a state after a cache-out has occurred from a higher-level cache device in the state of FIG. 4;

FIG. 6 is a diagram showing a state after data is cached out from the cache data area to the back storage in the state of FIG. 5;

FIG. 7 is a diagram showing a state after further performing a cashout process from the state of FIG. 6;

FIG. 8 is a diagram showing a main flow of the first embodiment of the present invention.

FIG. 9 is a view showing a flow of a process of caching out data on a memory according to the first embodiment.

FIG. 10 is a view showing a flow of processing for securing a free area in the hard disk cache according to the first embodiment.

FIG. 11 is an exemplary flowchart showing the flow of a process of caching out data in the hard disk cache according to the first embodiment.

FIG. 12 is a diagram showing a configuration of a cache management table according to the second embodiment when a 1-bit round delay mark is used instead of a counter as a round delay attribute.

FIG. 13 is an exemplary view showing a flow of a process of searching for a free area in the case of using the orbit delay mark according to the second embodiment;

FIG. 14 is an exemplary view showing a cash-out processing flow of the hard disk cache in the case where the round delay mark of the second embodiment is used.

FIG. 15 is a flowchart illustrating a processing procedure when data exists in the hard disk cache when data is cached out of the memory cache according to the third embodiment.

FIG. 16 is a flowchart illustrating a processing procedure when data is present in the hard disk cache when data is cached out of the memory cache according to the fourth embodiment.

[Description of Signs] 1 CPU, 2 main memory, 3 hard disk,
4 ... I / O control unit, 5 ... Library device control unit, 6 ... Library device, 7 ... Magneto-optical disk drive device, 8 ...
Storage slot, 9 accessor, 11 upper cache device, 12 cache registration processor, 13 cache read processor, 14 cache data area, 15 cache out processor, 16 back storage.

Claims (12)

[Claims] 1. A cache device in which a plurality of entries are managed in a ring shape, wherein: a free area search pointer for searching for an empty entry; a stage-out pointer for searching for an entry for caching out data; A circling delay mark indicating whether or not the data has passed the empty area search pointer, and entry management means for newly rewriting cache hit data with another entry. A new or old data stored in the entry is represented by the index number of each entry and the circulation delay mark. 2. A cache device in which a plurality of entries are managed in a ring shape, wherein: a free area search pointer for searching for an empty entry; a stage out pointer for searching for an entry for caching out data; And a circling delay mark indicating whether or not the data is passed by the empty area search pointer, and when a cache hit involving updating occurs, the data is newly added to another entry. An entry management means for clearing the round delay mark corresponding to the entry holding the data when a cache hit that does not involve rewriting or updating occurs, the index number of each of the plurality of entries and the round The old and new data of the entry is indicated by the delay mark. Cache device which is characterized in that. 3. A cache device in which a plurality of entries are managed in a ring shape, wherein: a free area search pointer for searching for an empty entry; a stage out pointer for searching for an entry for caching out data; A circulation delay counter that is provided corresponding to each of the entries and holds the number of times that the free area search pointer has passed, and entry management means that newly rewrites the cache hit data to another entry. A new or old data stored in the entry is represented by an index number of each entry and the value of the circulation delay counter. 4. A cache device in which a plurality of entries are managed in a ring shape, a free area search pointer for searching for a free entry, a stage out pointer for searching for an entry to cache data out, and A wraparound delay counter provided for each of the entries and holding the number of passes by the free space search pointer; and when a cache hit involving updating occurs, the data is newly stored in another entry. Rewriting, when a cache hit involving no update occurs, comprising an entry management means for decreasing the value of the circulation delay counter corresponding to the entry holding the data, the index number of each of the plurality of entries, The entry holds according to the value of the circulation delay counter Cache apparatus characterized by representing the old and new over data. 5. A cache device in which a plurality of entries are managed in a ring shape, a free area search pointer for searching for a free entry, a stage out pointer for searching for an entry to cache data, and Circulating delay counter provided for each of the entries, and holding the number of times that the free area search pointer has passed, when a cache hit involving an update occurs, and when a cache hit involving no update occurs And, when the value of the circulation delay counter corresponding to the entry holding the data indicates the lowest value, the data is newly rewritten to another entry, and a cache hit without updating occurs, And the value of the circulation delay counter corresponding to the entry holding the data is at least An entry management means for decreasing the value of the loop delay counter when a value other than the above is indicated, and the data held by the entry based on the index number of each of the plurality of entries and the value of the loop delay counter. A cache device that expresses the old and new of a device. 6. A free entry securing means for caching out data to a predetermined number of entries when the number of free entries falls below a predetermined value. The cache device according to 1, 2, 3, 4, or 5. 7. A hierarchical storage device comprising a plurality of cache devices according to claim 1, 2, 3, 4, 5, or 6 connected hierarchically. 8. An empty area search pointer for searching for an empty entry, a stage out pointer for searching for an entry to cache data, and an empty area search pointer provided for each of a plurality of entries. An entry management method for a cache device, comprising: a circling delay mark indicating whether or not the data has been passed; and a plurality of entries being managed in a ring shape, the method further comprising a step of newly rewriting cache hit data to another entry. An entry management method, wherein the index number of each of the plurality of entries and the round delay mark represent new or old data held by the entries. 9. A free area search pointer for searching for an empty entry, a stage out pointer for searching for an entry to cache data, and a free area search pointer provided for each of a plurality of entries. An entry management method for a cache device, comprising: a circling delay mark indicating whether or not the data has been passed, and a plurality of entries being managed in a ring shape, wherein when a cache hit involving updating occurs, the data is deleted. The step of rewriting a new entry, and when a cache hit without updating occurs,
Clearing the circling delay mark corresponding to the entry holding the data, wherein the index number of each of the plurality of entries and the circling delay mark represent new or old data held by the entry. Characteristic entry management method. 10. A free area search pointer for searching for an empty entry, a stage out pointer for searching for an entry to cache data, and a free area search pointer provided for each of a plurality of entries. An entry management method for a cache device, comprising: a circulation delay counter for holding the number of passed times; and a plurality of entries being managed in a ring shape, comprising a step of newly rewriting cache hit data to another entry. An entry management method, wherein the index number of each of the plurality of entries and the value of the circulation delay counter represent new or old data held by the entries. 11. A free area search pointer for searching for an empty entry, a stage out pointer for searching for an entry to cache data, and the free area search pointer provided for each of a plurality of entries. An entry management method for a cache device, comprising: a circulation delay counter for holding the number of passes; a plurality of entries being managed in a ring shape, wherein when a cache hit involving updating occurs, the data is deleted. The step of rewriting a new entry, and when a cache hit without updating occurs,
Decreasing the value of the loop delay counter corresponding to the entry holding the data, and determining whether the data held by the entry is new or old based on the index number of each of the plurality of entries and the value of the loop delay counter. An entry management method characterized by expression. 12. An empty area search pointer for searching for an empty entry, a stage out pointer for searching for an entry to cache data, and an empty area search pointer provided for each of a plurality of entries. An entry management method for a cache device comprising a circulation delay counter for holding the number of passes, and a plurality of entries being managed in a ring shape, wherein a cache hit involving an update occurs and Rewriting the data to another entry when a cache hit occurs and when the value of the circulation delay counter corresponding to the entry holding the data indicates the lowest value; If a cache hit occurs and the entry corresponding to the data Reducing the value of the orbit delay counter when the value of the orbit delay counter indicates a value other than the minimum value. Wherein the new and old data held by the entry is represented by the following.