JPH1026044A - Timing pulse generating circuit for controlling engine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a timing pulse generating circuit for controlling an engine to further simply constitution. SOLUTION: In this timing pulse generating circuit 10 for controlling an engine to output corresponding timing pulses SA-SD in response to a plurality of pulse input signals S1-S2, the leading edge timings of pulse input signals S1-S2 are detected by a single leading edge detecting circuit 13 by utilizing a difference in a phase from each other. From a detecting leading edge timing, a plurality of constant width pulses having a given pulse width are generated, in order, by using a timer circuit 14. The constant width pulses are distributed and outputted as timing pulses SA-SD corresponding to respective pulse input signals by a pulse synthesizing output part 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an engine control timing pulse generating circuit.

[0002]

2. Description of the Related Art When electronically controlling an engine, a timing pulse generating circuit is required to operate various actuators and the like at appropriate timings according to the operating conditions. For example, there is a case where electronic control of the injection timing of fuel for fueling each cylinder of the engine is to be performed.

FIG. 8 shows an example of a conventional configuration of a drive circuit for a fuel injection valve when such control is performed. The drive circuit 100 is a shared drive circuit having a shared circuit portion for driving the solenoids SD1, SD2, SD3, and SD4 of four fuel injection valves for performing fuel injection for each cylinder of a four-cylinder engine (not shown). 101, and a timing pulse generation circuit 102 which receives drive signals S1, S2, S3, S4 of each fuel injection valve sent from a control computer (not shown).

[0004] The timing pulse generation circuit 102 has a structure shown in FIG.
As shown in detail, leading edge detection circuits 103A to 103A provided corresponding to the respective drive signals S1 to S4.
3D and these leading edge detection circuits 103A.
And 103D corresponding to 103D. Leading edge detection circuit 103A
To 103D detect the timing of the leading edge of the corresponding drive signal, and the timer circuits 104A to 104D respond to the timing of the leading edge detected by the corresponding leading edge detection unit to determine the predetermined pulse width T.
In this configuration, p pulses are output as timing pulses SA to SD.

[0005] Fuel injection to each cylinder of the engine is not usually performed simultaneously, but is performed with a predetermined phase difference. That is, as shown in FIG. 10, all of the drive signals S1 to S4 are output without overlapping each other, and the timing pulse SA having the pulse width Tp at each leading edge timing of the drive signals S1 to S4.
~ SD is output.

The timing pulses SA to SD output from the timing pulse generating circuit 102 are input to the shared driving circuit 101, and the corresponding solenoids SD1 to SD1 are used by utilizing the fact that these timing pulses SA to SD do not overlap. Timing pulses SA to SD for driving SD4 with a time difference are output.

[0007]

However, according to the conventional timing pulse generating circuit described above, a circuit having a similar function must be prepared by the number of input drive signals, so that the circuit becomes large-scale. As a result, there is a problem that the cost must be increased.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a timing pulse generating circuit for engine control having a simpler configuration.

[0009]

According to a first aspect of the present invention, there is provided a computer system comprising: a plurality of pulse input signals which respond to a plurality of non-overlapping pulse input signals having mutually different phases; An engine control timing pulse generating circuit for outputting a plurality of timing pulses having a pulse width of a predetermined time width from each leading edge timing of a signal, wherein each leading edge of the pulse input signal is responsive to the pulse input signal. A leading edge detection circuit for generating a first pulse train signal including a plurality of detection pulses each indicating a timing, and a predetermined pulse width from each leading edge timing indicated by the plurality of detection pulses in response to the first pulse train signal A second pulse train signal consisting of a plurality of fixed width pulses having A timer circuit for generating, and a pulse for distributing and outputting the plurality of constant width pulses as timing pulses corresponding to each of the plurality of pulse input signals in response to the second pulse train signal and the plurality of pulse input signals. And a combination output unit.

Since the plurality of pulse input signals have different phases and do not overlap with each other, they are sequentially input to a leading edge detection circuit to sequentially detect each leading edge timing of these pulse input signals. A first pulse train signal is output. The first pulse train signal is obtained as a series of detection pulses output at each leading edge timing of the pulse input signal. In the timer circuit, a plurality of constant width pulses are obtained in response to each detection pulse. The constant width pulse has information on the leading edge timing indicated by the corresponding detection pulse, and from the timer circuit, a plurality of constant width pulses having a pulse width for a certain time duration from each leading edge of the pulse input signal. Is obtained. Then, a plurality of fixed width pulses constituting the second pulse train signal are distributed and output as timing pulses in the pulse synthesis output section as timing pulses by referring to the pulse input signals.

A feature of the present invention is that a plurality of pulse input signals having a pulse width corresponding to a plurality of pulse input signals having phases different from each other and having a predetermined pulse width from each leading edge timing of the plurality of pulse input signals. In an engine control timing pulse generating circuit for outputting a timing pulse, a plurality of shortened pulse inputs which do not overlap with each other by shortening a pulse width without changing a phase difference between the plurality of pulse input signals. A conversion circuit for converting the signal into a plurality of signals, and a plurality of detection pulses responsive to the plurality of shortened pulse input signals and indicating respective leading edge timings of the plurality of shortened pulse input signals.
A leading edge detection circuit for generating a pulse train signal, and a second constant pulse having a predetermined pulse width in response to the first pulse train signal and having a predetermined pulse width from each leading edge timing indicated by the plurality of detection pulses. A timer circuit for generating a pulse train signal; and distributing the plurality of constant width pulses as timing pulses in response to the second pulse train signal and the plurality of pulse input signals, respectively, corresponding to each of the plurality of pulse input signals. And a pulse synthesizing output section for outputting.

The plurality of pulse input signals are converted by the conversion circuit into a plurality of shortened pulse input signals which are shortened only by their respective pulse widths while maintaining the same phase difference and do not overlap with each other. Thereafter, each leading edge timing of the plurality of shortened pulse input signals is sequentially detected by the leading edge detection circuit, and the first pulse train signal is output. The first pulse train signal is obtained as a series of detection pulses output at each leading edge timing of the pulse input signal. In the timer circuit,
A plurality of constant width pulses are obtained in response to each detection pulse. The constant width pulse has information on the leading edge timing indicated by the corresponding detection pulse,
From the timer circuit, a second pulse train signal composed of a plurality of pulses of a fixed width having a pulse width of a fixed time width is obtained from each leading edge of the pulse input signal. Then, in the pulse synthesizing output section, the constant-width pulse constituting the second pulse train signal is distributed and output as a timing pulse corresponding to each pulse input by referring to the pulse input signal.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of the first embodiment of the present invention. The timing pulse generating circuit 10 for engine control shown in FIG. 1 is a circuit suitable as a timing pulse generating circuit for the drive circuit of the fuel injection valve shown in FIG. Timing pulse generation circuit 10
Have four input signals S1 to S4 for controlling four fuel injectors for a four-cylinder engine.
1A to 11D. The following description is made with reference to the waveform diagrams of the signals of the respective parts of the timing pulse generation circuit 10 shown in FIG.

As can be seen from FIG. 2, these pulse input signals S1 to S4 are a plurality of pulse signals having mutually different phases and not overlapping. The timing pulse generation circuit 10 responds to the pulse input signals S1 to S4 to determine the timing T of each of the leading edges E1, E2, E3, E4,... Of these pulse input signals S1 to S4.
The timing pulses SA to SD having a pulse width of a predetermined time width Tp from 1, T2, T3, T4,.
The circuits are configured to output from the output terminals 12A to 12D, respectively.

In the timing pulse generation circuit 10,
Reference numeral 13 denotes each leading edge timing T of the pulse input signals S1 to S4 in response to the pulse input signals S1 to S4.
, A plurality of detection pulses KP1, KP2, KP3, KP4,... Indicating 1, T2, T3, T4,.
A leading edge detection circuit 14 for generating the pulse train signal PT1 responds to the first pulse train signal PT1 to detect pulses KP1, KP2, KP3, KP4,.
Each leading edge timing T indicated by
A predetermined pulse width Tp from 1, T2, T3, T4,.
A plurality of fixed width pulses HP1, HP2, HP3,
A timer circuit 15 for generating a second pulse train signal PT2 comprising HP4,.
In response to T2 and the pulse input signals S1 to S4, a plurality of constant-width pulses HP1, HP2, HP3, HP4,... Are output as timing pulses SA to SD corresponding to each of the pulse input signals S1 to S4. This is a pulse synthesis output unit that distributes and outputs the signal to 12D.

According to this configuration, the pulse input signals S1 to S1
Since S4 is a pulse signal having a different phase from each other and not overlapping, the two pulse input signals do not go into the high level state at the same time. Therefore, the pulse input signal S
1 to S4 are sequentially input to the leading edge detection circuit 13, whereby the leading edges E1, E2, E3, E4,... Of the pulse input signals S1 to S4 are sequentially detected, and the first pulse train having the waveform shown in FIG. The signal PT1 is output. The first pulse train signal PT1 is a pulse input signal S1
To S4, leading edge timings T1, T2,
Are obtained as a series of detection pulses KP1, KP2, KP3, KP4,... Outputted for each of T3, T4,. In the timer circuit 14, each detection pulse KP
In response to 1, KP2, KP3, KP4,..., A plurality of fixed width pulses HP1, HP2, HP3, HP4,.
・ Is obtained. Constant width pulses HP1, HP2, HP3,
HP4,... Can be obtained by using a timer circuit having a configuration in which the output level state is inverted for a certain time corresponding to the pulse width Tp in response to the detection pulse.

These fixed width pulses HP1, HP2, H
, P3, HP4,... Have information on the leading edge timing indicated by the corresponding detection pulse.
4, leading edges E1, E2, E3, E4,.
··· Four fixed-width pulses HP1, HP2, HP3, HP4 having a pulse width of a fixed time width Tp from.
, A second pulse train signal PT2 is obtained. Then, in the pulse synthesis output unit 15, the constant width pulses HP1, HP constituting the second pulse train signal PT2 are output.
2, HP3, HP4,... Are pulse input signals S1 to S
4 and distributed and output as timing pulses SA to SD.

In the above description, the pulse input signals S1 to S4
Has been described for one cycle, the pulse input signals S1 to S4 are usually input to this type of timing pulse generation circuit 10 at a predetermined repetition cycle with a predetermined phase difference. However, also in this case, the operation in the case of the above-described pulse input signals S1 to S4 for one cycle is merely repeated sequentially and sequentially.

FIG. 3 is a circuit diagram showing a more specific embodiment of the first embodiment of the present invention shown in FIG. The timing pulse generation circuit 10 'shown in FIG.
In the timing pulse generation circuit 10 shown in FIG.
The same reference numerals are given to the portions corresponding to the respective portions, and the description thereof will be omitted.

The leading edge detection circuit 13 is a four-input NOR to which pulse input signals S1 to S4 are input.
A pulse input signal S1 to S4
The input NOR gate 13A combines the signals into one signal,
A first pulse train signal PT1 is obtained. The waveform of the first pulse train signal PT1 is the same as that shown in FIG.

The timer circuit 14 includes resistors 14A and 14B
A reference voltage VR obtained by dividing the power supply voltage Vcc by a voltage comparator 14C applied to the + input terminal and a predetermined time Tp from the leading edge of the pulse from the 4-input NOR gate 13A in cooperation with the capacitor 13B. When the time elapses, a voltage of the same level as the reference voltage VR is supplied to the capacitor 13.
And a resistor 14D for generating a voltage at the terminal B, which are connected as shown in FIG.

As a result, a constant width pulse having a pulse width Tp is output from the output of the voltage comparator 14C at each leading edge timing of the pulse input signals S1 to S4.

The pulse synthesis output section 15 has four AND gates 15A to 15A corresponding to the pulse input signals S1 to S4.
D, a constant-width pulse from the timer circuit 14 is commonly input to one of the input terminals, and a corresponding one of the pulse input signals S1 to S4 is input to each of the other input terminals. I have. Therefore, AND gate 1
From each of 5A to 15D, a constant width pulse output when the corresponding pulse input signal is in the high level state is output to the corresponding output terminal as a timing pulse. As described above, the leading edge detection circuit 1 responds to the four pulse input signals S1 to S4.
Since only one set of the timer circuit 3 and the timer circuit 14 needs to be provided, the circuit can be simplified and the cost can be reduced.

In the case of a four-cylinder four-cycle direct injection engine, the fuel injection timing is limited to the intake stroke or the compression stroke. Therefore, as shown in FIG.
In the case where the four strokes of intake, compression, explosion, and exhaust are sequentially executed with a phase difference of 180 ° at the crankshaft angle of 0 ° to 720 ° in the four cylinders K1 to K3, the intake and compression strokes for each cylinder are determined. The pulse input signals to be shown overlap, and there may be a case where two pulse input signals are simultaneously in the high level state. In such a case, the timing pulse generation circuits 10 and 1 shown in FIGS.
When the value is 0 ', each leading edge timing of the pulse input signal cannot be detected by the leading edge detection circuit 13.

FIG. 5 shows a timing pulse generating circuit which can be used for controlling a fuel injection valve in an internal combustion engine having the operation timing as shown in FIG. The timing pulse generating circuit 20 shown in FIG. 5 shows an example of the embodiment of the second aspect of the present invention. The timing pulse generation circuit 20 receives four pulse input signals S11 to S14 from input terminals 11A to 11D for controlling four fuel injection valves for a four-cylinder engine. The following description is made with reference to the waveform diagrams of the signals of the respective parts of the timing pulse generation circuit 20 shown in FIG.

These pulse input signals S11 to S14
6 is the same as the pulse input signals S1 to S4 shown in FIG. 2 in that the phases are different from each other, as shown in FIG. 6, but in that two adjacent pulse input signals overlap. It is different from the pulse input signals S1 to S4. The timing pulse generation circuit 20 also has the pulse input signals S11 to S14.
In response to each of the leading edges E10, E20, E30, E40,
E11,... Timings T10, T20, T30,
Are configured as circuits for outputting timing pulses SA to SD having a pulse width of a predetermined time width Tp from T40, T11,... From corresponding output terminals 12A to 12D, respectively.

The timing pulse generation circuit 20 shortens the pulse width of the pulse input signals S11 to S14 without changing the phase difference between them and converts them into a plurality of shortened pulse input signals which do not overlap with each other. Conversion circuit 21
It has. In the present embodiment, the conversion circuit 21
The pulse input signals S11 and S13, which have a shortening circuit 21A and a second shortening circuit 21B and do not overlap each other, are input to the first shortening circuit 21A to reduce the pulse width, and the first shortened pulse input is performed. The signal S113 is output. On the other hand, another set of pulse input signals S12 and S14 which do not overlap each other is input to the second shortening circuit 21B to reduce the pulse width, and the second shortened pulse input signal S12
4 is output.

First shortening circuit 21A and second shortening circuit 21
B is provided with a timer function, and the pulse width is shortened as follows. As shown in FIG. 6, assuming that the minimum interval of the leading edge between the pulse input signals is Tc and the fixed pulse width of the timing pulse is Tp, the first and second shortened pulse input signals S1
13. The pulse width Tr in S124 may be determined so as to satisfy Tp <Tr <Tc. Here, Tp is a constant value, and Tc changes depending on the rotation speed of the engine. Therefore, the value of Tr should be smaller than the value of Tc at the maximum rotation speed of the engine and larger than Tp. Such time management does not need to be an accurate timer, and therefore, it is possible to assemble the first shortening circuit 21A and the second shortening circuit 21B using inexpensive parts with low accuracy.

In response to the pulse input signals S11 and S13, a pulse having a constant width of time Tr is generated from the leading edges E10 and E30 to obtain a first shortened pulse input signal S113 as shown in FIG. The circuit configuration itself of the first shortening circuit 21A can be easily realized by using the circuit configuration of the leading edge detection circuit 13 and the timer circuit 14 shown in FIG. Second shortening circuit 21
The same applies to the configuration of B.

As can be seen from FIG. 6, the first shortened pulse input signal S113 and the second shortened pulse input signal S124 obtained as a result of shortening the pulse width by the conversion circuit 21 are:
The pulse signal has information on the leading edge timing of the pulse input signals S11 to S14 and does not overlap.

The first shortened pulse input signal S113 and the second
The shortened pulse input signal S124 is input to the leading edge detection circuit 22, where the leading edge timing of each pulse included in the first shortened pulse input signal S113 and the second shortened pulse input signal S124, that is, the timing T10, T20, T30, and T40 are detected in the same manner as in the leading edge detection circuit 13 of FIG. Next, the second pulse train signal PT2 is obtained in the timer circuit 23 in the same manner as in the case of the timing pulse generation circuit 10 shown in FIG.

The pulse synthesizing output unit 24 also performs a timing pulse distribution output operation in the same manner as the pulse synthesizing output unit 15 shown in FIG. 1, and outputs the output terminals 12A to 12D.
Output timing pulses SA to SD.

In the case of the circuit configuration shown in FIG. 5, the number of timers used is different from that of the conventional circuit configuration shown in FIG. Therefore, there is an advantage that the circuit scale is small and the cost can be reduced because time management can be rough. That is, each of the circuit configurations shown in FIGS. 1, 3, and 5 has an advantage that only one timer requiring strict time management is required.

FIG. 7 is a circuit diagram showing a more specific embodiment of the timing pulse generation circuit 20 shown in FIG. When the pulse input signals S11 to S14 shown in FIG. 6 are input to the input terminals 31A to 31D, the timing pulse generation circuit 30 shown in FIG. It has a circuit configuration capable of obtaining SA to SD. The same reference numerals are given to the portions corresponding to the respective portions in FIG. 5 among the respective portions in FIG. 7, and the description thereof will be omitted.

In the timing pulse generation circuit 30, the pulse input signals S11 to S14 are processed after their levels are inverted by the corresponding inverters 33A to 33D. The first shortening circuit 21A includes an OR circuit including diodes D1 and D2, and a differentiating circuit including resistors R1 and R2 and a capacitor C1 for differentiating the output from the OR circuit. A signal having only a reduced pulse width can be obtained without changing the leading edge timing of the input signals S11 and S13. The second shortening circuit 21B has the same configuration.

The circuit configurations of the leading edge detection circuit 22 and the timer circuit 23 are substantially the same as the circuit configurations of the leading edge detection circuit 13 and the timer circuit 14 shown in FIG. 3, so that detailed description thereof will be omitted. As the pulse synthesis output 24, three-input NAND gates 24A to 24D are used, and in the NAND gates 24A and 24C, the output from the first shortening circuit 21A is also considered.
The NAND gates 24B and 24D differ from the configuration of the pulse synthesizing output unit of the timing pulse generating circuit described above in that the output from the second shortening circuit 21B is also considered.

[0038]

According to the present invention, as described above, only one timer circuit requiring strict time management need be used and shared, so that the circuit scale can be reduced and the cost can be reduced. Can be planned.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of an embodiment of a timing pulse generation circuit according to the present invention.

FIG. 2 is a timing chart showing waveforms of signals of respective units for explaining the operation of the timing pulse generation circuit shown in FIG. 1;

FIG. 3 is a circuit diagram showing a more specific embodiment of the timing pulse generation circuit shown in FIG. 1;

FIG. 4 is a diagram showing the operation timing of each cylinder of a four-cylinder four-cycle engine.

FIG. 5 is a block diagram showing an example of an embodiment of a timing pulse generation circuit according to the invention of claim 2;

6 is a timing chart showing waveforms of signals of respective parts for explaining the operation of the timing pulse generation circuit shown in FIG. 5;

FIG. 7 is a circuit diagram showing an example of a more specific embodiment of the timing pulse generation circuit shown in FIG. 5;

FIG. 8 is a block diagram showing a configuration of a conventional fuel injection valve drive circuit configured using a timing generation circuit.

9 is a detailed block diagram showing a conventional configuration example of the timing pulse generation circuit shown in FIG.

FIG. 10 is a timing chart showing waveforms of signals of respective sections for explaining the operation of the timing pulse generation circuit shown in FIG. 9;

[Explanation of symbols]

10, 10 ', 20, 30 Timing pulse generation circuit 13, 22 Leading edge detection circuit 14, 23 Timer circuit 15, 24 Pulse synthesis output unit 21 Conversion circuit 21A First shortening circuit E1-E4, E10, E20, E30, E40 , E11
Leading edge PT1 First pulse train signal PT2 Second pulse train signal S1 to S4, S11 to S14 Pulse input signal SA to SD Timing pulse T1 to T4 T10, T20, T30, T40, T11
Leading edge timing

Claims (2)

[Claims] A plurality of timings responding to a plurality of non-overlapping pulse input signals having phases different from each other and having a pulse width of a predetermined time width from each leading edge timing of the plurality of pulse input signals. An engine control timing pulse generating circuit for outputting a pulse, comprising: a reading circuit for generating a first pulse train signal including a plurality of detection pulses respectively indicating respective leading edge timings of the pulse input signal in response to the pulse input signal. An edge detection circuit, a second pulse comprising a plurality of constant width pulses having a predetermined pulse width from respective leading edge timings indicated by the plurality of detection pulses in response to the first pulse train signal;
A timer circuit for generating a pulse train signal; and distributing the plurality of constant width pulses as timing pulses in response to the second pulse train signal and the plurality of pulse input signals, respectively, corresponding to each of the plurality of pulse input signals. An engine control timing pulse generating circuit, comprising: a pulse synthesizing output unit for outputting. 2. A method for responding to a plurality of pulse input signals having mutually different phases and outputting a plurality of timing pulses having a pulse width of a predetermined time width from each leading edge timing of the plurality of pulse input signals. In the engine control timing pulse generating circuit, a conversion for converting the plurality of pulse input signals into a plurality of shortened pulse input signals which do not overlap with each other by reducing a pulse width without changing a phase difference between the plurality of pulse input signals. A leading edge detection circuit for generating a first pulse train signal including a plurality of detection pulses respectively indicating leading edge timings of the plurality of shortened pulse input signals in response to the plurality of shortened pulse input signals; Each lead responsive to the first pulse train signal and indicated by the plurality of detection pulses A timer circuit for generating a second pulse train signal composed of a plurality of constant width pulses having a predetermined pulse width from the edge timing; and the plurality of constant pulses in response to the second pulse train signal and the plurality of pulse input signals. A pulse synthesis output unit for distributing and outputting a width pulse as a timing pulse corresponding to each of the plurality of pulse input signals.