JPH10257507A - Video camera with still camera - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video camera with a still camera to obtain a still image with high resolution. SOLUTION: A spatial sampling position of an image pickup element 18 is deviated by a half pixel pitch in an oblique direction with respect to a spatial sampling position of an image pickup element 20 and image pickup elements 16, 18, 22 are placed at the same sampling position. A control circuit 84 supplies a control signal 108 to an image pickup part 10 to transfer the signals of the even and odd number of lines from horizontal registers for each of the even and odd number of lines for one line period. The signal from each of the horizontal registers is converted into a digital signal, is sent and stored in a 1st memory of an image memory 64. An arithmetic circuit of the memory 64 applies interpolation processing to data G1, G2 from the 1st memory to obtain green (G) data for the interpolation and stores the data G1, G2 from the 1st memory and the G data from the arithmetic circuit to a prescribed position of the 2nd memory of the memory 64 in the unit of a half pixel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention more specifically relates to
For example, the present invention relates to a video camera with a still camera that has a still camera function of recording a still image for each frame on a memory card or the like and a video camera function of recording a moving image on a video tape or the like, and can perform still shooting and video shooting. More particularly, the present invention relates to a video camera with a still camera suitable for obtaining a high-resolution (high-definition) still image in still photography.

[0002]

2. Description of the Related Art In recent years, a video-integrated camera capable of simultaneously taking a still image (electronic still image) at a photo opportunity while taking a moving image (video) has been proposed.
A camera that can selectively switch between a moving image and a still image for shooting has also been proposed.

The still camera section of such a camera is generally configured as shown in FIG. That is, the optical image of the subject that has passed through the imaging lens 300 is
R (red), G (green), B with 302 color separation prism 304
After being decomposed into each color component of (blue), an image is formed on the solid-state imaging elements 306, 308, and 310 (three-plate type) of the solid-state imaging unit 302 and converted into image signals. Here, the relationship between the pixel positions of the solid-state imaging devices 306, 308, and 310 is as shown in FIG. Image signals R, G, B output from each solid-state image sensor 306, 308, 310
Are amplified to a predetermined level by the signal processing unit 312 to adjust the white balance, and further subjected to non-linear processing such as gamma correction. The image signals R, G, and B output from the signal processing unit 312 are analog-to-digital (A / D) converters.
The digital signals are converted into corresponding digital signals by 314 and sent to the frame memory 316 to be temporarily stored. The image data R, G, and B once stored are sent to the memory card 318 and recorded as still image data.

[0004]

However, the solid-state imaging devices 306, 308 and 310 basically have the same number of pixels. Therefore, the resolution of the still image formed by the solid-state imaging device is determined by the number of pixels of the solid-state imaging device. In order to obtain a higher resolution, the number of pixels of the solid-state imaging device must be increased.

The present invention solves the above-mentioned drawbacks of the prior art. Even when a plurality of solid-state imaging devices having the same number of pixels are used, a still image having a higher resolution than the resolution determined by the number of pixels of the solid-state imaging device is obtained. It is an object to provide a video camera with a still camera that can be obtained.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention captures an image of a subject by an image capturing means to obtain image data of a still image, captures an image of the subject by the image capturing means, and obtains a moving image of the moving image. In a video camera with a still camera that obtains image data, an imaging unit receives a red imaging light among the imaging light and forms and outputs a red image signal, and a green solid imaging device among the imaging light. A first solid-state image sensor for green which receives light and forms and outputs a first green image signal; and receives green image-forming light among the image-forming light and forms and outputs a second green image signal. A first solid-state imaging device for blue, which includes a second solid-state imaging device for green, and a solid-state imaging device for blue that receives blue imaging light among the imaging light and forms and outputs a blue image signal; At the spatial sampling position of The spatial sampling position of the second green solid-state imaging device is shifted obliquely by a half pixel pitch, and the red solid-state imaging device, the second green solid-state imaging device, and the blue The solid-state imaging device means is at the same spatial sampling position.

The above-described solid-state image pickup device for red of the present invention includes a horizontal transfer register for red even-numbered lines for transferring red image signals of even lines, and a horizontal transfer for red-odd lines for transferring red image signals of odd lines. Register means, wherein the first solid-state image pickup device means for first green transfers a green image signal of an even-numbered line, and a first transfer register means for transferring a green image signal of an odd-numbered line. A horizontal transfer register for green and odd lines; a second solid-state imaging device for green for transferring green image signals for even lines; and a horizontal transfer register for green lines for even green lines, and a green image signal for odd lines. And second horizontal transfer register means for odd-numbered green lines,
The blue solid-state imaging device includes a blue even-numbered line horizontal transfer register for transferring even-numbered blue image signals, and a blue odd-numbered horizontal transfer register for transferring odd-numbered blue image signals. I do.

The camera according to the present invention further includes control means for controlling the image pickup means. The control means supplies a control signal for reading out to the image pickup means to supply a horizontal transfer register for each color even number line. Means for transferring each color image signal of each pixel of the even line and the odd line from the horizontal transfer register for the odd line of each color in a predetermined one line period, the horizontal transfer register for the even line of each color, and the horizontal transfer register for the odd line of each color It is characterized in that the means transfers each color image signal of each pixel of an even line and an odd line for one screen in a predetermined one frame period.

Further, the above-mentioned camera of the present invention further comprises a red signal conversion means for converting a red image signal output from the red even number line and red odd line horizontal transfer register means into a corresponding digital signal and outputting the same. And the first
A first green signal converting means for converting a first green image signal output from the green even line and first green odd line horizontal transfer register means into a corresponding digital signal and outputting the digital signal; Green even line and second
A second green signal converting means for converting the second green image signal output from the green odd line horizontal transfer register means into a corresponding digital signal and outputting the digital signal, and a blue horizontal line for even and blue odd lines A blue signal converting means for converting a blue image signal output from the transfer register means into a corresponding digital signal and outputting the digital signal, wherein the control means is further connected to the signal converting means for each color, and the control means is provided for each color. The signal conversion means for converting the signal into a digital signal.

The above-mentioned camera of the present invention further comprises a red signal conversion means for converting a red image signal output from the horizontal transfer register means for red even number lines and a red odd number line into corresponding digital signals and outputting the same. And the first
A first green signal converting means for converting a first green image signal output from the green even line and first green odd line horizontal transfer register means into a corresponding digital signal and outputting the digital signal; Green even line and second
A second green signal converting means for converting the second green image signal output from the green odd line horizontal transfer register means into a corresponding digital signal and outputting the digital signal, and a blue horizontal line for even and blue odd lines A blue signal converting means for converting a blue image signal output from the transfer register means into a corresponding digital signal and outputting the digital signal, wherein the control means is further connected to the signal converting means for each color, and the control means is provided for each color. The signal conversion means for converting the signal into a digital signal.

Further, the above-mentioned camera of the present invention further comprises a first red storage means for storing red image data digitized by the red signal conversion means, and a digitalization by the first green signal conversion means. First green storage means for storing the converted first green image data, and second green storage means for storing the second green image data digitized by the second green signal conversion means. And a first blue storage means for storing blue image data digitized by the blue signal conversion means.

Further, the above-mentioned camera of the present invention further performs an interpolation process on the first and second green image data read from the first and second green storage means, and performs a third interpolation. A first interpolation unit for obtaining green image data, wherein the first and second green image data are divided by 1 / in the horizontal and vertical directions;
The third green image data is arranged at a pitch of one pixel with a width of two pixels, and the third green image data is horizontal to the first and second green image data.
It is characterized by a half pixel width shifted by a half pixel pitch in the vertical direction.

Further, the camera of the present invention described above further comprises a first green storage means, a second green storage means and a first green storage means.
A third green storage means for storing each color image data output from the interpolation means in units of 1/2 pixel, and the camera comprises a first red storage means and a first blue storage means. Each color image data stored in the third green storage means is used as still image data.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a video camera with a still camera according to the present invention will be described in detail with reference to the accompanying drawings.

Details of the video camera with a still camera are shown in the functional block diagrams of FIGS. 1 and 2 combined as shown in FIG. The video camera with a still camera shown in FIGS. 1 and 2 can record digital image data of a moving image on the magnetic tape 54 and reproduce digital image data of the moving image recorded on the magnetic tape 54. Further, in the video camera with a still camera shown in FIGS. 1 and 2, digital image data of a still image can be recorded on a memory 72 (memory card or the like) in addition to recording and reproducing a moving image.

In this embodiment, an existing standard industry standard used in a digital video tape recorder (DVTR) is used as a recording system on the magnetic tape 54. This will be described below.

FIG. 25 shows a track Tr of the magnetic tape 54. Referring to FIG. 7, a large number of tracks Tr are shown at a fixed angle obliquely to the longitudinal direction of the magnetic tape 54. Consecutive of these many tracks Tr
One frame of image data is recorded on ten tracks.

FIG. 26 also shows the format of the track. One track Tr includes a subcode recording area, a video recording area, an auxiliary recording area, an audio recording area, and a track information recording area. Information such as time code and absolute track number for high-speed search is recorded in the subcode recording area, image data representing the subject image is recorded in the video recording area, and audio data representing sound is recorded in the audio recording area. Information is recorded in the track information recording area, which is a reference of the track Tr for the magnetic head to trace the center of the track Tr.
The auxiliary recording area is provided at intervals, and additional information is recorded in the auxiliary recording area. Although gaps are provided between the respective regions, they are omitted in FIG.

Returning to FIGS. 1 and 2, the video camera with a still camera includes a solid-state imaging unit 10, signal processing units 24 and 32, an analog / digital (A / D) converter 26, an interpolation / synthesis circuit 28, and a frame memory 30. , 34, shuffling / deshuffling circuit
36, image memories 38, 44, 62, 64, compression / expansion circuit 40, error correction code addition / error correction circuit 42, modulator / demodulator 46, recording / playback amplifier 48, waveform equalizer 50, magnetic head 52, magnetic tape 5
4, changeover switches 56, 70, digital / analog (D / A) converter 58, monitor device 60, orthogonal conversion circuit 66, lookup table (LUT) 67, encoding circuit 68, memory 72, operation unit 74
And a control circuit 84. Other parts of the camera not directly related to the present invention, such as a mechanism for focusing, are omitted.

The solid-state imaging unit 10 includes an imaging lens 12, a color separation prism 14, a solid-state imaging device 16 for R, and a solid-state imaging device 1 for G2.
8. Solid-state image sensor 20 for G1 and solid-state image sensor 22 for B
It is composed of

Solid-state image sensors 16, 18, 20 and 22 (four-plate type)
Has a 1/60 second non-interlaced all-pixel readout CCD
Image sensor (Progressive-Scan CCD Image Sensor or less PS-C
CD) is advantageously applied. The PS-CCD adopts the same non-interlace method as the computer scanning method.
Since PS-CCD handles twice as much information independently at one time,
Vertical CCD structure and Dual-Channel horizontal CC
The D structure (see FIG. 4) is employed.

More specifically, the PS-CCD is capable of simultaneously and independently outputting data of two horizontal lines, that is, an even line and an odd line adjacent to the even line during one horizontal period. Also, data of one frame can be read in one frame period by reading out the even numbered lines and the odd numbered lines in the order of the youngest number. In this example, the effective number of pixels of the PS-CCD is 720 horizontal pixels and 480 vertical pixels, the horizontal driving frequency is 13.5 MHz, and the frame driving frequency is 60 Hz.

In this embodiment, the solid-state image pickup device 18 for G2 and G1
The relationship between the pixel positions of the solid-state imaging device 20 is arranged at a position optically obliquely shifted by a half pixel as shown in FIG.
G2 solid-state image sensor 18, R solid-state image sensor 16 and B
As shown in FIG. 6, the pixel positions of the solid-state image sensor 22 are optically arranged at the same position. As described above, the pixel positions of the solid-state imaging device 18 for G2 and the solid-state imaging device 20 for G1 have a positional relationship of being shifted by a half pixel in the oblique direction.
Both are solid-state imaging devices that output G-component image signals.

By the way, the optical image of the object which has passed through the imaging lens 12 is R (red), G2 (green),
It is decomposed into G1 (green) and B (blue) color components. The R component is imaged on the solid-state imaging device 16 and converted into an image signal, and the G2 component is imaged on the solid-state imaging device 18 and converted into an image signal.
The G1 component is imaged on the solid-state imaging device 20 and converted into an image signal, and the B component is imaged on the solid-state imaging device 22 and converted into an image signal.

More specifically, an image signal of an even-numbered line of the R component is output from an output 100, and an image signal of an odd-numbered line of the R component is output from an output 101. Similarly, the image signal of the even line of the G2 component is output from the output 102, the image signal of the odd line of the G2 component is output from the output 103, the image signal of the even line of the G1 component is output from the output 104, and the G1 component is output. The image signal of the odd-numbered line is output from the output 105, the image signal of the even-numbered line of the B component is output from the output 106, and the image signal of the odd-numbered line of the B component is output from the output 107.
Such control is performed by a control signal transmitted from the control circuit 84.
108. Output 100, 101, 102, 103, 104, 105,
106 and 107 are connected to corresponding inputs of the signal processing unit 24, respectively.

The signal processing section 24 receives inputs 100, 101, 102, 103, 104, and 100 based on a gain control signal input from a control input 118.
Image signals of even line R, odd line R, even line G2, odd line G2, even line G1, odd line G1, even line B and odd line B input from 105, 106 and 107 To a predetermined level.

The signal processor 24 also performs necessary image signal processing such as white balance adjustment and γ correction on the amplified color component signals. The image of the R of the even line, the R of the odd line, the G2 of the even line, the G2 of the odd line, the G1 of the even line, the G1 of the odd line, the B of the even line, and the B of the odd line thus subjected to the signal processing. The signals are output at outputs 110, 111, 112, 113, 114, 115, 116 and 117, respectively. Outputs 110, 111, 112, 113, 114, 115, 116 and 117
Are connected to corresponding inputs of the A / D converter 26, respectively.

The A / D converter 26 receives 13.5
Input 110, 111, 112, 113,
The analog image signals input from 114, 115, 116 and 117 are sampled, converted into corresponding digital data of, for example, 8 bits, and output 120, 121, 122, 123, 124,
It is a signal conversion circuit for outputting to 125, 126 and 127. A /
Sampling pulses required for D conversion are supplied from the control circuit 84 via a control line 128.

Outputs 122, 123, 124 and 125 are connected to corresponding inputs of the interpolation and synthesis circuit 28, outputs 120, 121, 126 and 127 are connected to corresponding inputs of the frame memory 30 and the image memory 62, and the outputs 120 , 121, 122, 123, 124, 125, 126
And 127 are connected to corresponding inputs of the image memory 64.

When viewed in units of one frame, outputs 120 and 121
Outputs image data of the R component as shown in FIG. 7, output 122 and 123 output image data of the G2 component as shown in FIG. 8, and outputs 124 and 125 output the image data as shown in FIG. The image data of the G1 component is output, and the image data of the B component as shown in FIG.

[0031] In FIG. 7, the subscript numerals of R image data obtained from the red light-receiving element, based on the R ₀₀ of the image data obtained from the red light receiving elements on the left side at the top of the figure, The image data obtained from the light receiving element at the position of each light receiving element corresponding to the vertical scanning direction m (m = 0 to 479 in this example) and the horizontal scanning direction n (n = 0 to 719 in this example) is shown. The same can be said for FIGS. 8 to 10.

The interpolation / synthesis circuit 28 adds the G2 image data value of the even line input from the input 122 and the G1 image data value of the even line input from the input 124, and adds the data value obtained by the addition to two. , And the data value obtained by this division is output as G data of an even line.
This is an arithmetic circuit that outputs the result.

The interpolation / synthesis circuit 28 also adds the odd line G2 image data value input from the input 123 to the odd line G1 image data value input from the input 125, and obtains the data value obtained by the addition. Is divided by 2 and the data value obtained by this division is output to the output 131 as G data of the odd line. Control signals and the like necessary for the operation are supplied from the control circuit 84 via a control line 134. Outputs 130 and 131 are connected to corresponding inputs of frame memory 30 and image memory 62. The equation for calculating the data of G _mn is shown in equation (1).

G _mn = (G2 _mn + G1 _mn ) / 2 (1) When viewed in units of one frame, the output 130 and 131 output G component image data as shown in FIG. Stored in the memory 30.

In this example, the frame memory 30 is constituted by a RAM having a storage capacity for temporarily storing at least one frame of R, G, and B image data. A / D converter
The R data 120, 121 from 26 is written to the R frame memory. Similarly, the B data 126 and 127 from the A / D converter 26 are written to the B frame memory, and the G data 130 and 131 from the interpolation and synthesis circuit 28 are written to the G frame memory.

In this example, the image data for one frame stored in the R frame memory is stored as shown in FIG.
One frame of image data stored in the frame memory is stored as shown in FIG. 11, and one frame of image data stored in the B frame memory is stored as shown in FIG.

In order to form data corresponding to the even and odd fields of R, G, and B from the data of R, G, and B thus accumulated, the following reading is performed. When forming data corresponding to an even-numbered field, image data of an odd-numbered line next to the even-numbered line is read out in parallel with reading of the image data of the even-numbered line. This operation is performed in the order of the even-numbered lines up to the last even-numbered line.

When data corresponding to an odd-numbered field is formed, image data of an even-numbered line next to the odd-numbered line is read out in parallel with the image data of the odd-numbered line. This operation is performed in the order of the odd-numbered lines up to the last odd-numbered line.

In this case, in this example, after the reading of the data for the even field is completed, the reading of the data for the odd field is performed. In the case of a moving image, this operation is repeatedly performed. The period of one field is 1/60 second.

The R, G, B image data of the above even lines is output.
R, G, B image data of odd lines are output from outputs 137, 139, 141. In this case, a control signal including an address and a clock used for writing and reading is supplied from the control circuit 84 through a control line 142. Outputs 136, 137, 138, 139, 140 and 141 are connected to corresponding inputs of signal processor 32.

The signal processing section 32 comprises an R operation circuit, a G operation circuit, a B operation circuit, and a matrix circuit (all not shown). The R arithmetic circuit adds the R image data value of the even line input from the input 136 and the R image data value of the odd line input from the input 137,
An arithmetic circuit that outputs the data value obtained by the addition to the matrix circuit as R data for an even field or an odd field.

The arithmetic circuit for G adds the image data value of the even-numbered line input from the input 138 to the image data value of the odd-numbered line input from the input 139, and calculates the data value obtained by the addition. This is an arithmetic circuit that outputs G data for an even field or an odd field to a matrix circuit.

The arithmetic circuit for B adds the image data value of the even line inputted from the input 140 to the image data of the odd line inputted from the input 141, and calculates the data value obtained by the addition. This is an arithmetic circuit that outputs B data for an even field or an odd field to a matrix circuit.

In this case, during the period in which the data corresponding to the even field is read from the field memory 30, the obtained data for the even field is supplied to the matrix circuit, and the data corresponding to the odd field is read from the field memory 30. During the operation, the obtained data for the odd field is supplied to the matrix circuit.

Since the number of lines in one frame is 480 as described above, the number of lines in each field output from the arithmetic circuit is 240.

In this example, the matrix circuit multiplies the R image data value output from the R operation circuit by 0.3 to obtain 0.3 ·
The R value is obtained, and the G image data value output from the G operation circuit is multiplied by 0.59 to obtain 0.59 · G value. The B image data value output from the B operation circuit is multiplied by 0.11 to obtain 0.11 · G. An arithmetic circuit for calculating the B value, adding the obtained data values, and outputting the data value obtained by the addition to the output 144 as Y (luminance) data for an even field or an odd field. The equation for calculating the Y data is shown in equation (2).

Y _mn = 0.3 · R _mn + 0.59G _mn + 0.11B _mn (2) The matrix circuit calculates the Y data value obtained by the above calculation from the R image data value output from the R operation circuit. And outputs the data value obtained by the subtraction to the output 146 as data of the color difference signal RY for the even field or the odd field. Equation (3) shows the equation for calculating the RY data.

(RY) _mn = R _mn -Y _mn (3) The matrix circuit subtracts the Y data value obtained by the above operation from the B image data value output from the B operation circuit, and subtracts the result. Is an arithmetic circuit for outputting the data value obtained by the above to the output 148 as data of the color difference signal BY for the even field or the odd field. Equation (4) shows the formula for calculating the BY data.

(BY) _mn = B _mn -Y _mn (4) The control signal and the like necessary for the above operation are sent from the control circuit 84 to the control line.
Supplied via 150. Outputs 144, 146 and 148 are connected to corresponding inputs of frame memory 34.

In this example, the frame memory 34 is composed of frame memories for Y, RY and BY. These frame memories are composed of RAM having a storage capacity for temporarily storing at least one frame of image data. The Y data from the matrix circuit is stored in the Y frame memory.
4 is written for each field, RY data 146 from the matrix circuit is written to the frame memory for RY for each field, and BY data 148 from the matrix circuit is written to the frame memory for BY for each field.

In this case, the image data for one frame stored in the frame memory for Y is stored as shown in FIG. 12, and the image data for one frame stored in the frame memory for RY is as shown in FIG. The image data for one frame stored in the frame memory for BY is
Is accumulated as follows. As shown by the x mark in FIGS. 13 and 14, the RY and BY data in the odd columns are thinned out. Therefore, the number of pixels in the horizontal direction for one frame of RY and BY is 360, and the number of pixels in the vertical direction is 480. Further, since Y is not thinned out, the number of pixels in the horizontal direction for one frame of Y is 720 and the number of pixels in the vertical direction is 480.

The image data thus accumulated is Y, RY,
They are read out in the order of BY and output to the output 152. Control signals and the like necessary for the above-mentioned writing and reading are supplied from a control circuit 84 via a control line 154. The output 152 is connected to a corresponding input of the shuffling / deshuffling circuit 36 and the changeover switch 56.

When the moving image recording mode is set, the changeover switch 56 turns “ON” between the input 152 and the output 182, and
Turn OFF between 58 and output 182. Selector switch 56
Is set to “OFF” between input 152 and output 182 and “ON” between input 158 and output 182 when the video playback mode is set.
I do. The control signal for performing the switching in this way is a control line.
It is sent from the control circuit 84 through 186. Output 182 is
It is connected to a D / A converter 58.

The image data read from the frame memory 34 is supplied to a shuffling / deshuffling circuit 36. The image data read from the frame memory 34 is supplied to a D / A converter 58 via a changeover switch 56.
The digital image data is converted into an analog video signal 184 in the D / A converter 58. The analog video signal 184 is provided to the monitor device 60 to display a subject image. Thus, the subject being photographed is confirmed.

By the way, a digital video tape
In a recorder (DVTR), 8 pixels x 8 for one field
It is divided into DCT (Discrete Cosine Transform) blocks of pixels. FIG. 15 shows how Y data is divided, FIG. 16 shows how RY data is divided, and FIG. 17 shows how BY data is divided.
Shown in

Then, one macro block is composed of four DCT blocks for Y, two DCT blocks for RY, and two DCT blocks for BY. That is, the DCT block includes four DCT blocks for Y and two DCT blocks for RY and BY at the same position on the screen as the four DCT blocks. For example, YDCT ₀₀ for Y, YDC
Four blocks of T ₀₁ , YDCT ₁₀ and YDCT ₁₁ , two blocks of R-YDCT ₀₀ and R-YDCT ₁₀ for RY, and two blocks of B-YDCT ₀₀ and B-YDCT ₁₀ for BY One macro block is formed from the block and the block.

Further, one super block is formed from 27 macro blocks, five macro blocks are extracted from different super blocks, and the extracted five macro blocks (hereinafter referred to as a group). Is compressed so that the data amount of the image data representing the image data becomes a predetermined data amount.

A circuit for performing the above-described DCT block generation processing, macro block generation processing, super block generation processing, and group generation processing is a shuffling / deshuffling circuit 36.

The shuffling / deshuffling circuit 36 performs the above-described processing on the image data input from the input 152 and outputs it to the output 154. The output 154 is connected to the input of the image memory 38.

The image memory 38 is composed of a RAM having a storage capacity for temporarily storing image data for one frame, and stores image data input from the input 154 in units of macro blocks. The image data thus accumulated is read out in groups and output to the output 159. The output 159 is connected to the compression / expansion circuit 40.

The compression / expansion circuit 40 is a compression circuit that performs data compression on image data in a group unit input from the input 159 so as to have a predetermined data amount and outputs the data to an output 162. The output 162 is connected to the error correction code addition / error correction circuit 42. The compressed image data passes through the signal line 162, the error correction code addition / error correction circuit 42 and the signal line 170, is given to the image memory 44, and is temporarily stored.

The compressed image data is read from the image memory 44 and supplied to the error correction code addition / error correction circuit 42. The error correction code addition / error correction circuit 42 has an input 170
And an error correction code adding circuit for generating an error correction code for the image data input from the CPU, adding the generated error correction code to the input image data, and outputting to the output 166. The output 166 is connected to the modem 46.

The modulator / demodulator 46 is a modulation circuit for performing a predetermined modulation based on the image data to which an error correction code is input from an input 166 and outputting the modulated signal to an output 172. The output 172 is connected to the recording / reproducing amplifier 48.

The recording / reproducing amplifier 48 is a circuit for amplifying the modulation signal input from the input 172 to a predetermined level and sending the amplified signal to the magnetic head 52. The magnetic head 52, modulated image data is recorded in the video recording area A ₂ of the magnetic tape 54.

[0065] When the moving image reproduction mode is set, modulating the image data recorded in the video recording area A ₂ of the magnetic tape 54 is read by the magnetic head 52 recording and reproduction amplifier 48
Sent to The recording / reproducing amplifier 48 amplifies the modulated image data read by the magnetic head 52 to a predetermined level, and transmits the modulated image data to the modem 46 through the signal line 174 and to the signal line 180.
To the waveform equalizer 50.

The waveform equalizer 50 generates a control signal for equalizing the waveform of the input modulated image data based on the modulated image data input from the input 180, and sends the control signal to the modem 46 via a signal line 176.

The modulator / demodulator 46 performs a waveform equalization process on the modulated image data input from the input 174 according to the control signal input from the input 176, and further performs a demodulation process on the modulated image data on which the waveform equalization process has been performed. It is a circuit that outputs the output to the output 168. The output 168 is connected to the error correction code addition / error correction circuit 42.

The image data output from the modulator / demodulator 46 is supplied to an error correction code addition / error correction circuit 42 and a signal line 170.
Is sent to the image memory 44 and temporarily stored therein. The error correction code addition / error correction circuit 42 performs an error correction process based on the error correction code of the image data read and transmitted from the image memory 44, and outputs the error-corrected image data to an output 164. This is an error correction circuit for outputting. The output 164 is connected to the compression / expansion circuit 40.

The compression / decompression circuit 40 is a decompression circuit that performs decompression processing on the error-corrected compressed image data input from the input 164 and outputs the result to an output 160. The output 160 is connected to the image memory 38.

The image memory 38 temporarily stores the expanded image data sent from the compression / expansion circuit 40.
The stored image data is sequentially read from the image memory 38, and the read image data is sent to the shuffling / deshuffling circuit 36 via the signal line 156.

The shuffling / deshuffling circuit 36 has a deshuffling function of returning the image data input from the input 156 to the original position on the screen and outputting it to the output 158.
The output 158 is connected to the corresponding input of the changeover switch 56. The image data output from the shuffling / deshuffling circuit 36 is supplied to a D / A converter 58 via a changeover switch 56.
Supplied to The digital image data is converted into an analog video signal in the D / A converter 58. The video signal is provided to the monitor device 60 and is displayed visually.

Returning to FIG. 1, the image memory 62 is a memory for storing data of a standard still image. In this example, a RAM having a storage capacity for temporarily storing at least one frame of R, G, and B image data. It is composed of A / D converter
The R data 120 and 121 from the A / D converter 26 are written to the R frame memory, and the B data 126 and 127 from the A / D converter
G is written to the frame memory, and G
Data 130 and 131 are written to the G frame memory. In this example, the G data 130 and 131 from the interpolation / synthesis circuit 28 are stored in the G frame memory, but the G2 data 122 and 123 from the A / D converter 26 may be stored. .

In this example, one frame of image data stored in the R frame memory is stored as shown in FIG.
One frame of image data stored in the G frame memory is stored as shown in FIG. 11, and one frame of image data stored in the B frame memory is stored as shown in FIG.

The image memory 62 has a control line 19 from the control circuit 84.
Control signals are sent through 0. The image memory 62 has A /
The R and B image data sent from the D converter 26 are temporarily stored, and the G and
Are temporarily stored. The R, G, and B image data are blocked according to a control signal sent from the control circuit 84, and the blocked data is output to the orthogonal transform circuit 66.

Blocking is performed, for example, by converting an image 500 as shown in FIG. 18 into a plurality of areas 502, 502, 502,.
・ That is, it is divided into blocks. One block 502 shown in FIG. 19 is preferably composed of, for example, 16 × 16 = 256 pixels, but if it is a block composed of a predetermined number of pixels according to the number of pixels constituting an image signal, Good. The blocked R, G and B image data are output from outputs 192, 194 and 196. The outputs 192, 194 and 196 are connected to the orthogonal transform circuit 66.

The orthogonal transformation circuit 66 performs an orthogonal transformation on the R, G, and B image data in blocks for each block. In this example, a cosine transform is used as the orthogonal transform. Although the cosine transform is used in this example, Hadamard transform or Fourier transform may be used. The orthogonal transformation is performed based on a control signal 198 from the control circuit 84. The R, G and B image data orthogonally transformed by the orthogonal transformation circuit 66 are output from outputs 200, 202 and 204. Outputs 200, 202 and 204 are connected to encoding circuit 68.

The encoding circuit 68 has a look-up table (L
(UT) 67 through the signal line 208 for encoding. Encoding, for example, figure
Matrix data as shown in 20 is performed by allocating a predetermined number of bits to each data. For example, the number of bits as shown in FIG. 21 is allocated, 8 bits are assigned to the data 200 in FIG. 20, 6 bits are assigned to the data 150, 130 and 150, and data 100 and 9 are assigned.
0, 40, 70, 80 have 4 bits, and data 50, 50, 10, 5, 10, 60,
Two bits are assigned to 20 and these data are encoded. R encoded in the encoding circuit 68,
The G and B image data are output from outputs 210, 212 and 214. The outputs 210, 212 and 214 are
Is connected to

An image memory 64 is a first memory for storing data of a high-definition still image, an arithmetic circuit for forming data of an interpolation pixel G from data of G1 and G2 pixels, and G1 and G2.
It comprises a second memory that stores pixel data and data of the interpolated pixel G.

The first memory has at least R,
Each of the RAMs G1, G2, and B has a storage capacity for temporarily storing image data for one frame. A / D converter
The R data 120 and 121 from the A / D converter 26 are written to the R frame memory, the G2 data 122 and 123 from the A / D converter 26 are written to the G2 frame memory, and the G1 data 12 and
4 and 125 are written to the G1 frame memory, and the A / D converter 26
Are written in the B frame memory.

In this example, the image data for one frame stored in the R frame memory is stored as shown in FIG.
One frame of image data stored in the G2 frame memory is stored as shown in FIG. 8, and one frame of image data stored in the G1 frame memory is stored as shown in FIG. 9 and stored in the B frame memory. One frame of image data is accumulated as shown in FIG. After the accumulation, the data of the interpolated pixel G is obtained by the arithmetic circuit described below.

The operation circuit will be described with reference to FIGS. 22 and 23. FIG. 22 shows the positions of G1 and G2 pixels indicated by solid lines and the position of G of the interpolated pixel indicated by dotted lines. As can be seen from the figure, one pixel shift between G1 and one pixel between G2.
Pixel shift. G1 and G are shifted by a half pixel, and G2 and G are also shifted by a half pixel.

FIG. 23 is an explanatory diagram for finding the data value of the interpolation pixel G. G1 on a half pixel of G is defined as G1U,
G1 below half a pixel of G is G1B, G2 right of a half pixel of G is G2R, and G2 of a half pixel left of G is G2L. The data of G1 and G2 used for the operation are read from the frame memories of G1 and G2.

The first one is obtained from the left and right G2, and the equation is shown in equation (5).

G = (G2L + G2R) / 2 (5) The second is obtained from the upper and lower G1, and the equation is shown in equation (6).

G = (G1U + G1B) / 2 (6) The third is obtained from the upper and lower G1 and the left and right G2, and the equation is shown in equation (7).

G = k1 · (G2L + G2R) / 2 + (1-k1) (G1U + G1B) / 2 (7) Note that k1 is 0 <k1 <1.

A fourth method is to obtain the upper and lower G2 and the left and right G1 in addition to the upper and lower G1 and the left and right G2. Equation (8) shows the value obtained from the upper and lower G1 and left and right G2, and equation (9) shows the value obtained from the upper and lower G2 and the left and right G1.

G = (cv ₁ · (G2L + G2R) + ch ₁ · (G1U + G1B)) / 2 (8) where ch ₁ is ch ₁ = ah ₁ / (ah ₁ + av ₁ ) And cv ₁ is cv
₁ = av ₁ / (ah ₁ + av ₁ ). Where ah ₁ is ah ₁ = | G2L-G2R |
And av ₁ = | G1U-G1B |.

The above ch ₁ indicates the strength of the correlation in the horizontal direction, and cv ₁ indicates the strength of the correlation in the vertical direction.
The smaller the value, the stronger the correlation. Ah ₁ above is the left and right G2
Is the absolute value of the difference between the data values, av ₁ is the absolute value of the difference between the data values of the upper and lower G1 (see FIG. 23).

G = (cv ₂ · (G1L + G1R) + ch ₂ · (G2U + G2B)) / 2 (9) where ch ₂ is ch ₂ = ah ₂ / (ah ₂ + av ₂ ) And cv ₂ is cv
₂ = av ₂ / (ah ₂ + av ₂ ). Where ah ₂ is ah ₂ = | G1L-G1R |
And av ₂ = | G2U-G2B |.

The above ch ₂ indicates the strength of the correlation in the horizontal direction, and cv ₂ indicates the strength of the correlation in the vertical direction.
The smaller the value, the stronger the correlation. Ah ₂ above is left and right G1
Is the absolute value of the difference between the data values, av ₂ is the absolute value of the difference between the data values of the upper and lower G2.

Although the arithmetic circuit based on the fourth arithmetic expression is advantageously applied in the present embodiment, any one of the arithmetic circuits based on the other three arithmetic expressions may be applied.

The G data obtained by the above calculation and the G1 and G2 data read from the first memory are stored in the second memory. Finally, the G component data for one frame as shown in FIG. 24 is stored in the second memory.
Referring to FIG. 24, it can be seen that the number of pixels for one frame is four times the number of pixels for one frame of G1 or G2. Specifically, the number of pixels in the horizontal direction in FIG. 24 is twice the number of pixels in the horizontal direction of G1 or G2, and the number of pixels in the vertical direction is G1.
Or it is twice the number of pixels in the vertical direction of G2. Thus, a high-resolution still image can be obtained.

When one frame of G component image data is stored in the second memory, the R data is stored in the R memory of the first memory.
Read from the frame memory and output to output 216, G
Data (comprised of G1, G2 and interpolation G data) is read from the second memory and output on output 218, and B data is read from the B frame memory and output on output 220. Control signals necessary for writing, reading, and calculating such data are sent from the control circuit 84 through a control line 215. The outputs 216, 218 and 220 are connected to the changeover switch 70.

A printer may be connected to the output of the image memory 64, and the image of the high-definition still image data stored in the printer may be printed by the printer.

When the standard still image recording mode is set, the changeover switch 70 switches between the input 210 and the output 224 and the input 212
Between output and output 226 and between input 214 and output 228
N "between input 216 and output 224, input 218 and output 226
, And between input 220 and output 228 are set to “OFF”. If the high-resolution still image recording mode is set,
216 to output 224, input 218 to output 226, input 22
"ON" between 0 and output 228 respectively, input 210 and output
224, between input 212 and output 226, input 214 and output 22
The interval between 8 is “OFF”. Such a switching signal is sent from the control circuit 84 through the control line 222.
Outputs 224, 226 and 228 are connected to memory 72.

As the memory 72, for example, a so-called memory card in which a semiconductor memory or the like is mounted on a card-like substrate is advantageously used. The memory 72 stores an encoded standard still image and a high-definition still image. A control signal for storing such still image data is sent from the control circuit 84 through a control line 230.

Referring to FIG. 1, the operation unit 74 of the present apparatus includes a moving image recording mode setting button circuit 76, a moving image reproduction mode setting button circuit 78, a standard still image recording mode setting button circuit 80, and a high definition still image recording mode setting button. The circuit 82 is provided.

The moving image recording mode setting button circuit 76 has a moving image recording mode setting button, and when this button is pressed, a control signal indicating that moving image recording is to be performed is output to the output 232. By pressing this button, a control signal 232 indicating that moving image recording is performed is supplied to the control circuit 84,
Shooting and recording of a moving image is performed under the control of the control circuit 84. The moving image reproduction mode setting button circuit 78 has a moving image reproduction mode setting button, and when this button is pressed, a control signal indicating that the moving image is reproduced is output to the output 234. When this button is pressed, a control signal 234 indicating that the moving image is to be reproduced is supplied to the control circuit 84, and the moving image is reproduced under the control of the control circuit 84.

The standard still image recording mode setting button circuit 80 has a standard still image recording mode setting button, and when this button is pressed, a control signal indicating that standard still image recording is performed is output to the output 236. . Pressing this button causes a control signal 236 indicating that standard still image recording is to be performed.
Is supplied to the control circuit 84, and the shooting and recording of the standard still image is performed under the control of the control circuit 84. In this case, if the moving image recording mode setting button is also pressed, standard still image recording is performed simultaneously with moving image recording.

High-definition still image recording mode setting button circuit 82
Is a circuit having a high-definition still image recording mode setting button, and outputting a control signal to the output 238 indicating that high-definition still image recording is performed by pressing this button. When this button is pressed, a control signal 238 indicating that a high-definition still image is to be recorded is supplied to the control circuit 84. Under the control of the control circuit 84, a high-definition still image is recorded and recorded. In this case, if the moving image recording mode setting button is pressed, high-definition still image recording is performed simultaneously with moving image recording.

In this embodiment, the control circuit 84 is also advantageously constituted by a microcomputer, that is, a processing system such as a CPU (Central Processing Unit), and the moving picture recording transmitted through the control line 232 when the moving picture recording mode setting button is pressed. , A control signal 234 transmitted through the control line 234 when the moving image playback mode setting button is pressed, and a control signal 236 through the control line 236 when the standard still image recording mode setting button is pressed. A control signal 236 indicating that standard still image recording is transmitted, and a control signal 238 indicating that high-definition still image recording is transmitted via a control line 238 when the high-definition still image recording mode setting button is pressed. Is a control function unit that controls the operation of the entire apparatus in response to

The operation of recording a moving image will be described.

The moving image recording mode is set by pressing the moving image recording mode setting button. When the video recording mode is set,
The subject is photographed by the solid-state imaging unit 10 at a cycle of 60 seconds.
Image signals R, G2, G1, and B representing a subject image obtained by shooting are sequentially output from the solid-state imaging unit 10 in units of two lines, and the signal processing unit 24
Given to. Image signal sequentially output in units of two lines
R, G2, G1, and B are each amplified to a predetermined level in the signal processing unit 24, and the amplified image signals R, G2, G1, and B are subjected to white balance adjustment and γ correction, and / D converter 26.

The image signals R, G2, G1, and B sequentially output from the signal processing unit 24 in units of two lines are converted into digital signals in the A / D converter 26. The image data G2 and G1 converted into digital signals are supplied to the interpolation / synthesis circuit 28 and interpolated and synthesized as described above to generate image data G. The generated image data G is provided to the frame memory 30 and temporarily stored. Image data converted to digital signals
R and B are given to the frame memory 30 and temporarily stored.

The image data R, G, and B of one frame stored in the frame memory 30 are read by the control circuit 84 for generating even fields and reading for generating odd fields as described above. Read image data R,
G and B are given to the signal processing unit 32 and the image data R, G and B of the even field and the odd field by the method described above.
Are generated, and the image data Y, RY, and BY are generated from the generated image data R, G, and B. The generated image data Y, RY, and BY are provided to the frame memory 34 and temporarily stored.

The image data is read from the frame memory 34 and applied to the shuffling / deshuffling circuit 36.
DCT block generation processing, macro block generation processing, superblock generation processing, group generation processing, and the like are performed. Shuffling / deshuffling circuit
The image data output from 36 is supplied to an image memory 38 in units of macro blocks. Image data for one frame of Y, RY, BY is stored in the image memory 38.

The image data stored in the image memory 38 is read out in units of groups and supplied to the compression / expansion circuit 40. In the compression / expansion circuit 40, data compression is performed so that the data amount of the image data of the group becomes a predetermined data amount. The compressed image data is provided to an image memory 44 via an error correction code addition / error correction circuit 42 and is temporarily stored therein. The compressed image data is read from the image memory 44, applied to an error correction code addition / error correction circuit 42, and added with an error correction code.

The image data to which the error correction code has been added is supplied to the modulator / demodulator 46 and modulated. The modulated image data is
The signal is amplified by the recording / reproducing amplifier 48 and supplied to the magnetic head 52. The magnetic head 52, modulated image data is recorded in the video recording area A ₂ of the magnetic tape 54.

The operation of reproducing a moving image will be described.

[0111] The moving image reproduction mode is set by pressing the moving image reproduction mode setting button. When the moving image playback mode is set, the image data recorded in the video recording area of the magnetic tape 54 is read by the magnetic head 52. Magnetic head
The data read by 52 is amplified by a recording / reproducing amplifier 48 and sent to a modem 46. Recording / playback amplifier 48
The data amplified in is also sent to the waveform equalizer 50. A control signal for waveform equalization is generated in the waveform equalizer 50 and sent to the modem 46. The modulator / demodulator 46 performs demodulation processing of image data and waveform equalization processing.

The image data output from the modulator / demodulator 46 passes through an error correction code addition / error correction circuit 42, is given to an image memory 44, and is temporarily stored. The image data stored in the image memory 44 is sequentially read out, and the error correction code addition / error correction circuit 42 performs an error correction process based on the error correction code. The error-corrected image data is applied to a compression / expansion circuit 40, where the data is expanded, and is applied to an image memory 38 where it is temporarily recorded.

The image data is read from the image memory 38, applied to the shuffling / deshuffling circuit 36, and returned to the original position on the image. The output image data of the shuffling / deshuffling circuit 36 is transmitted through the changeover switch 56.
The signal is supplied to the D / A converter 58 and converted into an analog video signal. This analog video signal is provided to the monitor device 60 and is displayed visually.

The operation of standard still picture recording will be described.

When the standard still image recording mode is set by pressing the standard still image recording mode setting button, the solid-state imaging unit 10
Is performed to photograph the subject. Image signals R, G2, G1, and B representing a subject image obtained by photographing are sequentially output from the solid-state imaging unit 10 in units of two lines and supplied to the signal processing unit 24. 2
Image signals R, G2, G1, and B sequentially output in line units are amplified to predetermined levels in the signal processing unit 24, respectively.
Further, the amplified image signals R, G2, G1, and B are subjected to white balance adjustment and gamma correction, and are subjected to an A / D converter.
Given to 26.

The image signals R, G2, G1, and B sequentially output in units of two lines from the signal processing unit 24 are converted into digital signals by the A / D converter 26. The image data G2 and G1 converted into digital signals are supplied to the interpolation / synthesis circuit 28 and interpolated and synthesized as described above to generate image data G. The generated image data G is provided to the image memory 62 and temporarily stored. Also, image data R and B converted to digital signals
Is given to the image memory 62 and temporarily stored.

The image data stored in the image memory 62 is divided into blocks as described above by the control signal from the control circuit 84, and is supplied to the orthogonal transformation circuit 66. The orthogonal transform is performed by the orthogonal transform circuit 66 and is supplied to the encoding circuit 68. The orthogonally transformed data is encoded in the encoding circuit 68 in accordance with the picture of each block, and given to the memory 72 via the changeover switch 70 and recorded.

The operation of recording a high-definition still image will be described.

When the high-definition still image recording mode is set by pressing the high-definition still image recording mode setting button, the object is photographed by the solid-state imaging unit 10. The operation from the solid-state imaging unit 10 to the A / D converter 26 is basically the same as that in the standard still image recording mode or the like, and a description thereof is omitted.

Image data R converted into digital signals,
G2, G1, and B are given to the first memory of the image memory 64 and temporarily stored. The image data G2 and G1 are read from the first memory and are used as image memories for forming data of the interpolation pixels G.
It is provided to 64 arithmetic circuits. The image data G is generated by the interpolation and synthesis in the arithmetic circuit as described above. The generated image data G is provided to the second memory of the image memory 64, and is temporarily stored in a predetermined position in units of 1/2 pixel. The image data G2 and G1 stored in the first memory are also read out and given to the second memory, where they are temporarily stored in predetermined positions in half-pixel units.

The image data R, B stored in the first memory
And the G component image data G stored in the second memory
2, G1 and G are given to the memory 72 via the changeover switch 70 and recorded.

According to the high-definition still image recording system of this embodiment, as can be seen from the number of pixels of the G component stored in the second memory, the number of pixels of the G component is changed to the G2 component solid-state image pickup device 18.
Can be made four times the number of pixels in one frame or four times the number of pixels in one frame of the solid-state imaging device 20 for the G1 component. Therefore, the resolution of the still image can be effectively improved.

[0123]

As described above, according to the present invention, the image pickup means of the video camera with a still camera includes a red solid-state image pickup device, a first green solid-state image pickup device, and a second green solid-state image pickup device. And a spatial sampling position of the second green solid-state imaging device is a half pixel pitch with respect to a spatial sampling position of the first green solid-state imaging device. The solid-state image pickup device for red, the second solid-state image pickup device for green, and the solid-state image pickup device for blue are at the same spatial sampling position.

The red solid-state image sensing means includes horizontal transfer register means for red even-numbered lines, and horizontal transfer register means for red odd-numbered lines, and the first solid-state image sensing means for green comprises a first green even-numbered line. And a first green odd-numbered line horizontal transfer register. The second green solid-state image pickup device includes a second green even-numbered line horizontal transfer register, and a second green odd-numbered horizontal transfer register. And a horizontal transfer register for blue, and the solid-state imaging device for blue includes horizontal transfer register for blue even-numbered lines and horizontal transfer register for blue odd-numbered lines.

Further, there is provided control means for controlling the image pickup means. The control means supplies a control signal for reading to the image pickup means, and supplies a horizontal transfer register means for each color even number line and a horizontal transfer register means for each color odd line. , The respective color image signals of the pixels of the even lines and the odd lines are transferred in a predetermined one line period, and the horizontal transfer register means for the even lines of each color and the horizontal transfer register means for the odd lines of each color are used to transfer the even lines and odd numbers of one screen. Each color image signal of each pixel of the line can be transferred in a predetermined one frame period. Therefore, still photography in which still recording is performed in units of one frame and video photography in which video (moving image) recording is performed in even fields and even fields can be performed simultaneously.

The spatial sampling position of the second green solid-state imaging device is shifted obliquely by a half pixel pitch from the spatial sampling position of the first green solid-state imaging device. Further, the first and second green image data read from the first and second green storage means are subjected to interpolation processing to obtain third green image data for interpolation.
And the first and second green image data are arranged in a horizontal and vertical direction at a half pixel width and one pixel pitch, and the third green image data is stored in the first and second green image data. The data is shifted by a 1/2 pixel pitch in the horizontal and vertical directions with respect to the data to have a 1/2 pixel width. And a first green storage means,
There is provided a third green storage unit for storing each color image data output from the second green storage unit and the first interpolation unit in units of 1/2 pixel. As you can see from the above,
The third green storage means stores data having a data amount four times the data amount stored in the first or second green storage means. The data stored in the third green storage means is used for reproducing the still image. Therefore, a high-resolution still image can be obtained.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a specific configuration of an embodiment of a video camera with a still camera according to the present invention in combination with FIG.

FIG. 2 is a functional block diagram showing a specific configuration of an embodiment of a video camera with a still camera according to the present invention in combination with FIG.

FIG. 3 is a diagram showing a combination state of FIGS. 1 and 2;

FIG. 4 is a functional block diagram showing a specific configuration of each solid-state imaging device of the embodiment shown in FIG.

FIG. 5 is a diagram showing a relationship between pixel positions of two solid-state imaging devices for G1 and G2 in the embodiment shown in FIG. 1;

FIG. 6 is a diagram illustrating a relationship between pixel positions of three solid-state imaging devices for G2, R, and B in the embodiment illustrated in FIG. 1;

FIG. 7 shows an analog / digital (A / A / D) circuit of the embodiment shown in FIG.
D) A diagram showing image data for one frame of a red (R) component output from the converter.

FIG. 8 shows an analog / digital (A / A / D) circuit of the embodiment shown in FIG.
D) A diagram showing one frame of image data of a green (G2) component output from the converter.

FIG. 9 shows an analog / digital (A / A / D) of the embodiment shown in FIG. 1;
D) A diagram showing one frame of image data of a green (G1) component output from the converter.

FIG. 10 shows the analog / digital (A) of the embodiment shown in FIG. 1;
/ D) is a diagram showing one frame of image data of a blue (B) component output from a converter.

11 is a diagram showing one frame of image data of an interpolated pixel green (G) component formed by the interpolating / combining circuit of the embodiment shown in FIG. 1;

12 is a diagram showing image data of an even field and an odd field of a luminance component Y stored in the frame memory of the embodiment shown in FIG. 1;

13 is a diagram showing image data of an even field and an odd field of a color difference component RY stored in the frame memory of the embodiment shown in FIG. 1;

FIG. 14 is a diagram showing image data for even and odd fields of a color difference component BY stored in the frame memory of the embodiment shown in FIG. 1;

FIG. 15 is a diagram showing an example of a DCT block for one field of a luminance component Y formed by the shuffling / deshuffling circuit of the embodiment shown in FIG. 2;

16 is a diagram showing an example of a DCT block for one field of a color difference component RY formed by the shuffling / deshuffling circuit of the embodiment shown in FIG. 2;

FIG. 17 is a diagram showing an example of a DCT block for one field of a color difference component BY formed by the shuffling / deshuffling circuit of the embodiment shown in FIG. 2;

18 is a diagram showing an example of an image of one screen input to the image memory of the embodiment shown in FIG.

FIG. 19 is a conceptual diagram showing an example of a block for one field formed by the control circuit and the image memory of the embodiment shown in FIG. 1;

FIG. 20 is a diagram showing an example of one block of data output from the orthogonal transform circuit of the embodiment shown in FIG. 1;

21 is a diagram illustrating an example of the number of bits allocated to each data of one block output from the look-up table of the embodiment illustrated in FIG. 1;

FIG. 22 is a conceptual diagram showing a pixel position of an interpolation pixel green (G) component formed by the image memory of the embodiment shown in FIG.

FIG. 23 is a diagram showing an example of a method for obtaining data of an interpolation pixel green (G) component formed by the image memory of the embodiment shown in FIG. 1;

FIG. 24 is a diagram showing one frame of image data of a green (G) component stored in a second memory of the image memory of the embodiment shown in FIG. 1;

FIG. 25 is a diagram showing tracks on the magnetic tape of the embodiment shown in FIG. 2;

FIG. 26 is a diagram showing a format of the track shown in FIG. 25.

FIG. 27 is a functional block diagram of an example of a conventional still camera unit.

FIG. 28 is a diagram illustrating a relationship between pixel positions of three solid-state imaging devices illustrated in FIG. 27;

[Explanation of symbols]

 10 Solid-state imaging unit 24, 32 Signal processing unit 26 Analog / digital (A / D) converter 28 Interpolation / synthesis circuit 30, 34 Frame memory 36 Shuffling / deshuffling circuit 38, 44, 62, 64 Image memory 40 Compression / expansion circuit 42 Error correction code addition / error correction circuit 46 Modulator / demodulator 48 Recording / playback amplifier 50 Waveform equalizer 52 Magnetic head 54 Magnetic tape 56, 70 selector switch 58 Digital / analog (D / A) converter 60 Monitoring device 66 Quadrature conversion circuit 67 Look-up table (LUT) 68 Encoding circuit 72 Memory 74 Operation unit 84 Control circuit

Claims (11)

[Claims] 1. A video camera with a still camera that captures an image of a subject by an imaging unit to obtain image data of a still image, and captures an image of the subject by the imaging unit to obtain image data of a moving image. A red solid-state imaging device for receiving the red imaging light of the imaging light and forming and outputting a red image signal; and receiving the green imaging light of the imaging light to form a first green image signal. First green solid-state imaging device means for receiving and outputting green imaging light among the imaging light to form and output a second green image signal; and A blue solid-state imaging device that receives blue imaging light among the imaging light and forms and outputs a blue image signal; and a spatial sampling position of the first green solid-state imaging device. 2 for green The spatial sampling position of the body imaging device is shifted obliquely by a half pixel pitch, and the red solid imaging device, the second green solid imaging device, and the blue solid imaging device are the same. A video camera with a still camera, which is a spatial sampling position. 2. The video camera with a still camera according to claim 1, wherein said solid-state image pickup device for red comprises a horizontal transfer register for red even-numbered lines for transferring the red image signal of even-numbered lines, and a horizontal transfer register for odd-numbered lines. And a horizontal transfer register for odd-numbered red lines for transferring the red image signal, wherein the first solid-state imaging device for green for first green transfers horizontal transfer for the first green even-numbered line for transferring the green image signal of even-numbered lines. Register means; and first horizontal transfer register for odd green lines for transferring the green image signal of odd lines, wherein the second solid-state image pickup device for green transfers the green image signal of even lines. Second horizontal transfer register for even green lines, and a second horizontal transfer register for odd green lines for transferring the green image signal of odd lines. A blue solid-state imaging device means, a blue even-number line horizontal transfer register means for transferring the even-numbered blue image signal, and a blue odd-line horizontal transfer means for transferring the odd-numbered blue image signal. A video camera with a still camera, comprising: register means. 3. The video camera with a still camera according to claim 2, further comprising control means for controlling said image pickup means, said control means including a control signal for reading out to said image pickup means. To transfer the respective color image signals of the pixels of the even lines and odd lines from the horizontal transfer register means for each color even line and the horizontal transfer register means for each color odd line in a predetermined one line period, and A still camera, wherein the color image signals of the pixels of even and odd lines of one screen are transferred from a horizontal transfer register for lines and a horizontal transfer register for odd lines of each color in a predetermined one frame period. Video camera. 4. The video camera with a still camera according to claim 3, wherein the camera further supports a red image signal output from the horizontal transfer register for red even-numbered lines and the horizontal transfer register for red-odd-numbered lines. Signal conversion means for converting to a digital signal to be converted and outputting, and a first green image signal output from the first horizontal transfer register for green even lines and the first horizontal transfer register for green odd lines Into a corresponding digital signal and output the first green signal conversion means; and the second green even number line horizontal transfer register means and the second green odd line horizontal transfer register means Second green signal converting means for converting the green image signal into a corresponding digital signal and outputting the digital signal; Signal conversion means for converting the blue image signal output from the horizontal transfer register means for blue and the horizontal transfer register means for blue odd lines into a corresponding digital signal and outputting the digital signal, and wherein the control means further comprises: A video camera with a still camera, wherein the video camera is connected to a signal converting means for the camera, and the control means causes the signal converting means for each color to perform conversion into the digital signal. 5. The video camera with a still camera according to claim 4, wherein said camera further comprises: first red storage means for storing red image data digitized by said red signal conversion means; First green storage means for storing first green image data digitized by the first green signal conversion means, and second green image digitized by the second green signal conversion means A video camera with a still camera, comprising: a second storage device for storing green data; and a first storage device for storing blue image data digitized by the signal conversion device for blue. . 6. The video camera with a still camera according to claim 5, wherein the camera further interpolates the first and second green image data read from the first and second green storage means. A first interpolation means for performing processing to obtain third green image data for interpolation, wherein the first and second green image data are 、 pixel width in a horizontal and vertical direction at a one pixel pitch. The third green image data is shifted by 1/2 pixel pitch in the horizontal and vertical directions with respect to the first and second green image data, and
A video camera with a still camera, which has a pixel width. 7. The video camera with a still camera according to claim 6, wherein said camera further comprises: a color output from said first green storage means, a second green storage means, and a first interpolation means. Image data 1 /
A third green storage unit for storing in two-pixel units, wherein the camera is stored in the first red storage unit, the first blue storage unit, and the third green storage unit. A video camera with a still camera, wherein each color image data is image data of the still image. 8. The video camera with a still camera according to claim 6, wherein said first interpolation means shifts said third green image data vertically and vertically by a half pixel pitch. If the second green image data is located between the image data and is shifted horizontally by a half pixel pitch from the second green image data, the first green image data is shifted vertically by a half pixel pitch And first calculating means for obtaining the third green image data from the second green image data shifted to the left and right by a half pixel pitch, and wherein the third green image data is vertically shifted by a half pixel vertically. The first green image data which is located between the second green image data shifted in pitch and shifted 1/2 pixel pitch left and right in the horizontal direction.
And between the green image data of
A second calculating means for obtaining the third green image data from the second green image data shifted by a pixel pitch and the first green image data shifted by a half pixel pitch to the left and right. Video camera with still camera. 9. The video camera with a still camera according to claim 4, wherein the camera further converts the first and second green image data digitized by the first and second green signal conversion means. Video camera with a still camera, comprising: a second interpolation means for performing interpolation processing to obtain fourth green image data for interpolation. 10. The video camera with a still camera according to claim 9, wherein said camera further comprises: a second red storage means for storing red image data digitized by said red signal conversion means; Fourth green storage means for storing fourth green image data output from the second interpolation means, and second blue storage for storing blue image data digitized by the blue signal conversion means. And a video camera with a still camera. 11. The video camera with a still camera according to claim 10, further comprising: a camera that outputs image data for even and odd fields from the red image data read from the second red storage means. A red field generation unit formed in the predetermined one frame period; and even and odd field image data from the green image data read from the fourth green storage unit in the predetermined one frame period, respectively. Green field generating means for forming, and blue field generating means for forming image data for even and odd fields from the blue image data read from the second blue storage means in each of the predetermined one frame period The camera has an even field and an odd field output from the field generation means for each color. Still camera a video camera, characterized in that the image data of each color use the image data of the moving image.