JPH10257422A - Image recording and reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To expand an idle capacity even during image recording. SOLUTION: An inputted moving image is compressed and encoded by a block circuit 10, an orthogonal transforming circuit 12, a quantizing circuit 16, and a variable length encoding circuit 20, and the result is written through a formatting circuit 22 into a semiconductor memory 24. When the idle capacity of memory 24 is reduced, recorded image data are read out and restored up to orthogonal transform coefficient data by a variable length decoding circuit 30 and an inverse quantizing circuit 32. A quantizing step control circuit 18 sets the quantizing step of recompressibility to the quantizing circuit 16. A switch 14 is connected to a contact (b) during idle time in the recording processing of the input image. The quantizing circuit 16 quantizes both the input image and the recompressed image through the same quantizing step.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image recording and reproducing apparatus for recording and reproducing an image.

[0002]

2. Description of the Related Art A recording medium of a conventional image recording / reproducing apparatus is:
Generally, a magnetic tape is used, and a hard disk is also used due to an increase in image compression technology and an increase in recording capacity. Also, the recording capacity of optical disks, magneto-optical disks, and even semiconductor memories has been increasing, and their use as recording media for image information, particularly moving images, has been studied.

[0003] Semiconductor memories are expected to be used in portable devices, for example, video cameras because of their low power consumption and easy downsizing. Semiconductor memories have many other advantages, such as high speed access, random access, and resistance to vibration.

There are various image compression techniques.
A method using both quantization and variable-length coding is well known, and is known as a JPEG method, an MPEG method, or the like. FIG. 3 is a schematic block diagram of an image recording / reproducing apparatus that uses an image compression technique that uses orthogonal transform, quantization, and variable-length coding in combination.

The blocking circuit 110 divides input image data into blocks of 8 × 8 pixels or 16 × 16 pixels, and outputs the blocks in units of blocks. Orthogonal transform circuit 112
Performs orthogonal transformation (for example, discrete cosine transformation) on image data output from the blocking circuit 110 in units of predetermined blocks, and a quantization circuit 114 quantizes the output of the orthogonal transformation circuit 112. The quantization step control circuit 116
The quantization step of the quantization circuit 114 is controlled according to the output of the orthogonal transformation circuit 112. Thereby, the compression ratio can be adjusted. The variable length coding circuit 118 performs variable length coding on the output data of the quantization circuit 114 and supplies the code data to the formatting circuit 120. The formatting circuit 120 is further supplied with information on the quantization step applied by the quantization circuit 114 from the quantization step control circuit 116. The formatting circuit 120 shapes the input information into a predetermined format, and Write to memory 122.

The data separation circuit 124 is a semiconductor memory 12
The code data and the information about the quantization step are extracted from the data read out from the data 2, and the code data is applied to the variable length decoding circuit 126 and the information about the quantization step is applied to the inverse quantization circuit 128. The variable length decoding circuit 126 performs variable length decoding on the code data from the data separation circuit 124 and applies the decoded data to the inverse quantization circuit 128. Inverse quantization circuit 128
Dequantizes the output data of the variable length decoding circuit 126 according to the information on the quantization step from the data separation circuit 124. The inverse orthogonal transform circuit 130 is an inverse quantization circuit 1
Orthogonally transforms the output of the raster-scan processing circuit 28 into a raster scan processing circuit 1
32 converts the output of the inverse orthogonal transform circuit 130 into raster data.

[0007]

However, since the recording capacity of a semiconductor memory is much smaller than that of a magnetic tape,
Movie recording time (or number of recordable still images)
Is much shorter (less) than magnetic tape. As a result, the period in which the recording medium has to be used and the recording medium must be replaced is significantly shorter than that of the magnetic tape.

Of course, if the recording medium cannot be replaced because there is no new recording medium at hand, the already recorded image must be erased and overwritten, or the recording of a new image must be abandoned.

An object of the present invention is to provide an image recording / reproducing apparatus which solves such a problem.

[0010] That is, an object of the present invention is to provide an image recording / reproducing apparatus which can lengthen the exchange period of a recording medium.

Another object of the present invention is to provide an image recording / reproducing apparatus which can use one recording medium for a longer period of time.

[0012]

According to the present invention, when the remaining amount of a recording medium becomes insufficient during recording of an image, the already recorded image data is decoded without interrupting the recording of the moving image.
Re-encoding is performed with different compression characteristics and re-recorded on the same recording medium. Thus, the remaining amount of the recording medium can be increased without requiring the user to take extra time.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic block diagram showing an embodiment of the present invention. Reference numeral 10 denotes a blocking circuit that divides input image data into blocks of 8 × 8 pixels or 16 × 16 pixels and outputs the blocks in units of blocks. An orthogonal transformation circuit 14 that performs an orthogonal transformation (for example, a discrete cosine transformation) at a contact point a (orthogonal transformation circuit 1) during image recording.
2) and a switch for selecting the b-contact at the time of recompression, 16 is a quantization circuit for quantizing the orthogonal transform data selected by the switch 14, and 18 is a switch 14
Quantization circuit 16 in accordance with the orthogonal transformation data selected by
Quantization step control circuit for controlling the quantization step of
Reference numeral 20 denotes a variable length coding circuit for performing variable length coding on output data of the quantization circuit 16, and reference numeral 22 denotes a code data from the variable length coding circuit 20 and a quantization circuit 114 from the quantization step control circuit 18. A formatting circuit for shaping the information on the quantized step into a recording format of the semiconductor memory 24, and a memory control circuit 26 for controlling data writing and reading of the semiconductor memory 24.

Reference numeral 28 denotes a data separation circuit for separating code data and information relating to a quantization step from data read from the semiconductor memory 24, and 30 denotes a data separation circuit 2
A variable-length decoding circuit for performing variable-length decoding on the code data from No. 8 and an inverse quantization circuit for performing inverse quantization on the output data of the variable-length decoding circuit 30 in accordance with information on the quantization step from the data separation circuit; , 34 are the inverse quantization circuit 32
Is connected to the contact a during recording, and connected to the contact b during recompression. 36 is an inverse orthogonal transform circuit for performing inverse orthogonal transform of data from the contact a of the switch 34;
Is a raster scan processing circuit for converting the output data of the inverse orthogonal transform circuit 36 in raster order.

Reference numeral 40 denotes a system control circuit for controlling the whole, especially the switches 14, 34, the quantization step control circuit 18 and the memory control circuit 26.

The b contact of the switch 34 is connected to the b
Connect to contacts. Information on the quantization step at the time of recording output from the data separation circuit 28 is also supplied to the quantization step control circuit 18.

Next, the operation of this embodiment when recording an image will be described. At this time, the system control circuit 40
To the a contact. The blocking circuit 10 divides the input image data of one frame into two-dimensional blocks of 8 × 8 pixels, and outputs the two-dimensional blocks to the orthogonal transformation circuit 12 for each block. The orthogonal transformation circuit 12 orthogonally transforms the image data from the blocking circuit 10, and the orthogonal transformation coefficient data is applied to the quantization circuit 16 and the quantization step control circuit 18 via the switch 14. Quantization step control circuit 18
Determines the quantization step to be applied by the quantization circuit 16 in accordance with the range of the orthogonal transform coefficient data from the switch 14, and the quantization circuit 16
Quantizes the orthogonal transform coefficient data from the switch 14 in accordance with the quantization step determined in (1). Variable length coding circuit 2
0 performs variable length coding on the output data of the quantization circuit 16.

The formatting circuit 22 shapes the code data from the variable length coding circuit 20 and the information on the quantization step from the quantization step control circuit 18 into a predetermined recording format, and writes it into the semiconductor memory 24.
The memory control circuit 26 controls a write address of the semiconductor memory 24 and the like. In the semiconductor memory 24, the image data is managed by the memory control circuit 26 for each frame.

The operation of reading and reproducing an image recorded in the semiconductor memory 24 is the same as in the conventional example. In this reproduction mode, the switch 34 is connected to the contact a.

FIG. 4 shows the structure of one frame of data recorded in the semiconductor memory 24. One frame of data is
It consists of the address of the data of the previous frame, the address of the data of the next frame, and the image data. By having addresses (or pointers) to the data of the next frame and the previous frame, it is not necessary to write the data of each frame to the semiconductor memory 24 in sequence. Such techniques are known per se.

The system control circuit 40 controls the switches 14, 34, the quantization step control circuit 18 and the memory control circuit 26 in response to commands such as recording, reproduction, retrieval and automatic compression. System control circuit 40
Is also transmitted through the memory control circuit 26 to the semiconductor memory 24.
Is constantly monitoring the remaining amount.

When the automatic compression command is set or input, the system control circuit 40 automatically recompresses the recorded image data when the remaining amount of the semiconductor memory 24 becomes equal to or less than the set amount. If the automatic compression instruction is not set,
The system control circuit 40 does not automatically execute the recompression processing regardless of the remaining amount of the semiconductor memory 24. When the recompression processing of the already recorded image data is performed by the automatic compression instruction, the image recording processing and the recompression processing are executed by the system control circuit 40 in a time division manner.

The operation in the case where the remaining amount of the semiconductor memory 24 becomes small during recording of a moving image and the recording image of the semiconductor memory 24 is re-compressed while continuing to record the image will be described in detail.

The system control circuit 40 constantly monitors the remaining capacity of the semiconductor memory 24 via the memory control circuit 26, and the remaining capacity of the semiconductor memory 24 is, for example, 3
When the number decreases, the quantization step control circuit 18 and the switches 14 and 34 are set to the recompression mode. When the recording process of the input image is not executed, the recompression process of the recorded image is preferentially executed. When the recording process of the input image is executed, the recompression process of the recorded image is skipped between the recording processes of the input image. Perform compression processing.

In the recompression mode, the quantization step control circuit 18 increases the value of the quantization step of the image to be recorded at the time of normal recording, and sets the same value as the compression ratio at the time of recompression of the recorded image. The compression ratio should be about the same.

In the recompression mode, the system control circuit 40 instructs the memory control circuit 26 to
4 to read the recorded image data. The data separation circuit 28 separates information relating to the quantization step and code data from the data read from the semiconductor memory 24, and replaces the former with the quantization step control circuit 18 and the inverse quantization circuit 32.
And the latter is applied to the variable length decoding circuit 30. The variable length decoding circuit 30 performs variable length decoding on the code data from the data separation circuit 28, and the inverse quantization circuit 32 refers to the information on the quantization step at the time of recording from the data separation circuit 28 and performs variable length decoding. The output of the quantization circuit 30 is inversely quantized. The output of the inverse quantization circuit 32 is orthogonal transform coefficient data.

When one frame of recorded image data read from the semiconductor memory 24 is reproduced up to the orthogonal transform coefficient data, the memory control circuit 26 records the read recorded image on the semiconductor memory 24 where the recorded image was recorded. The data in the area is deleted to make it a free area.

The output of the inverse quantization circuit 32 is applied to the contact "b" of the switch 14 via the switch 34.
Is supplied to the quantization circuit 16 and the quantization step control circuit 18 during the connection to the b contact.

For the data to be recompressed, the quantization step control circuit 18 refers to the information on the quantization step supplied from the data separation circuit 28, and determines a larger quantization step than the quantization step in the first recording. The quantization circuit 16 is controlled to apply the quantization step. For example, the quantization step control circuit 18 sets a quantization step twice as large as the quantization step specified by the information on the quantization step supplied from the data separation circuit 28 in the quantization circuit 16. As a result, the compression ratio can be greatly increased, and the occupied capacity of the semiconductor memory 24 can be reduced.

The quantization step control circuit 18 also sets a larger quantization step (for example, a normal quantization step) than the normal one in order to make the compression rate of the recompression equal to the compression rate of the image currently being recorded. 2 times quantization step) is applied.
Of course, the present invention is not limited to the case where the quantization step is doubled.
Other than double may be used.

The image data currently being recorded and the image data to be recompressed are quantized by the quantization circuit 16 in the time-division processing as described above, and the variable-length encoding circuit 20 and the formatting circuit The data is written to the semiconductor memory 24 through the memory 22.

FIG. 5 is a conceptual diagram showing how the free space of the semiconductor memory 24 is increased by the recompression process. FIG.
(1) is before recompression, and (2) is after recompression. A is the image data before the recompression processing, and B is the image data after the recompression processing. Due to the recompression process, the data amount is reduced, and the free space is increased. C is image data recorded by a recording process performed in parallel with the recompression process.
The compression ratio of the image data C is the same as the compression ratio of the recompressed image data B.

Since the image data is managed by the memory control circuit 26 in units of one frame or smaller, it is not necessary for the image data B and C to be continuously arranged on the semiconductor memory 24.

As described above, even during the recording processing of the input image, the already recorded image is recompressed at a higher compression rate and rerecorded on the same recording medium, so that the user is troublesome. Without them, more images or longer moving images can be recorded. That is, it is possible to increase the remaining amount of the recording medium.

The compression rate of the re-encoded image data is the same as that of the currently recorded image data, and the entire image has the same compression rate.

FIG. 2 is a schematic block diagram showing the configuration of a second embodiment of the present invention. The imaging circuit 52 converts an optical image from the photographing lens 50 into an electric signal and outputs an analog video signal. The A / D converter 54 converts an analog video signal output from the imaging circuit 52 into a digital signal. The switch 56 is normally connected to the a contact, and the A / D converter 54
Output data from the video compression circuit 5 via the switch 56.
8 and compression-coded by a well-known image compression method. For example, a predictive coding method, an orthogonal transform coding method, a variable length coding method, and the like are applied.

The video data compressed by the video compression circuit 58 is applied to the semiconductor memory 60 and written. The memory control circuit 62 controls writing and reading of the semiconductor memory 60. The video data recorded in the semiconductor memory 60 is managed in frame units. The data structure of one frame is, for example, as shown in FIG.
By having addresses (or pointers) to the data of the next frame and the previous frame, each frame does not need to be stored in order.

At the time of reproduction, the operation is as follows. That is,
The data read from the semiconductor memory 60 is applied to a video expansion circuit 66, where the data is expanded. The output of the video decompression circuit 66 is converted into an analog signal by a D / A converter 68 and applied to an electronic view finder 70. As a result, the reproduced video is displayed on the electronic view finder 7.
0 is displayed on the screen.

The system control circuit 72 responds to an instruction input such as recording / reproducing / searching / automatic thinning out from the operating device 74, and the memory control circuit 62 and the image data processing circuit 6
4 and the switch 56 are controlled. System control circuit 7
2 is also connected to the semiconductor memory 6 via the memory control circuit 62.
The remaining amount of 0 is constantly monitored.

When the automatic thinning-out instruction is input to the system control circuit 72 and the remaining amount of the semiconductor memory 60 becomes less than a predetermined value, the processing for thinning out the already recorded image data is automatically executed. When the automatic thinning-out instruction has not been input, the thinning-out processing is not executed even if the remaining amount of the semiconductor memory 60 is low.

When the thinning process of the already recorded image data is performed by the automatic thinning command, the system control circuit 72 executes the image recording process and the thinning process in a time sharing manner. This is basically the same as the embodiment shown in FIG.

The operation of decoding image data already recorded in the semiconductor memory 60, thinning it out, and re-recording it in the semiconductor memory 60 when the remaining amount of the semiconductor memory 60 becomes small during recording of a moving image will be described. I do.

When the remaining capacity of the semiconductor memory 60 becomes, for example, 30% of the whole, the system control circuit 72 includes the switch 56, the memory control circuit 62, and the image processing circuit 64.
Output a thinning command to

The switch 56 is connected to the contact b in response to the thinning command. As a result, the captured image data (output of the A / D converter 54) is applied to the image processing circuit 64 via the switch 56. For example, if image data is recorded at 30 frames / second during normal recording, the image data is applied to the image processing circuit 64 every 1/30 second. The image processing circuit 64 subjects the image data from the switch 56 to the same thinning-out processing as the thinning-out processing of the already recorded image data, and supplies it to the video compression circuit 58.

The memory control circuit 62 reads out the image data already recorded in the semiconductor memory 60 to the video decompression circuit 66 in response to the thinning command from the system control circuit 72. The video expansion circuit 66 expands data from the semiconductor memory 60 and supplies the data to the image processing circuit 64. The semiconductor memory 6 in which the read image data has been recorded
In the recording area of 0, the image data is erased and set to a free area.

The image processing circuit 64 performs a thinning process (for example, thinning out pixels and thinning out frames) on the image data from the video decompression circuit 66 to reduce the amount of image data. Although the motion of the moving image becomes awkward due to the frame thinning, the amount of image data can be significantly reduced. If it is played back as it is, it will be the same as high-speed playback, so information indicating that frames are thinned out is embedded. Thereby, the reproduction speed can be adjusted during reproduction. For example, when the number of frames is reduced to １ ／, each frame may be displayed twice, and control information for that may be embedded instead of the thinned frame.

The process of thinning out the pixel data means lowering the resolution of the image, and this can also reduce the amount of image data without being noticeable. FIG. 6 shows an example of the resolution change. FIG. 6A shows the original image, 640 × 48.
It consists of 0 pixels. FIG. 6 (2) shows an image after the pixels are thinned out, and is composed of 320 × 240 pixels. Considering 2 × 2 4-pixel data as one set, this corresponds to a process of changing the 4-pixel data to 1-pixel data. Specifically, there is a method in which only the upper left one pixel of the 2 × 2 four pixels is left and the other three pixels are discarded. This conceptual diagram is shown in FIG. In addition to this, there is a method in which an average value of 2 × 2 4 pixels is used as a representative value to generate 1-pixel data.

The image data subjected to such thinning processing is compression-encoded by the video compression circuit 58 and re-recorded in the semiconductor memory 60.

In this way, even while a new image is being recorded, the information amount of the image data already recorded can be reduced and re-recorded on the same recording medium, and the remaining amount of the recording medium can be increased. Become. In addition, the image quality of the re-recorded image is the same as the image quality of the image currently being recorded.

[0051]

As can be easily understood from the above description, according to the present invention, during recording of a moving image, the image data already recorded on the recording medium can be changed without interrupting the recording of the moving image. The image can be recompressed with the compression characteristic and re-recorded on the same recording medium, and more images can be recorded on the recording medium without extra work for the user.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a first embodiment of the present invention.

FIG. 2 is a schematic configuration block diagram of a second embodiment of the present invention.

FIG. 3 is a schematic configuration block diagram of a conventional example.

FIG. 4 is a diagram illustrating a data configuration of an image of one frame according to the present embodiment.

FIG. 5 is a schematic diagram illustrating a change in recorded content of a recording medium according to the present embodiment.

FIG. 6 is a schematic diagram of a resolution change in the second embodiment.

FIG. 7 is a schematic diagram illustrating an example of a resolution changing process.

[Explanation of symbols]

 10: Blocking circuit 12: Orthogonal transformation circuit 14: Switch 16: Quantization circuit 18: Quantization step control circuit 20: Variable length coding circuit 22: Formatting circuit 24: Semiconductor memory 26: Memory control circuit 28: Data separation Circuit 30: Variable length decoding circuit 32: Inverse quantization circuit 34: Switch 36: Inverse orthogonal transformation circuit 38: Raster scan processing circuit 40: System control circuit 50: Photographing lens 52: Imaging circuit 54: A / D converter 56: Switch 58: Video compression circuit 60: Semiconductor memory 62: Memory control circuit 64; Image processing circuit 66: Video expansion circuit 68: D / A converter 70: View finder 72: System control circuit 74: Operating device 110 : Blocking circuit 112: Orthogonal transformation circuit 114: Quantization circuit 116: Quantization step Loop control circuit 118: variable length encoder 120: formatting circuit 122: a semiconductor memory 124: data separation circuit 126: a variable length decoding circuit 128: inverse quantizer 130: inverse orthogonal transform circuit 132: raster scan processing circuit

Claims (6)

[Claims] 1. A method for decoding already recorded image data, re-encoding it with different compression characteristics, and re-recording the same recording medium without interrupting the recording of the moving image during recording of the moving image. Characteristic image recording / reproducing device. 2. The image recording and reproducing apparatus according to claim 1, wherein said recording medium is a semiconductor memory. 3. The image recording / reproducing apparatus according to claim 1, wherein a compression rate of re-recording is higher than a previous compression rate. 4. The image recording / reproducing apparatus according to claim 3, wherein the currently recorded image data is recorded in a free area created in the recording medium by re-encoding. 5. The image recording / reproducing apparatus according to claim 3, further comprising means for controlling a compression ratio according to a recordable remaining amount on the recording medium. 6. The image recording / reproducing apparatus according to claim 3, wherein the compression rate at the time of re-recording and the compression rate of the currently recorded image are the same.