JPH10257021A - Synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronization circuit by which an initial synchronizing signal is locked at a high speed while reducing the power consumption and the circuit scale. SOLUTION: In a synchronization circuit, a correlation device 11 and a level detection section 12 calculate an amplitude or a power value being a scalar value from a correlation value between a reception signal for each sample and a spread code, an averaging section 13 calculates a mean value of accumulated results corresponding to the scalar value and the sample, a DPRAM 14 generates an averaged delay profile, a path detection section 15 retrieves a peak from the averaged delay profile, the position of the peak is outputted as a latch timing, a DPLL 16 detects a deviation between the latch timing of the maximum peak and the timing of the spread code for reception to fine- adjust the output timing of the spread code so as to cancel the deviation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a DS-CDMA.
(Direct Sequence Code Division Multiple Access)
Related to the synchronization circuit in the receiver adopting the system,
The present invention relates to a synchronous circuit that can perform initial synchronization at high speed with a circuit that is inexpensive, easy, and has low power consumption.

[0002]

2. Description of the Related Art A conventional synchronous circuit will be described with reference to FIG. FIG. 3 is a schematic block diagram showing a conventional synchronous circuit. A conventional synchronous circuit, as shown in FIG.
A searcher 31, a plurality of spreading code generators 32, and a DLL (Delay
(Locked Loop) 33 and a correlator 34 provided in association with the spreading code generator 32.

[0003] The function of each part will be described in detail below.
In the following description, it is assumed that the spread code length of the received signal is n and the number of oversampling is m. Therefore, the spread code period of the received signal is nxm.

[0004] The searcher 31 is a sliding correlator that outputs a correlation value between a predetermined spreading code and a reception signal, which changes in a spreading code cycle of n × m−1. That is, the spread code of the received signal and the spread code used by the searcher 31 for calculating the correlation value are shifted by one sample per one spread code period.

When the first spread code generator 32a detects the peak of the correlation value output from the searcher 31, it starts to output a spread code that changes in an n × m spread code cycle at that timing. .

When the correlation value peak is further input from the searcher 31 after the first spreading code generator 32a starts outputting the spreading code, the second spreading code generator 32b , N × m. The output of a spreading code that changes in a spreading code cycle is started. Less than,
The third spreading code generator 32c operates similarly.

That is, the first spreading code generator 32a
Will output the spreading code in synchronization with the direct wave,
The second spreading code generator 32b and the third spreading code generator 3
2c outputs a spread code in synchronization with the first and second echoes, respectively.

Further, the spreading code generator 32 finely adjusts the phase of the spreading code to be output by a control signal input from the DLL 33 provided correspondingly.

The DLL 33 receives the input of the received signal and the spread code generator 32 corresponding to the DLL 33, detects a phase difference between the received signal and the spread code of the received signal, and outputs a control signal to the corresponding spread code generator 32. Thus, the phase is adjusted so as to cancel the phase difference of the spread code.

By the operation of the DLL 33, the phase difference between the spread code of the received signal and the spread code output from the spread code generator 32 is finely adjusted, the peak of the correlation value is prevented from attenuating, and the synchronization is maintained. I have to. DLL33
Can be realized by two correlators, respectively.

The correlator 34 has a corresponding spreading code generator 3
2 calculates a correlation value between the spreading code input from 2 and the spreading code of the received signal, and outputs the correlation value to a determination unit that determines a symbol.

Next, regarding the operation of the conventional synchronization circuit, the case where the spread code length of the received signal is n and the number of oversampling is m, that is, the case where the spread code period of the received signal is n × m. An example will be described. First, the searcher 31 calculates a correlation value between a preset spreading code and a spreading code of a received signal while shifting one symbol at a time for one spreading code period.
The peak of the correlation value as the synchronization timing of the spread code is output until the time of × m times elapses.

Then, the first spreading code generator 32a starts outputting a spreading code that changes in the n × m spreading code cycle at the timing of the peak of the correlation value input from the searcher 31 first. Also, the second spreading code generator 32b
Starts the output of the spreading code that changes in the n × m spreading code cycle at the second peak timing of the correlation value input from the searcher 31.

Thus, the first spreading code generator 3
2a is a direct wave, the second spreading code generator is synchronized with the timing of the first echo, and the third spreading code generator 32c is synchronized with the timing of the second echo. , The output of the spreading code that changes.

The correlator 34 calculates a correlation value between the spreading code input from the corresponding spreading code generator 32 and the spreading code of the received signal, and outputs the correlation value to a determination unit for determining symbols. Become like

When the spread code output from the spread code generator 32 deviates from the spread code of the received signal, the DLL
33 detects a phase difference generated by the shift, outputs a control signal to the corresponding spread code generator 32, and adjusts the phase so as to cancel the phase difference of the spread code. In this way, the phase difference of the spread code output from the spread code generator 32 is finely adjusted to maintain synchronization with the spread code of the received signal.

[0017]

However, in the above-mentioned conventional synchronous circuit, the circuit scale and the power consumption are large, and at the time of initial synchronization, the maximum number of transmission symbols before the searcher detects the peak of the correlation value. Since it takes n × m times, when the transmission line fluctuation is fast or the frequency offset between the transmitter and the receiver is large, the synchronization is easily lost and the path may be lost. Drawback is slow.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a synchronous circuit capable of reducing the power consumption and the circuit scale, and at the same time, making it possible to pull in the initial synchronization at a high speed.

[0019]

According to a first aspect of the present invention, there is provided a synchronous circuit for accumulating a correlation value of a received signal in one symbol time in a synchronous circuit, and calculating the accumulated value from a result of the accumulation. It is characterized in that a peak is searched and the maximum peak is set as the synchronization timing, and the pull-in of the initial synchronization can be performed at high speed.

According to a second aspect of the present invention, there is provided a synchronous circuit according to the first aspect, wherein:
It is characterized in that the correlation values of the received signals are accumulated while averaging, and the accumulation result is obtained, so that the initial synchronization can be pulled in at high speed.

According to a third aspect of the present invention, there is provided a synchronous circuit according to the first or second aspect, wherein the synchronous timing is a latch timing for a direct wave. As a result, the initial synchronization can be pulled in at high speed.

According to a fourth aspect of the present invention, there is provided a synchronous circuit for calculating, for each sample, a correlation value between an I-phase signal of a received signal and a predetermined spreading code. A first correlator, a second correlator that calculates a correlation value between the Q-phase signal of the received signal and a preset spreading code for each sample, and a second correlator for each sample from the first and second correlators. A level detection unit that calculates and outputs a specific scalar value for the sample from the correlation value input to the scalar value for the specific sample input from the level detection unit, and a scalar value for the sample that is input from the outside. An averaging unit that calculates an average value of the scalar value of the sample and the averaged accumulation result, and outputs the result as an averaged accumulation result of a new scalar value for the sample; and an input from the averaging unit. Sa A dual port for overwriting the averaged accumulation result of the scalar value for the sample in the corresponding position of the averaged delay profile, which is a set for one symbol time, and updating and storing the averaged delay profile A path for searching for peaks of the averaged delay profile stored in the memory and the dual-port memory, sorting the peaks in the order of magnitude of the searched peaks, and outputting the determined number of peak positions as latch timings; It is characterized by having a detection unit, and can pull in the initial synchronization at high speed.

According to a fifth aspect of the present invention, there is provided a synchronous circuit according to the fourth aspect, wherein:
It has a DPLL that detects a difference between a latch timing for a maximum peak and an output timing of a spread code for despreading a received signal and finely adjusts an output timing of the spread code so as to cancel the shift. As a result, the initial synchronization can be pulled in at a high speed, and the circuit scale can be reduced and the power consumption can be reduced.

[0024]

Embodiments of the present invention will be described with reference to the drawings. Synchronous circuit according to the present invention (this circuit)
Calculates an average of several symbol times of the correlation value between the spreading code and the received signal set in advance and stores it in the memory,
The initial synchronization is acquired from the correlation value stored in the memory, and then only synchronization is maintained for the received signal of the direct wave.This reduces the circuit scale, reduces power consumption, and speeds up the initial synchronization. Can be done.

This circuit will be described with reference to FIG. FIG.
FIG. 3 is a configuration block diagram of the present circuit. FIG. 1 shows first and second correlators 11, a level detector 12, an averaging unit 13,
It comprises a dual port memory (DPRAM) 14 for storing a correlation value for one symbol time for each sample unit, a path detection unit 15, and a DPLL 16.

Hereinafter, each part will be described in detail. The first correlator 11 a calculates a correlation value I between the I-phase signal and a preset spreading code and outputs the correlation value I to the level detector 12. The second correlator 11b calculates a correlation value Q between the Q-phase signal and a predetermined spreading code, and
2 is output.

The level detector 12 calculates the amplitude value A or the power value P (from the following equation 1 or 2) from the correlation values I and Q input from the first and second correlators 11. In the claims, they are collectively referred to as “scalar value” and output to the averaging unit 13.

[0028]

(Equation 1)

[0029]

(Equation 2)

Here, since the correlation value is calculated for each sample, the amplitude value or the power value is also calculated for each sample.

The averaging unit 13 calculates the amplitude value or power value of a specific sample input from the level detection unit 12 and the amplitude value or power value stored in the DPRAM 14 as an accumulation result of the sample within one symbol time. The average value with the power value is calculated, and overwritten and stored as the accumulation result of the sample in the DPRAM 14. here,
The average value may be an exponential weighted average or the like.

The DPRAM 14 stores a set of averaged correlation values for one symbol time (hereinafter, referred to as an “averaged delay profile signal”) in units of samples. By overwriting the accumulation result, the averaged delay profile signal is updated and stored every symbol time.

The path detecting section 15 reads out the averaged delay profile signal from the DPRAM 14, searches for peak samples, sorts the peak samples in descending order of peaks, and sets the time at which the peak was detected as a plurality of latch timings. Output.

The DPLL 16 receives the input of the latch timing (the timing of synchronization with the direct wave) corresponding to the highest peak input from the path detector 15, and outputs the spread code used for despreading the received signal. And finely adjusts the timing at which the spread code used for despreading the received signal is output so as to cancel the deviation.

Next, the operation of this circuit will be described. First and second correlators 11 calculate a received signal, a predetermined spreading code and a correlation value, and an amplitude value or a power value corresponding to the correlation value is calculated by a level detection unit 12, and the DPRAM 1
4 is averaged by the averaging unit 13, and the amplitude value or the power value for one symbol time from which noise has been removed is stored while being updated every symbol time.

After several symbol time has passed, DP
In the RAM 14, an averaged delay profile signal which is an average of the amplitude value or the power value for one symbol time is shaped and stored as shown in FIG. FIG. 2 shows the DP
FIG. 4 is an explanatory diagram illustrating an example of an averaged delay profile signal stored in a RAM 14.

Then, the path detecting unit 15 sets the DPRAM 14
, An averaged delay profile signal is read from the CPU, the sample in which the peak is stored is detected, and the positions of the plurality of samples where the peak is detected are output as latch timings in descending order of the sample.

Then, the DPLL 16 sets the first one of the latch timings (the sample storing the maximum value).
Then, the timing for outputting the spread code used for despreading the received signal is finely adjusted so as to cancel the deviation from the timing for outputting the spread code used for despreading the received signal.

According to this circuit, the pull-in of the initial synchronization is performed by the correlator 11, the level detecting unit 12, the averaging unit 13, and the DPRA.
With M14, within a few symbol hours
Further, since the DLL control is performed by the position of the sample corresponding to the direct wave to protect the synchronization, there is an effect that the initial synchronization can be performed at high speed while reducing the circuit scale and the power consumption.

Although the DPRAM 14 is used here, the present circuit can be realized using a normal RAM. In that case, in addition to the present circuit, a configuration must be added so that the RAM can be referred to by both the averaging unit 13 and the path detection unit 15. A widely known method such as the use of such a method is conceivable, and the description is omitted.

It is conceivable to use an analog digital filter (ADF) as the correlator 11. ADF is described in detail in "Matched Filter LSI for Broadband DS-CDMA", Sawabashi, Adachi, Kotobuki, Zhou, et.al., IEICE, RCS96-01, RCS96-01. Here, the description is omitted. If an ADF is used for the correlator 11, there is an effect that the circuit scale can be further reduced and the power consumption can be further reduced.

[0042]

According to the first to third aspects of the present invention, the correlation value of the received signal in one symbol time is accumulated, the peak is searched from the accumulated result, and the maximum peak is set as the synchronization timing. Since it is a circuit, it takes only a few symbol times for the accumulated result to reach sufficient accuracy,
There is an effect that the pull-in of the initial synchronization can be performed at high speed.

According to the fourth aspect of the present invention, the first and the second
, The level detector, and the averaging unit accumulate the averaged correlation value of the received signal in one symbol time in the dual-port memory while averaging the correlation value, and the result obtained by accumulating the path detector in the dual-port memory , The peak is searched for, and the maximum peak is output as the synchronization timing. Therefore, it takes only several symbol times for the accumulated result to reach sufficient accuracy, and the initial synchronization is performed at high speed. There is an effect that can be.

According to the fifth aspect of the present invention, the DPLL
Detects the difference between the latch timing for the maximum peak input from the path detector and the output timing of the spread code for despreading the received signal, and fine-tunes the output timing of the spread code so as to cancel it. Therefore, in addition to the effect of the invention described in claim 4, the effect of being able to reduce the circuit scale and reduce power consumption by performing synchronization protection only at the latch timing for a direct wave is provided. is there.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of the present circuit.

FIG. 2 is an explanatory diagram illustrating an example of an averaged delay profile signal stored in a DPRAM 14.

FIG. 3 is a schematic configuration block diagram showing a conventional synchronization circuit.

[Explanation of symbols]

11: Correlator, 12: Level detector, 13: Averaging unit, 14: DPRAM, 15: Path detector, 16
... DPLL, 31 ... Searcher, 32 ... Spreading code generator, 33 ... DLL, 34 ... Correlator

Claims (5)

[Claims] 1. A synchronization circuit for accumulating a correlation value of a received signal in one symbol time, searching for a peak from the accumulation result, and setting a maximum peak as a synchronization timing. 2. The synchronization circuit according to claim 1, wherein the correlation value of the received signal is averaged and accumulated to obtain an accumulation result. 3. The synchronization circuit according to claim 1, wherein the synchronization timing is a latch timing for a direct wave. 4. A first correlator for calculating a correlation value between an I-phase signal of a received signal and a preset spreading code for each sample, a Q-phase signal of the received signal and a preset spreading code And a second correlator for calculating a correlation value for each sample, and a specific scalar value for the sample is calculated and output from the correlation value input for each sample from the first and second correlators. A level detection unit, calculating a scalar value for a specific sample input from the level detection unit, and calculating an average value of an averaged accumulation result of a scalar value input from outside for the sample; An averaging unit that outputs a new scalar value of the sample as an averaged accumulation result, and an averaged accumulation result of the scalar value of the sample that is input from the averaging unit. A dual-port memory that overwrites the corresponding position of the averaged delay profile, which is a set of data time, updates and stores the averaged delay profile, and searches for the peak of the averaged delay profile stored in the dual-port memory. And a path detector for rearranging the peaks in the order of the magnitude of the searched peaks and outputting the determined number of peak positions as latch timings. 5. A DPLL which detects a difference between a latch timing with respect to a maximum peak and an output timing of a spread code for despreading a received signal, and finely adjusts an output timing of the spread code so as to cancel the shift. 5. The synchronization circuit according to claim 4, comprising: