JPH10256226A - Etching of gan semiconductor layer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for etching an electrically conductive GaN semiconductor layer formed on a substrate in accordance with the design basis. SOLUTION: In this method, when an electrically conductive GaN semiconductor layer 6 formed on a substrate 1 via a buffer layer 5 is etched, a metallic layer 3 is formed in a place, where etching is to be carried out on the substrate 1, and the buffer 5 and the electrically conductive GaN semiconductor layer 6 are formed in this order on the surface of the substrate including this metallic layer 3, and a protecting film 7 is formed in a region 6B, where no etching is to be carried out. Then, electrolytic erosion treatment is carried out by using the electrically conductive GaN semiconductor layer 6, connected to a metal plate 9 as an anode within an alkaline electrolyte solution.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for etching a GaN-based semiconductor layer, and more particularly, to a method for etching a GaN-based semiconductor layer without damaging a substrate by applying a wet etching method. The present invention relates to a method of etching a GaN-based semiconductor layer capable of forming a pattern of (i).

[0002]

2. Description of the Related Art For example, optical devices and electronic devices having various integrated circuit structures are manufactured using GaAs-based III-V compound semiconductors. In that case, first, a GaAs-based semiconductor having a predetermined composition is epitaxially grown on a semi-insulating GaAs single-crystal substrate by applying, for example, the MOCVD method, and then the GaAs-based semiconductor layer is selectively etched. Thus, a desired pattern is formed.

As an etching method at that time, a dry etching method such as reactive ion etching (RIE) or reactive ion beam etching (RIBE) has been widely adopted because highly accurate patterning is possible. I have. Further, the surface of the GaAs-based semiconductor layer is made of Si.
After covering with a protective film such as O ₂ , the protective film is patterned by photolithography, and GaAs exposed from an opening formed in the SiO ₂ protective film is, for example, KOH
In the aqueous solution, the GaAs is used as an anode, a metal bar is used as a cathode, and a DC voltage of, for example, 10 V is applied between the two electrodes to form GaAs.
A wet etching method of etching the s-plane may be applied.

[0004] Comparing the dry etching method and the wet etching method, dry etching is effective in that the pattern accuracy is easily obtained and the etching rate is high, but on the other hand, there is a drawback that the substrate is easily damaged. . Therefore, wet etching is more preferable as an etching method that does not cause damage to the substrate.

Incidentally, as in the above-mentioned GaAs-based semiconductor, it belongs to the group III-V compound semiconductor and has the general formula: I
A GaN-based semiconductor represented by nxAlyGa1-x-yN (0 ≦ x <1, 0 ≦ y <1) has a large band gap and is a direct transition type, and thus a light-emitting element such as a light-emitting diode or a laser diode. , Photodiodes, phototransistors and other light-receiving elements, as well as field-effect transistors and HBs
It is attracting attention as a material for electronic devices such as T.

When a device having an integrated circuit structure is manufactured using this GaN-based semiconductor, the GaN
It is necessary to etch a system semiconductor layer to form a desired pattern there. As a method of etching the GaN-based semiconductor layer, the following wet etching method is conventionally known.

[0007] For example, the proceedings of the 56th Annual Conference of the Japan Society of Applied Physics (August 26-29, 1995)
No. 1, page 246, 27p-ZE-16 includes KOH,
Each alkali aqueous solution prepared by dissolving 20 g of NaOH in 100 cc of water was prepared, and the epitaxial growth layer of GaN was immersed in a mixed solution obtained by mixing aqueous hydrogen peroxide with the aqueous alkali solution, and the strength was 0.6 W / cm ^2. It is disclosed that the GaN is very well etched when irradiated with ultraviolet light.

Further, for example, Japanese Patent Application Laid-Open No. 51-3779 discloses that an etching target GaOH is added to a 0.1N NaOH solution.
A method is disclosed in which an N layer is immersed and electro-eroded at a current density of about 10 mA / cm ² to dissolve the GaN layer. In the case of this electrolytic erosion method, the GaN layer to be etched needs to be conductive, but has an advantage that the etching rate is extremely high as compared with the above another wet etching method. .

[0009]

All of these wet etching methods are effective in that they do not cause damage to the substrate. However, there are the following problems. First, regarding the former wet etching method, recently, GaN
It is pointed out that etching proceeds smoothly when the crystallinity of the crystal is not good (for example, in the case of a polycrystalline structure), but it becomes more difficult as the target GaN approaches the single crystal structure. ing. for that reason,
It is not always effective to apply it to pattern formation of a GaN-based semiconductor layer formed as a single crystal.

In the case of the latter electrolytic erosion method, for example,
It remains unclear whether a conductive GaN-based semiconductor layer formed on an insulating substrate such as a sapphire substrate can be uniformly etched. In particular, how to attach a current-carrying terminal to a conductive GaN-based semiconductor when performing electrolytic erosion remains unknown.

In this regard, the inventor has conducted the following experiment. That is, when a lead wire is simply connected to a part of the conductive GaN layer and electrolytic erosion is advanced in that state, the etching of the portion of the GaN layer to which the lead wire is connected reaches the interface with the substrate. Progress intensively,
A disconnection occurred between the other portions and, as a result, the entire etching was impossible.

Further, when electrolytic erosion is performed in a state where a resist mask pattern is formed on the surface of the conductive GaN layer, the alkaline electrolyte used invades the interface between the GaN layer and the resist mask. As a result, the etching shape of the GaN layer deviated from the design standard, and it was impossible to manufacture a target device. The present invention solves the problem in the method of etching a GaN-based semiconductor layer by electrolytic erosion having the above-described problem while having the advantage that damage to the substrate is not caused, and solves the problem of the conductive layer formed on the substrate. It is an object of the present invention to provide a method capable of etching a conductive GaN-based semiconductor layer according to a design standard.

[0013]

In order to achieve the above object, according to the present invention, when a conductive GaN-based semiconductor layer formed on a substrate via a buffer layer is etched, the conductive GaN-based semiconductor layer is etched on the substrate. A metal layer is formed at a place to be etched in the above, a buffer layer and a conductive GaN-based semiconductor layer are formed in this order on the surface of the substrate including the metal layer, and then the conductive layer is formed in an alkaline electrolyte. There is provided a method for etching a GaN-based semiconductor layer, wherein electrolytic erosion treatment is performed using the GaN-based semiconductor layer as an anode.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The etching method of the present invention will be described below in detail with reference to the drawings. That is, a case where the portion to be etched on the GaN-based semiconductor layer formed on the surface of the substrate 1 is the plane pattern A as shown in FIG. 1 will be described. Here, the pattern A of the portion to be etched is drawn in a predetermined plane pattern on the surface 1a of the substrate 1, and its end extends to the peripheral portion 1b of the substrate 1.

First, a metal layer having a desired plane pattern is formed on a portion to be etched on a substrate.
Specifically, as shown in FIG. 2, a substrate 1 made of an insulating material such as sapphire is prepared, a resist film 2 is formed by covering the entire surface 1a, and then known photolithography is applied. Then, the portion of the resist film 2 corresponding to the portion to be etched is removed, and an opening 2a having a desired plane pattern is formed there.

The plane pattern of the opening 2a shown in FIG. 2 is the same as the pattern A shown in FIG. 1, and extends to the peripheral portion 1b of the surface of the substrate 1. Then, using the remaining resist film 2 as a mask, a metal is vacuum-deposited in the opening 2a, for example, and then the resist film 2 is removed. As a result, as shown in FIG.
A metal layer 3 extending to the peripheral portion 1b and having a plane pattern corresponding to a portion to be etched is formed. The ends of the metal layer extending from the metal layer 3 shown in FIG. 3 and formed on the peripheral portion 1b are indicated by 3a and 3a in FIG. The metal used for forming the metal layer 3 is GaN, which is an etching target described later.
It is preferable that the metal has a relatively large lattice mismatch with the system semiconductor, and examples thereof include Al, Ti, Mo, and Ni.

Then, as shown in FIG. 4, the peripheral portion 1b of the substrate 1 is set in a crystal growth apparatus while being held by a holder 4 made of Mo, for example, and a GaN-based buffer is applied by applying MBE, for example. The layers and the GaN-based semiconductor layers are stacked in this order. At this time, the entire periphery 1b of the substrate and the ends 3a, 3a of the metal layer existing there are covered with the holder 4, so that the buffer layer and the GaN-based semiconductor layer are formed there. Not done.

As a result of this film forming operation, as shown in FIG. 5, on the surface of the substrate 1 excluding the peripheral portion gripped by the holder, the metal layer 3 is covered and the buffer layer 5 is formed. The GaN-based semiconductor layer 6 is formed to cover the buffer layer 5. And the peripheral part 1b of the base material surface
And the portions 3a of the metal layer existing there are exposed as they are.

At the time of this film forming operation, the GaN-based semiconductor growing on the metal layer 3 has a polycrystalline structure. Therefore, in the case of the uppermost GaN-based semiconductor layer 6 in FIG. 5, the region 6A existing on the metal layer 3 has a polycrystalline structure,
The other region 6B, that is, the region where the metal layer 3 does not exist has a single crystal structure. In other words, the uppermost GaN-based semiconductor layer 6 has a planar pattern of the metal layer 3,
That is, the pattern A at the portion to be etched shown in FIG.
Thus, a pattern of a polycrystalline structure is formed.

Next, as shown in FIG. 6, after forming a resist film 2 'by covering the entire surface, the known lithography is applied to form a region 6B of a single crystal structure on the surface of the GaN-based semiconductor layer. Then, a pattern of the opening 2a 'corresponding to the shape of the target device is formed. Next, using the remaining resist film 2 'as a mask, an electrically insulating material such as SiO ₂ or SiN _x is applied to the opening 2a', and then the resist film 2 'is removed.

As a result, as shown in FIG. 7, an electrically insulating protective film 7 is formed at necessary portions in the single crystal structure region 6B of the GaN-based semiconductor layer 6. Subsequently, electrolytic erosion treatment is performed. First, a conductive paint such as a copper paste or dootite is applied with a uniform width while covering the peripheral portion 1b of the substrate 1. At this time, at least the end 3 of the metal layer
a and 3a need to be completely covered with the conductive paint.

If the ends 3a, 3a of the metal layer are not completely covered with the conductive paint and are partially exposed, the exposed portions are dissolved during the electrolytic erosion treatment to be described later, resulting in a disconnected state. This is because electrolytic erosion treatment of the GaN-based semiconductor layer 6 cannot be performed. As a specific application mode, as shown in FIG. 8, the conductive material paint 8 is applied to the end 3 of the metal layer.
It is preferable to bury the layers a and 3a, and to apply them so as to cover the peripheral walls of the buffer layer 5 and the GaN-based semiconductor layer 6. Further, as shown by the imaginary line in FIG. 8, the coating may be performed so that the surface of the peripheral portion of the GaN-based semiconductor layer 6 is overcoated.

Then, as shown in FIG. 9, a conductive metal plate 9 made of, for example, Al, Cu, or stainless steel is adhered to the conductive paint 8. As a result, the metal plate 9 forms a conductive relationship with the edges 3a, 3a of the peripheral metal layer via the conductive paint, and the edges 3a, 3a of the metal layer are extended by the metal layer 3. Therefore, a conductive relationship is formed with the buffer layer 5 and the GaN-based semiconductor layer 6 via the metal layer 3. That is, a conductive relationship is formed between the metal plate 9 and the buffer layer 5 and the GaN-based semiconductor layer 6.

The surface of the metal plate 9 excluding the conductive portion with the conductive paint 8 is coated with an electrically insulating paint such as wax or Teflon as a sealant so as to be used during the electrolytic erosion treatment described later. Corrosion resistance and electrical insulation to the electrolytic solution used are provided. In this state, the whole is immersed in an alkaline electrolyte, the above-mentioned metal plate 8 is connected to a positive electrode of a power source to serve as an anode, and an insoluble electrode such as a Pt electrode is arranged facing the GaN-based semiconductor layer 6. It is used as a cathode, and a predetermined voltage is applied between the two electrodes to conduct electricity.

As the alkaline electrolyte used, for example, K
Suitable examples include an OH aqueous solution and an NaOH aqueous solution, and the temperature of the electrolytic solution is preferably about 20 to 50 ° C. Further, the voltage applied between the two electrodes changes depending on the concentration of the alkaline electrolyte to be used. For example, when electrolytic corrosion is performed at room temperature using a 0.7N KOH aqueous solution, 10 to 10 What is necessary is just about 20V.

By this electrolytic erosion treatment, electrons from the cathode intensively flow into the surface of the GaN-based semiconductor layer 6 facing the cathode, oxidize the flow-in portion, and dissolve the portion. Then, electrons do not flow into the region 6B of the single crystal structure of the GaN-based semiconductor layer covered with the protective film 7 due to the action of the protective film 7, and thus remain without being dissolved. However, the region other than the region 6B receives electrons from the cathode and has a polycrystalline structure due to the effect of the metal layer 6 located therebelow. Advances. Irradiation with ultraviolet rays at this time is preferable because electrolytic erosion effectively proceeds.

Finally, in the region 6A, the lowermost metal layer 3 is also electrolytically eroded. As a result, as shown in FIG. 10, the target pattern is not formed on the surface 1a of the substrate 1. As a result, the buffer layer 5 and the GaN-based semiconductor layer 6 having a single crystal structure, which is an epitaxial growth layer located thereon, are left. Then, by removing the uppermost protective film 7, a device using the GaN-based semiconductor layer 6 having a single crystal structure can be manufactured.

[0028]

EXAMPLE Using a sapphire substrate, as shown in FIG. 3, a 50 nm thick Al
A layer was formed. Then, about 2 mm of the peripheral portion 1b of the substrate 1 is gripped by a Mo holder 4 as shown in FIG.
First, dimethylhydrazine (5 × 10 ⁻⁶ Torr) and metallic Ga (5 × 10 ⁻⁷ Torr) at a temperature of 640 ° C.
To form a GaN buffer layer 5 having a thickness of 5 nm, followed by a growth temperature of 850 ° C. and ammonia (5 × 10 ⁻⁶ To
rr), metal Ga (5 × 10 ⁻⁷ Torr) and Si (5 × 10 ⁻⁹ Torr)
An n-type GaN layer 6 having a thickness of 1000 nm was formed using Torr (FIG. 5). Region 6A of n-type GaN layer on Al layer 3
Has a polycrystalline structure, and the other region 6B has a single crystal structure.

[0029] Then, after coating the entire surface with a resist film, an opening is formed in the device creating scheduled point, there is deposited a SiO ₂ with spackling method, followed by protection by removing the resist film film 7 was formed (FIGS. 6 and 7). Then, doitite (conductive paint made by Fujikura Kasei Co., Ltd.) 8 is completely buried in the peripheral portion 1b of the substrate 1, and the edges 3a of the Al layer are completely buried. After being applied so as to be covered to a certain extent, a donut-shaped Al disk 9 was bonded thereto (FIGS. 8 and 9). In addition, Al
The disk 9 has an aluminum oxide film formed on the surface other than the bonding portion with the dootite 8.

On the other hand, KOH5 was added to 200 ml of deionized water.
g was dissolved to prepare a 0.7N KOH aqueous solution, into which the substrate with the Al disk shown in FIG. 9 was immersed, and the Al disk was connected to the positive electrode of the power supply. A Pt electrode was arranged facing the GaN layer 6 and connected to the negative pole of the power supply. Then, the voltages shown in Table 1 were respectively applied between the two electrodes to perform the electrolytic erosion treatment for 10 minutes. After 10 minutes, the substrate is taken out, and A at the center and the periphery of the substrate is removed.
The etching depth on the l layer was measured. The results are shown in Table 1.

The n-type GaN located under the protective film 7
Layer 6 remained unetched.

[0032]

[Table 1] In addition, while the applied voltage between both electrodes was kept constant at 10 V, the processing time was varied as shown in Table 2, and the etching depth was measured. The results are shown in Table 2.

[0033]

[Table 2]

As is clear from the table, for example, by applying an applied voltage of 20 V for 20 minutes, the GaN-based semiconductor layer (polycrystalline structure region) formed at the position where the metal layer is patterned on the substrate is removed. Etching and removal can be performed according to the pattern of the metal layer to leave a region having a single crystal structure.

[0035]

As is apparent from the above description, according to the method of the present invention, the GaN-based semiconductor layer formed by the epitaxial growth method is uniformly etched in a desired pattern by the electrolytic erosion method which is one of the wet etching methods. can do.
In the method of the present invention, the problem of damage to the substrate does not occur because the wet etching method is applied without using a high energy beam such as RIE or RIBE.

Therefore, the method of the present invention is effective when applied to the production of high-quality devices using GaN-based semiconductors.

[Brief description of the drawings]

FIG. 1 is a perspective view showing an example of a substrate.

FIG. 2 is a cross-sectional view showing a state where an opening of a resist film for forming a metal layer is formed on the surface of the substrate.

FIG. 3 is a cross-sectional view showing a state where a metal layer pattern is formed on a substrate surface.

FIG. 4 is a cross-sectional view showing a state where a substrate is held by a holder.

FIG. 5 is a cross-sectional view showing a state where a buffer layer and a GaN-based semiconductor layer are formed by covering a metal layer.

FIG. 6 is a cross-sectional view showing a state in which an opening is formed in a resist film formed on a GaN-based semiconductor layer.

FIG. 7 is a cross-sectional view showing a state in which a protective film is formed in a single crystal structure region of a GaN-based semiconductor layer.

FIG. 8 is a cross-sectional view showing a state where a conductive paint is applied to a peripheral portion of the substrate.

FIG. 9 is a cross-sectional view showing a state where a metal plate is attached to a substrate.

FIG. 10 is a cross-sectional view showing a state in which a GaN-based semiconductor layer on a metal layer is electrolytically eroded and removed by etching.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 1a Surface of substrate 1 1b Perimeter of substrate 1 2, 2 'Resist film 2a, 2a' Opening 3 Metal layer 3a Edge of metal layer 4 Holder 5 Buffer layer 6 GaN-based semiconductor layer 6A GaN-based semiconductor layer 5 Polycrystalline structure region 6B Single crystal structure region of GaN-based semiconductor layer 5 7 Insulating protective film 8 Conductive paint 9 Metal plate

Claims (1)

[Claims] When etching a conductive GaN-based semiconductor layer formed on a substrate via a buffer layer,
Form a metal layer on the substrate at the place to be etched,
A buffer layer and a conductive GaN-based semiconductor layer are formed in this order on the surface of the substrate including the metal layer, and then electrolytically eroded in an alkaline electrolyte using the conductive GaN-based semiconductor layer as an anode. A method of etching a GaN-based semiconductor layer.