JPH10255500A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the yield from lowering and a defective product from flowing out into the market by arranging plural didived test areas in which the cell area for test of a read-only memory, which is writable only one time, is divided roughly uniformly on the whole of a main cell area to perform a propriety judgement with high accuracy. SOLUTION: Cells for test 21, 22 and 23 in which a cell part for test 2 is divided into three cell parts are arranged in between main cells 11 and 12, 12 and 13, and 13 and 14 in which a main cell part 1 is divided into four cell parts. Moreover, decoders X11-X14, X21-X23 for selecting respective memory cells of main cells 11-14 and cells for test 21-23 are provided in this device. The criterion of a quality decision is set as to a chip for evaluation by obtaining a correlation with the measured value of the main cell part 1 and the measured value of the cell part for test 2 and by considering the value of the correlation. Next, the cell part for test 2 of a chip under test is tested and the quality decision of the main part 1 of the chip is performed based on the measured value. Thus, the man-hour for setting the criterion value is made reducible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device including a read-only memory (OTPROM) which can be written only once.

[0002]

2. Description of the Related Art Ultraviolet erasable programmable ROM (E)
A PROM is a type of a read-only memory (ROM) that retains its storage by using charges accumulated in a floating gate, and is capable of erasing data by irradiating ultraviolet rays and writing again. OTPROM
Is an EPROM chip enclosed in a package such as a plastic mold without a window for irradiating ultraviolet rays. Therefore, it is not possible to correct data, but it is characterized by a low cost. The OTPROM is widely used as a memory for storing various programs and data because the OTPROM is low-cost in addition to the high degree of integration and the ability to easily cope with a large variety of small quantities, which are features of the EPROM.

A semiconductor integrated circuit device including this type of OPTROM is composed of a main cell which can be actually used by a user and a test cell which is used for quality judgment since an OTPROM cell can be written only once. Sometimes, a predetermined test write is performed on the test cell,
The characteristic value of the main cell is estimated from the measured value, and the quality is determined.

Conventionally, in the OTPROM cell, a test cell is arranged separately from a main cell, for example, at a lower portion, and each is selected by a dedicated decoder.

Referring to FIG. 3, which shows a block diagram of a conventional semiconductor integrated circuit device, the conventional semiconductor integrated circuit device includes a main cell 101, a test cell 102 separately arranged below the main cell 101, Main cell 10
1 and a decoder X102 for the test cell 102.

Next, the operation of the conventional semiconductor integrated circuit device will be described with reference to FIG. 3. First, at the time of testing, a test cell 102 is selected by a decoder X102, and predetermined test data is written. Next, a predetermined measurement is performed on the read data of the test cell,
The measured values of these test cells 102 are obtained. Finally,
From the measured value of the test cell 102, the main cell 101
Are estimated and pass / fail is determined.

In the estimation method, a difference S3 between the measured value S1 of the main cell 101 and the measured value S2 of the test cell 102 is determined in the form of S3 = S1−S2 in a product evaluation stage. At the time of the pass / fail judgment, the value obtained by adding S3 to the measured value ST of the test cell 102 is used as the characteristic value of the main cell 101.

However, when trying to estimate the characteristic value of the main cell 101 from the measured value of the test cell 102, the accuracy is poor, and in some cases, there is a problem that useless decrease in yield and outflow of defective products are caused.

[0009] The reason is that the area of the main cell 101 has become larger as the memory capacity increases. Along with this, dispersion of electrical characteristics due to dispersion of process conditions at the time of manufacturing, that is, variation in electrical characteristic values due to differences in physical memory cell positions due to manufacturing variation has also increased. For example, if there is a difference in the characteristic value between the memory cell edge and the center or between the upper and lower ends, the value of the difference is not always uniform, and differs depending on the manufacturing lot or wafer.

A certain chip used for the characteristic evaluation, that is, the evaluation chip is simply the worst characteristic value at the upper end of the main cell 101 and the characteristic value of the main cell 101 at the lower end where the test cell 102 is arranged. Suppose. At this time, the characteristic difference S3 between the main cell 101 and the test cell 102
Takes a positive value.

At this time, a case is considered in which, contrary to the evaluation chip described above, whether the chip to be tested has the best characteristic value at the upper end of the main cell 101 and the best characteristic value at the lower end is good or bad. If the characteristic value of the main cell 101 is to be estimated by the above evaluation chip, the characteristic value of the test cell 102 becomes S
However, since the characteristic value of the test cell 102 is the same as the worst characteristic value of the main cell 101, S3
Is determined to be a characteristic value worse than the actual value. Therefore, a chip that should be a good product is determined to be a defective product, and useless yield is reduced and the product cost is increased.

Conversely, the evaluation chip has the best characteristic value at the upper end of the main cell 101 and the worst characteristic value at the lower end, and the chip under test has the worst characteristic at the upper end of the memory cell 101 and the best characteristic at the lower end. When the pass / fail judgment is made in the case of, the chip which should be a defective product is determined to be a non-defective product, and the defective product is leaked to the market.

[0013]

In the conventional semiconductor integrated circuit device described above, as the main cell area increases with an increase in the memory capacity, the electrical differences due to physical differences in the positions of the memory cells due to manufacturing variations. Variations in the characteristic values also increase, and the accuracy of estimating the characteristic values of the main cell from the measured values in the test cells away from the main cell area decreases, causing unnecessary yield reduction and outflow of defective products to the market. There were drawbacks.

Considering the characteristic dispersion caused by the difference between the physical positions of the main cell and the test cell requires a large number of evaluation man-hours and man-hours for setting a reference value. However, there is a disadvantage that the possibility of remarkable improvement is low.

An object of the present invention is to solve the above-mentioned drawbacks and to provide an OT
It is an object of the present invention to provide a semiconductor integrated circuit device in which the quality of a PROM is determined with high accuracy and unnecessary reduction in yield and prevention of outflow of defective products to the market are prevented.

[0016]

SUMMARY OF THE INVENTION A semiconductor integrated circuit device according to the present invention includes a read-only memory (OTPROM) which can be written only once, and the OTPROM is used by a user for a main cell area and a test cell area for a characteristic test. Wherein the test cell region is divided into a plurality of divided test cell regions, and each of the plurality of divided test cell regions is arranged substantially uniformly over the entire main cell region. It is.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIG. 1 showing a block diagram of an embodiment of the present invention, a semiconductor integrated circuit device according to the present embodiment shown in FIG. Is divided into four main cells 11, 12, 13, and 14, and the test cell part 2 is divided into three main cells 11 and 1.
2, test cells 21, 22, 23 arranged between 12, 13, and 13, 14, and main cells 11,
Decoders X11, X12, X13, X14 for selecting memory cells 12, 13, and 14;
Decoder X for selecting each of memory cells 1, 2, 23
21, X22 and X23.

Next, the operation of the present embodiment will be described with reference to FIG. 1. The test method is the same as the conventional method. First, the measured value of the main cell unit 1 and the test cell unit A correlation is obtained with the measured value of No. 2 and a reference value for pass / fail judgment is set in consideration of the value. Next, the test cell section 2 of the test target chip is tested, and the quality of the main cell section 1 is determined based on the measured value.

As described above, since the test cell section 2 is divided into the test cells 21 to 23 and divided and arranged in the main cell section 1, the variation of the characteristic value due to the manufacture of the main cell section 1 is reduced. Can be reflected by the measured value in the test cell unit 2. That is, the quality can be determined with high accuracy based on the measured value in the test cell unit 2.

Therefore, it is possible to remarkably reduce the man-hour required for setting the reference values for evaluation and pass / fail judgment. In addition, it is possible to cope with variations in characteristics depending on manufacturing lots.

In the prior art, since the evaluation chip happens to have a large difference in characteristics between the main cell 101 and the test cell 102, an unnecessary margin is applied to the reference value for pass / fail judgment, thereby lowering the product yield. However, by applying the present embodiment, this problem can be prevented and the outflow of defective products to the market can be suppressed.

The conventional test cell 102
If the same area as the corresponding region is set as the test cell section 2 and divided into test cells 21 to 23, the chip area does not increase.

Further, when a test cell area is newly added, the chip size is slightly increased. However, considering the final yield of the product and the required number of man-hours, the result will be more than compensated for, resulting in a disadvantage. I can't get it.

In addition to FIG. 1, it can be easily presumed that test cells can be further arranged at the upper end of the main cell 11 and the lower end of the main cell 14.

Next, referring to FIG. 2 which shows a second embodiment of the present invention by blocks, the difference of the present embodiment shown in this figure from the above-described first embodiment is that a chip is used. A main cell part 3 composed of main cells 31 to 34 and a test cell part 4 composed of test cells 41 to 43 divided in the vertical (column) direction instead of the horizontal (row) direction; Selectors Y31 to Y34, Y41 to Y43 for selecting the divided area main cells 31 to 34 and test cells 41 to 43 of the test cell section 4, and sense amplifiers for amplifying the outputs of the selectors Y31 to Y34, Y41 to Y43. 5 is provided.

The operation of the present embodiment is different from the operation of the first embodiment only in the method of dividing the main cell section 3 and the test cell section 4, and the operation and effect are the same.

Also in the present embodiment, the main cell 31
It can be easily presumed that test cells can be further arranged on the left side of the main cell 34 and on the right side of the main cell 34.

Further, in the first and second embodiments, the number of test cells to be divided and inserted is three, but the number of divisions may be changed or the first and second embodiments may be combined. It can be easily estimated that the main cell is divided vertically and horizontally and test cells are inserted.

[0029]

As described above, in the semiconductor integrated circuit device of the present invention, the test cell area is divided and the test cell area is divided and arranged over the entire main cell area, so that it depends on the variation caused by manufacturing for each product lot. Since the quality judgment can be performed with high accuracy without any problem, there is an effect that it is possible to prevent a useless decrease in yield and an outflow of defective products due to an extra test margin.

Further, there is an effect that the number of steps for setting a reference value for product evaluation or pass / fail judgment can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 3 is a block diagram illustrating an example of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

1, 3 Main cell section 2, 4 Test cell section 5 Sense amplifier 11 to 14, 31 to 34, 101 Main cell 21 to 23, 41 to 43, 102 Test cell X11 to X14, X21 to X23, X101, X102
Decoder Y31-Y34, Y41-Y43 Selector

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (3)

[Claims] 1. A semiconductor integrated circuit device including a read-only memory (OTPROM) that can be written only once, wherein the OTPROM has a main cell area used by a user and a test cell area for a characteristic test. Is divided into a plurality of divided test cell regions, and each of the plurality of divided test cell regions is arranged substantially uniformly over the entire main cell region. 2. Each of N (N is a positive integer) row divided test cell areas obtained by dividing the test cell area in the row direction, and N + 1 row divided main cells obtained by dividing the main cell area in the row direction. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is arranged between each of the regions. 3. M + 1 column-divided main cells obtained by dividing each of the M (M is a positive integer) column-divided test cell regions obtained by dividing the test cell region in the column direction by dividing the main cell region in the column direction. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is arranged between each of the regions.