JPH10247953A - Receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a receiver in which a cause to data mis-discrimination given to a base band signal used for data discrimination of demodulation data to be outputed from the receiver resulting from an offset voltage generated in the inside of the circuit of the receiver and specific to the circuit is avoided. SOLUTION: The receiver is provided with a DC offset voltage output means 100 that outputs a DC offset voltage specific to a reception circuit receiving a signal and which a DC offset voltage cancellation means 101 that cancels a base band signal including the DC offset voltage component generated from a reception signal received by the reception circuit and specific to the reception circuit with the DC offset voltage component outputted from the DC offset voltage output means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver having a configuration in which a baseband signal generated from a received signal is amplified by a variable gain amplifier and influenced by a DC offset voltage component inherent in the receiving circuit included in the baseband signal. Related to receivers.

[0002]

2. Description of the Related Art Today, receivers in wireless communication systems are becoming smaller and lighter. As a small and lightweight receiver, there is a receiver called a direct conversion receiver. The direct conversion receiver directly converts an RF (Radio Frequency) signal received via an antenna into a baseband signal without converting it into an IF (Intermediate Frequency) signal.
There is no need to perform processing such as amplification and filtering of the IF signal, and accordingly, there is an advantage that the required components can be reduced and the receiver can be reduced in size and weight.

FIG. 10 is a diagram of a "direct conversion receiver using baseband AGC", Miyuki Soetani, Takashi Ueno, Hiroshi Tsurumi, IEICE Spring Conference B
-322, 1993. 1 is a configuration diagram of a conventional direct conversion receiver described in FIG.

In FIG. 10, 1 is an antenna, 2 is an amplifier, 3
Is a band-pass filter, and 4a and 4b are mixers. The output signal of the band-pass filter 3 is branched into two and input to one input terminal of each of the mixers 4a and 4b.

6a and 6b are low-pass filters, 8a and 8
b denotes a variable gain amplifier, and output signals of the low-pass filters 6a and 6b are input to one input terminals of the variable gain amplifiers 8a and 8b, respectively.

Further, 10a and 10b are A / D converters,
12 is a data determiner, 13 is the phase of the input signal π
A phase shifter 14 that shifts the phase by 2 is a carrier oscillator. The output signal (carrier signal) of the carrier oscillator 14 is branched into two and input to one input terminal of the mixer 4a and the phase shifter 13, respectively. It has become. Also, the phase shifter 13
(Signal shifted by π / 2) is input to one input terminal of the mixer 4b.

Reference numeral 15 denotes a gain control voltage generator for controlling the variable gain amplifiers 8a and 8b. The gain control voltage generator 15 receives the output signals of the A / D converters 10a and 10b, Output signals (control voltages) from the gain control voltage generator 15 are supplied to the variable gain amplifiers 8a and 8b, respectively.
Input terminals.

Next, the operation of the conventional direct conversion receiver thus configured will be described with reference to FIG.

An RF (Radio Frequency) signal including a baseband signal received via the antenna 1 is amplified at a predetermined fixed amplification factor input to the amplifier 2. Then, the output signal of the amplifier 2 is input to the band-pass filter 3 to remove unnecessary frequency components.

Further, the output signal of the band-pass filter 3 is branched into two, and one of the signals is input to the mixer 4a, where the signal is multiplied by an output signal (carrier signal) from the carrier oscillator 14 as described later. Is done.

Here, the carrier oscillator 14 outputs a carrier signal having the same frequency as the signal received via the antenna 1. Accordingly, the output signal (multiplied signal) of the mixer 4a includes a baseband signal and a signal having a frequency twice as high as the carrier signal frequency (carrier frequency).

On the other hand, the other signal output from the band-pass filter 3 and branched into two is input to the mixer 4b and multiplied with the output signal of the phase shifter 13. The output signal of the mixer 4b is input to a low-pass filter 6b to extract a baseband signal, as described later.

The low-pass filters 6a and 6b are connected to the mixer 4
From the output signals a and 4b, a frequency signal that is twice the unnecessary carrier frequency is removed, and only the baseband signal is output.

The baseband signals output from the low-pass filters 6a and 6b are respectively applied to the variable gain amplifiers 8a and 8a.
8b, and are respectively input to the A / D converters 10a and 10a.
The signal is amplified to an appropriate predetermined amplitude for input to b.

The output signals of the variable gain amplifiers 8a and 8b are
The signals are converted into digital signals by A / D converters 10a and 10b, respectively. The output signals of the A / D converters 10a and 10b are each branched into two, and one of the branched signals is input to the data decision unit 12.

The data decision unit 12 decides the digital data to be output based on these two inputs, and outputs demodulated data from the data decision unit 12 as a result of the decision.

The other signals output from the A / D converters 10a and 10b and further branched and not input to the data decision unit 12 are both gain control voltage generators 1.
5, the gain control voltage generator 15 determines a control voltage serving as a control signal for controlling the gain of the variable gain amplifiers 8a and 8b based on the input signals, and sends the control voltage to the variable gain amplifiers 8a and 8b. Output.

Each of the variable gain amplifiers 8a and 8b controls the control signal (control voltage) of the gain control voltage generator 15.
The gain (amplification rate) is changed in accordance with.

In this case, the gain control voltage generator 15
When the input signal is less than a predetermined value based on the input signal output from / D converters 10a and 10b and further branched, the gains of variable gains 8a and 8b increase. A control signal (control voltage) is output such that the gain of the variable gain amplifiers 8a and 8b decreases when the value exceeds the specified value.

In this manner, the variable gain amplifier 8a sends the signal to the A / D converter 10a and the variable gain amplifier 8b sends the signal to the A / D converter 10a.
The signals output to the / D converters 10b always have a constant amplitude.

The conventional direct conversion receiver is configured as described above. When the direct conversion receiver is used particularly for land-based mobile communication, the distance between the base station and the mobile unit changes greatly. Since the received signal power greatly changes and the received signal power greatly changes due to fading, the gains of the variable gain amplifiers 8a and 8b are amplified to keep the input signal amplitudes of the A / D converters 10a and 10b constant. Rate, for example, 8
It has to be set to a large value of 0 (dB).

However, actually, a DC offset voltage component (hereinafter referred to as DC offset) unique to this circuit is generated inside the low-pass filters 6a and 6b and inside the variable gain amplifiers 8a and 8b, and the variable gain amplifier 8a , 8b are connected to low-pass filters 6a, 6b
And the variable gain amplifiers 8a and 8
There is a DC offset that occurs inside b.

Generally, although the amount of these DC offsets is small, when the maximum gain of the variable gain amplifiers 8a and 8b for amplifying the baseband signal is large, these DC offsets are greatly amplified and the variable gain amplifiers 8a and 8b
And the baseband signals input to the A / D converters 10a and 10b are greatly amplified DC.
Includes offset.

The amplified DC offsets contained in the input signals to the A / D converters 10a and 10b cause erroneous data determination at the subsequent data determination unit 12 and cause a bit error. There is a problem that the rate characteristics deteriorate.

For example, even if the DC offset at the input terminals of the variable gain amplifiers 8a and 8b is only 100 (μV), the maximum gain is 80 (dB) (expressed as 10
^In the case of ^80/20 = 10 ⁴ ), 100 μV × 10 ⁴ = 1 (V) (1) Therefore, at the time of the maximum gain, the A / D converters 10 a and 10
The baseband signal input to 0b contains a very large DC offset of 1 (V) although it is supposed to be several mV if there is no influence of the DC offset.

"Direct conversion receiver of double frequency digital phase shift demodulation method", Masahiro Mimura, Ohba
Motoki, Hasegawa Makoto, Makimoto Mitsuo, Yokozaki Katsushi, IEICE Spring Conference B-211, 1991. 11 shows a conventional direct conversion receiver shown in FIG.

In FIG. 11, as a new configuration with respect to the above-mentioned conventional example, 11a and 11b are high-pass filters, respectively, and the outputs of the variable gain amplifiers 8a and 8b are input to the high-pass filters 11a and 11b, respectively. , 11b output from the A / D converter 10a,
10b.

In such a direct conversion receiver, the high-pass filter 11a inserted between the variable gain amplifier 8a and the A / D converter 10a and the high-pass filter 11a inserted between the variable gain amplifier 8b and the A / D converter 10b. The DC offset is removed by the inserted high-pass filter 11b.

However, the direct conversion receiver shown in FIG. 11 has a problem that a part of the spectrum of the baseband signal is deleted depending on the modulation method as described below.

In the direct conversion receiver shown in FIG. 11, the transmission signal has a frequency shift keying (frequency shim).
This is a configuration of a direct conversion receiver when modulated by a modulation method called ft keying (hereinafter, referred to as FSK modulation).

In the case of FSK modulation, a low-pass filter 6
The spectra of the baseband signals output from a and 6b exist only in the vicinity of, for example, a frequency of several kHz, and do not exist in the vicinity of 0 Hz.

Therefore, the high-pass filters 11a and 11b set to a cutoff frequency of less than several kHz cause the DC
Even if the offset (0 Hz signal) and the low frequency component of less than several kHz are simultaneously removed, the bit error rate characteristics do not deteriorate and there is no problem.

However, when the transmission signal is modulated by a modulation method called phase shift keying (hereinafter, referred to as PSK modulation) mainly used in recent mobile communications, the low-pass filters 6a and 6b are used.
The spectrum of the baseband signal output from
It exists continuously up to z.

Therefore, the high-pass filters 11a and 11b
In this case, not only the DC offset component but also the low frequency components of the baseband signal are removed at the same time, and the baseband signal is distorted and the bit error rate characteristic is deteriorated.

As described above, when the conventional direct conversion receiver is used in a communication system in which the received signal power fluctuates greatly, the bit error rate characteristic deteriorates due to the greatly amplified DC offset. There is.

In the conventional method of removing the DC offset component, the low frequency component is deleted.
When receiving a PSK modulated wave, there is a problem that a part of the spectrum of the baseband signal is also deleted.

[0037]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is an object of the present invention to provide a baseband signal which causes a data error judgment when judging data of demodulated data to be output from a receiver. It is an object of the present invention to obtain a receiver capable of eliminating an offset voltage inherent in the circuit included in the receiver and generated inside the circuit.

[0038]

A receiver according to the present invention receives a phase-shift modulated radio signal, generates a baseband signal, and amplifies the baseband signal in accordance with the power of the radio signal. In a receiver, a DC offset voltage output means for outputting a DC offset voltage specific to a receiving circuit for receiving a signal using means at least equivalent to the means for amplifying the baseband signal, and a DC offset voltage output means for generating the DC offset voltage from a received signal received by the receiving circuit. And a DC offset voltage canceling means for canceling and outputting the DC offset voltage component output from the DC offset voltage output means from the baseband signal containing the DC offset voltage component unique to the receiving circuit.

Further, the DC offset voltage output means includes a DC offset voltage control circuit for determining the magnitude of the DC offset voltage component unique to the receiving circuit based on the output of the DC offset voltage canceling means in a non-communication state. Things.

Further, the DC offset voltage output means is based on an average value of an output of the first DC offset voltage canceling means in a non-speech state and an output of the second DC offset voltage cancellation means in a non-speech state. It includes a DC offset voltage control circuit that determines the magnitude of the DC offset voltage component unique to the receiving circuit.

The DC offset voltage control circuit converts the output result of the DC offset canceling unit from analog to digital.
A D converter, a smoothing circuit for smoothing the output of the A / D converter, and a magnitude of the DC offset voltage of a magnitude that eliminates the influence of the DC offset voltage component unique to the receiving circuit from the output voltage of the smoothing circuit. And a DC offset voltage calculation circuit that calculates the DC offset voltage calculated by the DC offset voltage calculation circuit based on the through signal output from the timing control circuit, and based on the hold signal output from the timing control circuit. A hold circuit for holding and outputting the DC offset voltage calculated last by the DC offset voltage calculation circuit;
And a D / A converter for performing A / A conversion.

Further, the DC offset voltage control circuit includes a determination circuit for determining whether the output result of the DC offset cancellation means is positive or negative, and counts the number of positive or negative determination results output from the determination circuit to determine whether the output result is positive or negative. When the count value reaches a predetermined number, a random fork filter that outputs the determination result of the reached count and starts counting again, and a DC offset voltage component unique to the receiving circuit based on the output of the random fork filter. A voltage adjustment circuit that determines the magnitude of the DC offset voltage to cancel out, and a DC offset voltage determined by the voltage adjustment circuit based on the through signal output from the timing control circuit and output from the timing control circuit A hold circuit that holds and outputs the last DC offset voltage determined by the voltage adjustment circuit based on the hold signal. When, in which the output of the hold circuit constituted by a D / A converter for converting D / A.

The timing control circuit outputs a through signal between immediately after power-on and a predetermined time.

The timing control circuit is adapted to output a hold signal during non-communication.

Further, the DC offset voltage output means is a fixed voltage generation means for generating a predetermined voltage for canceling the DC offset voltage component unique to the receiving circuit.

[0046]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a configuration diagram of a receiver (direct conversion receiver) according to Embodiment 1. FIG.
Medium, 16a, 1
6b is a subtractor, and 18a and 18b are variable gain amplifiers, that is, the variable gain amplifiers 8a, 8b, 18a and 18b are all composed of elements having similar characteristics, and each has a certain input for determining one gain. The gain is determined based on the signal (applied voltage).

The subtracters 16a and 16b subtract output signals of the variable gain amplifiers 18a and 18b (hereinafter referred to as replica DC offsets) from output signals (amplified baseband signals) of the variable gain amplifiers 8a and 8b, respectively. It is designed to output a signal.

Reference numerals 20a and 20b denote offset voltage control circuits. Both offset voltage control circuits 20a and 20b receive the output signals of the subtracters 16a and 16b, respectively, and amplify the signals included in the output signals of the subtracters 16a and 16b. And outputs the voltages E _a and E _b that cancel these DC offsets to 0, respectively, and outputs these voltages based on a timing signal which is an output signal of a timing control circuit described later. E _a , E _b
Are respectively held.

Reference numeral 22 denotes a voltage generator. The voltage generator 22 includes variable gain amplifiers 8a, 8b, 18a, and 18b.
Generate a preset voltage for operating at the maximum gain.

[0050] 23 is a selection switch, based on the H _i-level or L _o level timing signal from the timing control circuit 24 outputs an output signal in the form of the output voltage of the gain control voltage generator 15 (terminal A), One of the output voltages (terminals B), which is the output signal of the voltage generator 22, is selected as a voltage fetch source for determining the gain (amplification factor) of the variable gain amplifiers 8a, 8b, 18a, 18b. ing.

The output voltage selected by the selection switch 23 is output to the variable gain amplifiers 8a, 8b, 18a, 18b.
, And the variable gain amplifiers 8a and 8b are both supplied with low-pass filters 6a and 6b with a gain based on the applied voltage.
The baseband signal which is the output of b is amplified and output.

Further, based on the terminal selected by the selection switch 23, the variable gain amplifiers 18a and 18b also use the offset voltage control circuits 20a and 20b with a gain based on the applied voltage.
b is the output voltage E _a of, and outputs amplify respectively the E _b.

The subtractor 16 includes variable gain amplifiers 18a and 18b and offset voltage control circuits 20a and 20b.
The replica DC offset generation means 100 detects an amplified DC offset included in the output signals a and 16b and generates a replica DC offset for canceling the DC offset to zero.

Further, a DC offset canceling means 101 for performing a process of offsetting these DC offsets to 0 by using the replica DC offsets described above by the subtracters 16a and 16b is provided.

Then, the timing control circuit 24 outputs _Hi
A level or _Lo level timing signal is output to switch and control the operation timing of these means.

Next, Embodiment 1 configured as described above will be described.
Will be described with reference to FIGS. 1 to 4. FIG.

In this receiver, the variable gain amplifiers 8a, 8b, 18a, and 18b are operated at the maximum gain (ie, fixed gain) in the non-reception state immediately after the power is turned on (immediately after the receiver is started). , inside the receiver, such for example, variable gain amplifiers 8a as described above, already been generated voltage to offset the circuit-specific DC offset to zero at the input of the 8b, i.e., the voltage E _a, the E _b The required operation is performed (step 1 in FIG. 2).

Next, after obtaining these voltages E _a and E _b ,
In the control gain of amplifier gain control voltage generator 15 is performed in a normal receiving operation is performed voltages E _a, an operation to cancel the circuit-specific DC offsets are based on E _b respectively (step of FIG. 2 2).

These two operations are switched based on a timing signal output from the timing control circuit 24.

In FIG. 1, when the power is first turned on and the receiver is started, the timing control circuit 24 sets _Hi
The level timing signal is output to the selection switch 23.

The selection switch 23 controls the variable gain amplifiers 8a, 8b, 18a, 18b based on the output signal ( _Hi- level timing signal) of the timing control circuit 24.
The source of the control voltage for determining each gain is selected as the terminal B to which the voltage generator 22 is connected.

Accordingly, the terminal B is selected and the voltages E _a and E
_When determining _b , the variable gain amplifiers 8a, 8b, 1
8a, 18b are all operated at maximum gain (ie, fixed gain).

Here, for example, it is assumed that the maximum gains of these amplifiers are all 80 (dB), and the DC offsets specific to this circuit already generated at the input points of the variable gain amplifiers 8a and 8b are 100 (μV). For example, when all of these amplifiers are operated at the maximum gain, a DC offset of 1 (V) is amplified and included in the output signals of the variable gain amplifiers 8a and 8b according to the above-described equation (1). .

Since the variable gain amplifiers 18a and 18b are also operated at the maximum gain of 80 (dB), the offset voltage control circuits 20a and 20b are controlled by the variable gain amplifiers 8a and 8b.
When b, 18a, and 18b are all operated at the maximum gain, they are included in the output signals of the variable gain amplifiers 8a and 8b due to the respective replica DC offsets output from the variable gain amplifiers 18a and 18b. to offset the circuit-specific amplified DC offset arithmetic unit 16a, and detects the amplified DC offset contained respectively in the output signal of 16b, and these give it to the voltage E _a, the E _b respectively Ask.

The voltages E _a and E _b are held in the offset voltage control circuits 20 a and 20 b respectively when the receiver enters a normal reception state by the output of the timing signal output from the timing control circuit 24 ( Hold).

[0066] Voltage Voltage E _a as described above, after determining the E _b, the timing control circuit 24 the terminal A of the selection switch 23 outputs a timing signal L _o level from the terminal B
To set the receiver to the normal reception state.

[0067] Switching from H _i-level timing signal to L _o level of the timing signal, after the receiver has output a timing signal H _i-level start, as performed after a short time constant predetermined To Therefore, the above-mentioned voltages E _a and E _b are calculated in a short time after the start of the receiver.

[0068] During startup of the receiver, the power is by performing voltage E _a as described above each time turned ON, the operation to obtain the E _b such a short time, the circuit-specific DC offset due to temperature change occurs Even if the amount differs each time the power is turned on, the amplified DC offset included in the output signals of the variable gain amplifiers 8a and 8b can be canceled by the newly obtained replica DC offset.

The above-mentioned operations will be described more specifically with reference to FIGS. FIG. 3 is a configuration diagram around the offset voltage control circuit 20a extracted from FIG.
The offset voltage control circuit 20b has the same configuration and operates in the same manner as the offset voltage control circuit 20a, so the offset voltage control circuit 20a will be described as a representative of both.

As a specific configuration of the offset voltage control circuit 20a according to the first embodiment, for example, the configuration shown in FIG. 4 can be considered.

In FIG. 4, reference numeral 201a denotes an A / D converter.
The output signal of the subtractor 16a is input and A / D converted. 2
A smoothing circuit 02a smoothes (averages) the output signal of the A / D converter 201a to reduce the influence of noise and increases the amplified DC offset included in the output signal of the subtractor 16a. It is to detect with accuracy.

Reference numeral 203a denotes an offset voltage calculation circuit, which is an amplified DC output from the smoothing circuit 202a.
An offset is input, and a voltage Ea serving as _a basis of a replica DC offset necessary for canceling the DC offset to zero is calculated and output.

Reference numeral 204a denotes a hold circuit which outputs an H (timing signal) from the timing control circuit 24.
_{In the case of the i-} level (through signal), the input signal is passed through as it is and output. However, when this timing signal changes to the _Lo level (hold signal), the input signal (voltage) immediately before that time is held (hold). During the reception of the _Lo level signal, the held voltage is continuously output.

Reference numeral 205a denotes a D / A converter, which is the output of the hold circuit 204a, that is, the offset voltage calculation circuit 2
The value (digital value) calculated in step 03a is converted into an analog voltage and output.

In the offset voltage control circuit 20a thus configured, the offset voltage calculation circuit 203a
Calculating the voltage E _a in the following manner.

When the power is turned on and the receiver is started, the DC offset included in the baseband signal is x _a (V), and the variable gain amplifier 18a operates based on the maximum gain based on the output of the voltage generator 22. When the offset voltage control circuit 20a is operating at a fixed gain of 80 (dB) (10 ^80/20 = 10 ^{4 when} expressed as a real number) and the offset voltage control circuit 20a outputs a voltage of a _a (V), the subtractor If the DC offset included in the output signal of 16a is Δ _a (V), equation (2) holds. Δ _a = x _a −10 ⁴ · a _a (2)

Here, the offset voltage calculation circuit 203a
Calculates E _a (V) as a voltage that offsets the detected DC offset to 0, and calculates the offset voltage control circuit 20
Since Δa by outputting E _a (V) in place of the voltage of a _a (V) and (V) to offset from 0 to a, the equation (3) is satisfied in this state. Δ _a = x _a −10 ⁴ · E _a = 0 (3)

Eliminating xa using equations (2) and (3) yields equation (4). ^{_{E a = Δ a / 10 4}} + a a (4)

When the power is turned on and the receiver is started, the output voltage from the offset voltage control circuit 20a becomes a
For _a (V), when it is detected subtractor 16a is amplified DC offset contained in the output signal of the delta _a (V) is, the offset voltage calculating circuit 203a includes a subtractor 16a
The voltage E _a (V) that cancels out the amplified DC offset included in the output signal of (1) to 0 can be obtained by calculation using equation (4). Further, the offset voltage calculation circuit 203a outputs the voltage E _a (V) obtained by the calculation via the hold circuit 204a.

As described above, the receiver according to Embodiment 1
Immediately after the power is turned on and the receiver is started, the variable gain amplifiers 8a, 8a,
The gain of 8a is operated by fixing the maximum gain is determined by the processing described above the voltage E _a required to offset this circuit-specific DC offsets occurring in the circuit to zero.

[0081] When the predetermined time after startup has elapsed, L _o level of the timing signal instead of H _i-level timing signal (through signal) (hold signal) is outputted from the timing control circuit 24, the received machine is switched from a state to obtain the voltage E _a to the normal receiving state.

[0082] When the timing signal output from the timing control circuit 24 is switched from H _i level to L _o level, hold circuit 204a is a voltage E _a, which is calculated by the offset voltage calculating circuit 203a based on the timing signal It is held as a voltage used in a normal reception state.

[0083] In addition, the hold circuit 28a is, while receiving the timing signal of the L _o level, continues to output the voltage E _a that this holding is not performed the calculation of the new voltage E _a.

Therefore, in the normal reception state, the voltage E _a (V) obtained as described above and held in the hold circuit 204 is always applied to the variable gain amplifier 18a.

By shifting to the normal reception state, the gain of the variable gain amplifier 8a also changes based on the control signal from the gain voltage generator 15 according to the power change of the reception signal received via the antenna 1. The baseband signal, which is the output signal of the variable gain amplifier 8a, also includes an amplified DC offset unique to the circuit generated inside the circuit amplified according to the gain.

The variable gain amplifier 18a has the same configuration as that of the variable gain amplifier 8a, and, based on a control signal from the gain voltage generator 15 as in the above-described conventional example,
Since it operates with the same gain as the variable gain amplifier 8a,
The replica DC offset output from the variable gain amplifier 18a increases or decreases in accordance with the change in the gain.
This is an amount that can offset the offset to zero.

[0087] Thus, components of the circuit-specific amplified DC offset in the subtracter 16a with which the voltage E _a as described above and amplified by the variable gain amplifier 18a 0
Therefore, in the normal reception state, even if the gain of the variable gain amplifiers 8a and 18a changes based on the control signal output from the gain control voltage generator 15, the output of the subtractor 16a, that is, A / The amplitude of the input signal to the D converter 10a is D
The value is kept at a constant value where the influence of the C offset is eliminated.

[0088] Incidentally, by subtracting the voltage E _a at the input of the variable gain amplifier 8a, configurations are contemplated to offset the DC offset to zero at the input point of the variable gain amplifier 8a.

[0089] However, in general, since the DC offset generated within the variable gain amplifier varies with gain, in the configuration of subtracting the voltage E _a at the input of the variable gain amplifier 8a, DC offset generated inside the low-pass filter 6a Can be removed, but it cannot remove the DC offset generated inside the variable gain amplifier 8a and changing with the gain.

[0090] In contrast, in the configuration of the first embodiment, since the consist amplifies the voltage E _a variable gain amplifier 18a to subtract from the output signal of the variable gain amplifier 8a, a variable gain amplifier 18a By using an amplifier element equivalent to the variable gain amplifier 8a, the variable gain amplifier 8a,
Since the amount of DC offset generated inside 18a changes according to the change in gain, no matter how the gain changes, the DC offset generated inside variable gain amplifier 8a together with the DC offset output from low-pass filter 6a. The offset can also be offset to zero.

Therefore, according to the first embodiment, only the replica DC offset is subtracted from the baseband signal, so that the spectrum of the baseband signal is not cut off as in the conventional configuration, Offset can be removed. Further, it is possible to eliminate the offset voltage inherent in the circuit of the receiver included in the baseband signal, which is included in the baseband signal and causes the data error determination at the time of the data determination of the demodulated data to be output from the receiver. You can get a receiver.

In the above description, the input signal of the offset voltage control circuit 20a is described as the output signal of the subtractor 16a, but may be the output signal of the A / D converter 10a. In this case, since the A / D converter 201a in the offset voltage control circuit 20a is substituted by the A / D converter 10a, the configuration is simplified.

[0093] Incidentally, the operation of setting the voltage E _a, the E _b, not only performed within a predetermined time immediately after the power supply as described in FIG. 2 ON and turned by the receiver is activated, normal receiving It may be performed at the time of non-reception in the state.

That is, the above-described setting operation of the voltages E _a and E _b performed after the receiver is started immediately after the power is turned on is performed at the operation timing shown in FIG. 5 in the non-reception state between the reception states of the receiver. May also be performed intermittently.

In recent mobile communication systems, the same frequency is used by a plurality of users by time division, and communication is performed only in the assigned time slot, so that there is an idle time for communication.

Using the idle time of this communication, the voltage E
The setting operation of _a and _Eb is performed intermittently. This processing has an advantage that even when the DC offset amount included in the baseband signal changes due to a temperature change or the like, the replica DC offset can flexibly follow the change.

In the second and third embodiments described later, the replica DC offset may be obtained intermittently in the non-receiving state between the receiving states of the receiver.

Embodiment 2 As the configuration of the offset voltage control circuits 20a and 20b shown in FIG. 1 in the first embodiment, a replica DC offset may be generated by employing the following configuration in addition to the configuration shown in FIG. .

FIG. 5 is a configuration diagram of an offset voltage control circuit 20a in a receiver (direct conversion receiver) according to the second embodiment. Offset voltage control circuit 20
Since a and 20b have the same configuration, the first embodiment is also used here.
Similarly, the offset voltage control circuit 20a
Will be described.

In FIG. 5, as a new configuration in the second embodiment, 206a receives the output signal of subtracter 16a, determines whether the input signal is positive or negative, and determines whether the input signal is positive or negative.
It is a comparator that outputs a value signal, either “1” or “0”.

The output signal 207a smoothes (averages) the output signal from the comparator 206a, counts the number of outputs of the output signals "1" and "0", and counts one of the output signals in advance. When a predetermined threshold value is exceeded, a random walk filter (hereinafter referred to as RW) which outputs an output signal which has reached the count number earlier and resets the count and performs a count operation again.
F).

Reference numeral 208a denotes a voltage control circuit for controlling to increase or decrease the voltage for canceling the DC offset to 0 based on the output signal of the RWF 207a.

[0103] configured offset voltage control circuit 20a in this way, when the receiver power in the same manner as the first embodiment is turned ON is activated, the selection switch 23 is in H _i-level from the timing control circuit 24 since selects the terminal B, based on the timing signal, performs the operation of calculating the voltage E _a, as shown below.

The output signal of the subtractor 16a is
a, and the sign is determined. Comparator 206
a is a subtractor 16a if a signal of "1" is output when the input signal is positive and a signal of "0" is output if the input signal is negative.
In the case where the amplified positive DC offset exists in the output signal of the comparator 206a, the output signal of the comparator 206a includes many signals of "1".

Conversely, a negative DC signal is included in the output signal of the subtractor 16.
When an offset exists, the output signal of the comparator 206a contains many signals of "0".

The output of the comparator 206a is the RWF 207a
And is smoothed (averaged) to reduce the influence of noise. At the same time, the RWF 207a uses an internal counter (not shown) to count the number of “1” in the input signal to be equal to or greater than a predetermined threshold value that is ahead of the count of “0”. In this case, "1" is output to reset the internal counter.

Conversely, when the count of the number of "0" in the input signal is equal to or greater than a predetermined threshold value which is earlier than the count of the number of "1", "0" is output. To reset the internal counter.

Therefore, if the output signal from the subtractor 16a contains, for example, a positive DC offset, the output signal from the comparator 206a contains a large number of "1" signals as described above. , RWF 207a outputs a signal of “1”.

The voltage control circuit 208a is connected to the RWF 207a
Is "1", the output signal of the subtractor 16a contains many DC offsets that have not yet been canceled out, so that the output value (the voltage that offsets the DC offsets) is increased.

On the other hand, when the output of the RWF 207a is "0", the output value is reduced because the DC offset is excessively offset in the output signal of the subtractor 16a.

The output voltage from the voltage control circuit 208a is
The signal is input to the D / A converter 205a via the hold circuit 204a, is converted into an analog voltage, and is
8a. Further, the variable gain amplifier 18
a and is subtracted from the baseband signal amplified by the subtractor 16a.

Therefore, when a positive DC offset exists in the output signal of the subtractor 16a, the output from the RWF 207a becomes a signal of "1", so that the voltage control circuit 20
8a increases the output value so that the D / A converter 20
6a also increases, and the output of the variable gain amplifier 18a increases. That is, the amount of replica DC offset subtracted from the baseband signal increases, and the positive DC offset included in the baseband signal approaches zero.

On the other hand, in the output signal of the subtractor 16a, a negative D
When the C offset exists, as in the above case, in this case, “0” is output from the comparator 205a to the RWF 207.
"a" is output from each of the
8a reduces the output value so that the D / A converter 2
05a also decreases, and the output from the variable gain amplifier 18a decreases.

That is, the replica DC offset subtracted from the baseband signal output from the variable gain amplifier 8a decreases, and the negative DC included in the baseband signal is reduced.
The offset approaches zero.

As described in the first embodiment, these processes are repeated while the Hi-level signal is being output from the timing control circuit 24, that is, in a short time after the start of the receiver. The component of the amplified DC offset included in the amplified baseband signal is 0.
Converges to

[0116] When the predetermined time after startup has elapsed, the timing signal output from the timing control circuit 24 from the H _i level is switched to L _o level, the receiver is usually from a state to obtain the replica DC offset The state is switched to the reception state (state in which the DC offset is offset to 0).

[0117] normal receiving state to the switched operation after (voltage voltage E _a, the holding of E _b, the operation of the cancellation or the like of the DC offset) is so similar to that of the first embodiment and a description thereof will be omitted.

As described above, according to the configuration shown in FIG. 5, similarly to the configuration shown in FIG. 3, DC voltage included in the amplified baseband signal output from variable gain amplifier 8a is obtained.
The effect of the offset can be eliminated.

Therefore, according to the second embodiment, since the replica DC offset is simply subtracted from the baseband signal, unlike the conventional configuration, the spectrum of the baseband signal is not cut off, and Offset can be removed. Further, it is possible to eliminate the offset voltage inherent in the circuit of the receiver included in the baseband signal, which is included in the baseband signal and causes the data error determination at the time of the data determination of the demodulated data to be output from the receiver. You can get a receiver.

In the above description, the input signal of the offset voltage control circuit 20a has been described as the output signal of the subtractor 16a, but may be the output signal of the A / D converter 10a. That is, MS of the output signal from the A / D converter 10a
B (most significant bit) takes a value of “1” or “0” in accordance with the sign of the output of the subtractor 16a,
Since the output is the same as that from 6a, the comparator 206a becomes unnecessary and the configuration is simplified.

Embodiment 3 FIG. In Embodiments 1 and 2, the generation of the replica DC offset in the non-receiving state and the offset of the DC offset to 0 in the normal receiving state may be performed by the following configuration.

FIG. 6 is a configuration diagram of a receiver (direct conversion receiver) according to the third embodiment. FIG.
In the third embodiment, the two variable gain amplifiers 18a and 18b used in the first and second embodiments are combined into one variable gain amplifier 18, and the offset voltage control circuits 20a and 20b are also one offset voltage control circuit. 20 together.

An average voltage detector 34 receives the output signals (output voltages) of the subtracters 16a and 16b,
The average voltage of these signals is output. Then, the offset voltage control circuit 20 receives the output from the average voltage detector 34 and adjusts the output voltage E so that the output from the average voltage detector 34 cancels to 0 as in the first and second embodiments. Control.

FIG. 8 is a configuration diagram around the offset voltage control circuit 20 extracted from FIG. As a specific configuration of the offset voltage control circuit 20 according to the third embodiment, for example, the configuration already described in the first embodiment (FIG. 4) or the second embodiment (FIG. 5) can be considered. Here, for convenience of explanation, the internal configuration of the offset voltage control circuit 20 will be specifically described with reference to FIGS. 3 to 7 by specifically taking the configuration shown in FIG. 3 (Embodiment 1) as an example.

In the offset voltage control circuit 20 of the receiver according to the third embodiment, the voltage E is calculated as follows.

After the power is turned on and the receiver is started,
The average voltage detector 34 receives the outputs of the subtracters 16a and 16b and outputs the average voltage of these input signals. That is, the output of the subtractor 16a delta _a, the output of the subtractor 16b delta _b, and the output of the average voltage detector 34 and delta, the average voltage detector 34 calculates and outputs delta according to Equation (5) . _{Δ = (Δ a + Δ b} ) / 2 (5) Then, the output of the average voltage detector 34 is input to the offset voltage control circuit 20.

When the power is turned on and the receiver is started, the DC offsets contained in the two baseband signals input to the subtracters 16a and 16b are x
_a , x _b (V), and the variable gain amplifier 18 operates at a fixed gain of 80 (dB) (10 ^80/20 = 10 ^{4 when} expressed as an exponent) based on the output of the voltage generator 22. let is, when the offset voltage control circuit 20 is outputting a voltage of a (V), a subtracter 16a, 16b DC offset each delta _a contained in the output signal of, delta _b (V)
, Equation (6) holds. Δ _a = x _a −10 ⁴ · a Δ _b = x _b −10 ⁴ · a (6)

Here, if it is assumed that x _a = x _b , then Δ _a = Δ _b from equation (6). _{Therefore, x = x a = x b} , Δ = Δ a = Δ b putting (7), equation (8) holds. Δ = x−10 ⁴ · a (8)

Here, the offset voltage calculation circuit calculates E as a voltage that cancels the detected DC offset to zero.
(V) is calculated and the offset voltage control circuit 20 calculates a
E (V) is output instead of the voltage of (V), and Δ (V) is set to 0.
In this state, equation (9) is established. Δ = x−10 ⁴ · E = 0 (9)

Eliminating x using equations (8) and (9) yields equation (10). E = Δ / 10 ⁴ + a (10)

The offset voltage calculation circuit in the offset voltage control circuit 20 calculates a voltage Δ which is a DC offset when the output voltage of the offset voltage control circuit 20 is a (V).
Using the value of (V), a voltage E (V) serving as a replica DC offset is calculated by Expression (10).

When the power is turned on and the receiver is started, the output voltage from the offset voltage control circuit 20 becomes a
In the case of (V), if the average value Δ (V) of the DC offset, which is the output voltage of the average voltage detector 34 (the average value of the output voltages of the subtracters 16a and 16b), is detected, the offset voltage calculation circuit calculates The voltage E (V) that cancels out the amplified DC offset included in the outputs of the subtracters 16a and 16b to 0 can be obtained by calculation using Expression (10).

Further, the offset voltage calculation circuit outputs the calculated value to the variable gain amplifier 18 via the hold circuit 204a and the D / A conversion circuit 205a.

Thus, the receiver according to Embodiment 3
As in the first embodiment, the gains of the variable gain amplifiers 8 and 18 are fixed to the maximum gain and operated within a predetermined short fixed time immediately after the receiver is turned on and activated, and the circuit is operated. The voltage E required for canceling the internally generated DC offset unique to the circuit to zero is determined by the above-described processing.

[0135] Then, the state when the predetermined time after startup has elapsed, the timing signal L _o level instead of the timing signal H _i level is output from the timing control circuit 24, the receiver for determining a replica DC offset To the normal reception state.

[0136] When the timing signal output from the timing control circuit 24 is switched from H _i level to L _o level, as in the first embodiment, the hold circuit of the offset voltage control circuit 20 based on the reception of the timing signal The voltage E calculated by the offset voltage calculation circuit
(V) is held as a voltage used in a normal reception state.

[0137] In addition, the hold circuit, while receiving the timing signal of the H _i level, the holding voltage E (V) is applied to the variable gain amplifier 18.

The replica DC offset output from the variable gain amplifier 18 is supplied to the subtracters 16a and 16b, respectively, so that the DC offset unique to this circuit as described above is applied to the subtractors 16a and 16b according to the embodiment. Can be canceled in the same way as 1.

In the above description, the variable gain amplifiers 8a, 8a
b included in each baseband signal output from
It is assumed that the C offsets are equal (x _a = x _b ), and that the assumption of equation (7) holds.

In this case, if the voltage E (V) calculated by the equation (10) is output through the D / A converter, the DC offset in the output signals of the subtracters 16a and 16b is completely zero. Can be offset.

However, in general, the assumption that x _a = x _b is often not strictly satisfied due to variations in the characteristics of the elements, etc. Therefore, in the configuration of the third embodiment, the subtractor 16
The DC offset of the outputs of a and 16b cannot be exactly canceled out to zero.

[0142] However, if there is a large difference in value between x _a and x _b, DC offset can be a very small value, practically no problem.

For example, x _a = 1 (V), x _b = 0.9
Considering the case (V), it is as follows. When the maximum gain of the variable gain amplifier 18 is 80 (dB) (expressed as an ^exact number, 10 ^80/20 = 10 ⁴ ) and a = 50 (μV),
Delta _a, delta _b is the equation _{(6), Δ a = 1-10} 4 × 50 × 10 -6 = 0.5 (V) Δ b = 0.9-10 4 × 50 × 10 -6 = 0. 4 (V).

[0144] On the other hand, the average voltage detector 34 output is _{Δ = (Δ a + Δ b} ) /2=0.45 (V) (5).

Therefore, the offset voltage calculation circuit in the offset voltage control circuit 20 calculates the voltage E by the equation (10).
When (V) is calculated, E = 0.45 / 10 ⁴ + 50 × 10 ⁻⁶ = 95 (μV) (8)

Therefore, the output of the offset voltage control circuit 20 is 95 (μV), and the amplified DC offsets contained in the output signals of the subtracters 16a and 16b are respectively 1−10 ⁴ × 95 × 10 ^−6. = 0.05 (V) 0.9−10 ⁴ × 95 × 10 ⁻⁶ = −0.05 (V) (14), which is reduced to a sufficiently small value.

It is clear from the description of the second embodiment that the configuration of the offset voltage control circuit 20 may be a configuration as shown in FIG. Also in this case, the subtractor 1
The amplified DC offset included in the output signals of 6a and 16b can be controlled to a sufficiently small value.

As described above, in the third embodiment, the amplified DC signals included in the two amplified baseband signals, which are the outputs of the quasi-synchronously detected variable gain amplifiers 8a and 8b, are output.
Since the replica DC offset is configured to be generated based on the average value of the offset values, the configuration is as follows.
This can be applied when there is no large difference in the amount of DC offset of each output of the variable gain amplifiers 8a and 8b.

Therefore, according to the third embodiment, only the replica DC offset is subtracted from the baseband signal, so that the spectrum of the baseband signal is not reduced as in the conventional configuration, and Offset can be removed. Further, it is possible to eliminate the offset voltage inherent in the circuit of the receiver included in the baseband signal, which is included in the baseband signal and causes the data error determination at the time of the data determination of the demodulated data to be output from the receiver. You can get a receiver.

Further, the circuit configuration can be reduced by reducing the number of variable gain amplifiers for outputting replica DC offsets and the offset voltage control circuit, which are two required in the first and second embodiments, to one, and forming the same. There is an advantage that can be simplified.

Embodiment 4 For example, the subtractors 16a, 1
If the amplified DC offsets at the input points of the variable gain amplifiers 6a and 6b are known in advance, power is supplied to the input points of the variable gain amplifiers 18a and 18b to cancel these DC offsets to 0, respectively, so that the subtractor 16a , 1
The effect of the DC offset may be eliminated from the output signal of FIG.

FIG. 8 is a configuration diagram of a receiver (direct conversion receiver) according to the fourth embodiment. In the receiver shown in FIG. 8, fixed voltage generators 36a and 36b for generating fixed voltages for canceling their DC offsets to 0 are provided instead of the voltage control circuits 20a and 20b.

The output voltages of the fixed voltage generators 36a and 36b are used in the manufacturing process of the receiver to reduce the DC offset inherent to the circuit included in the output signals of the subtracters 16a and 16b when the receiver is in a normal reception state. Checking in advance, the voltages E _a , E _b
Are determined respectively.

In the first and second embodiments, the voltages E _a and E _{b serving} as replica DC offsets are obtained by calculation. In this case, the replica DC offset fixed and set in advance in the manufacturing process of the receiver is given. Therefore, although it is not flexible to follow the variation of the DC offset with respect to the temperature influence as compared with the first and second embodiments, there is an advantage that the circuit configuration is simplified because no offset voltage control circuit is required.

FIG. 9 shows that the configuration of the third embodiment simplifies the configuration of the first and second embodiments, and
The circuit configuration of FIG. 8 is simply configured by one variable gain amplifier 18 and one fixed replica DC offset generator 36.

In the manufacturing process of the receiver, the output voltage of the fixed voltage generator 36 is obtained by averaging the DC offset inherent in the circuit included in the output signals of the subtracters 16a and 16b when the receiver is in a normal reception state. Voltage E so as to offset to zero
To determine.

Therefore, according to the fourth embodiment, since only the replica DC offset is subtracted from the baseband signal, the spectrum of the baseband signal is not reduced as in the conventional configuration, and the DC spectrum is not reduced. Offset can be removed. Further, it is possible to eliminate the offset voltage inherent in the circuit of the receiver included in the baseband signal, which is included in the baseband signal and causes the data error determination at the time of the data determination of the demodulated data to be output from the receiver. You can get a receiver.

In the third embodiment, the voltage E is calculated by calculation.
Here, since a fixed voltage is applied in advance during the manufacturing process of the receiver, the variation in the DC offset with respect to the temperature effect is less flexible than in the third embodiment. When the DC offset amounts included in the band signals are substantially equal, an offset voltage control circuit is not required, and the configuration shown in FIG. 9 can be applied, so that there is an advantage that the circuit configuration is simplified.

[0159]

According to the present invention, in a receiver for receiving a phase shift modulated radio signal to generate a baseband signal and amplifying the baseband signal in accordance with the power of the radio signal, DC offset voltage output means for outputting a DC offset voltage unique to the receiving circuit using means at least equivalent to the means for amplifying the baseband signal, and DC unique to the receiving circuit generated from the received signal received by the receiving circuit. DC offset voltage canceling means for canceling and outputting the DC offset voltage component output from the DC offset voltage output means from the baseband signal containing the offset voltage component, so that the data judgment of demodulated data to be output from the receiver is provided. In the receiver circuit included in the baseband signal that causes data error determination at the time of It is possible to obtain a receiver capable of eliminating the circuit-specific offset voltage live.

Further, the DC offset voltage output means includes a DC offset voltage control circuit which determines the magnitude of the DC offset voltage component unique to the receiving circuit based on the output of the DC offset voltage canceling means in a non-communication state. Therefore, it is possible to eliminate the offset voltage inherent in the circuit of the receiver included in the baseband signal, which is included in the baseband signal and causes the data error determination when the data of the demodulated data to be output from the receiver is determined. You can get a receiver.

Further, the DC offset voltage output means is based on the average value of the output of the first DC offset voltage canceling means in the non-speech state and the output of the second DC offset voltage cancellation means in the non-speech state. Includes a DC offset voltage control circuit that determines the magnitude of the DC offset voltage component unique to the receiving circuit, so that when determining the data of demodulated data to be output from the receiver, the baseband signal that causes a data error determination , A receiver capable of eliminating the offset voltage unique to the circuit and generated inside the receiver circuit included in the receiver.

The DC offset voltage control circuit performs A / D conversion on the output result of the DC offset canceling unit.
A D converter, a smoothing circuit for smoothing the output of the A / D converter, and a magnitude of the DC offset voltage of a magnitude that eliminates the influence of the DC offset voltage component unique to the receiving circuit from the output voltage of the smoothing circuit. And a DC offset voltage calculation circuit that calculates the DC offset voltage calculated by the DC offset voltage calculation circuit based on the through signal output from the timing control circuit, and based on the hold signal output from the timing control circuit. A hold circuit for holding and outputting the DC offset voltage calculated last by the DC offset voltage calculation circuit;
And a D / A converter for performing A / A conversion. Therefore, when the data of the demodulated data to be output from the receiver is determined, it is necessary to determine whether or not demodulated data is to be output. It is possible to obtain a receiver that can eliminate the generated offset voltage unique to the circuit.

Further, the DC offset voltage control circuit includes a determination circuit for determining whether the output result of the DC offset canceling means is positive or negative, and counts the number of positive or negative determination results output by the determination circuit to determine whether the result is positive or negative. When the count value reaches a predetermined number, a random fork filter that outputs the determination result of the reached count and starts counting again, and a DC offset voltage component unique to the receiving circuit based on the output of the random fork filter. A voltage adjustment circuit that determines the magnitude of the DC offset voltage to cancel out, and a DC offset voltage determined by the voltage adjustment circuit based on the through signal output from the timing control circuit and output from the timing control circuit A hold circuit that holds and outputs the last DC offset voltage determined by the voltage adjustment circuit based on the hold signal. And a D / A converter for D / A converting the output of the hold circuit, so that a baseband signal which causes a data error determination at the time of data determination of demodulated data to be output from the receiver. It is possible to obtain a receiver capable of eliminating an offset voltage inherent in the included receiver circuit generated inside the circuit.

Further, the timing control circuit outputs a through signal between immediately after the power is turned on and before a predetermined time. Therefore, when judging the data of the demodulated data to be output from the receiver, a data error occurs. It is possible to obtain a receiver capable of eliminating an offset voltage inherent in the circuit of the receiver included in the baseband signal that causes the determination and generated inside the circuit.

Since the timing control circuit outputs a hold signal during non-communication, the timing control circuit includes a hold signal in a baseband signal that causes a data error determination when determining data of demodulated data to be output from the receiver. Thus, it is possible to obtain a receiver that can eliminate the offset voltage unique to the circuit generated inside the receiver circuit.

Further, the DC offset voltage output means is a fixed voltage generation means for generating a predetermined voltage for canceling the DC offset voltage component unique to the receiving circuit.
A receiver capable of eliminating an offset voltage inherent in a circuit of a receiver included in a baseband signal which is included in a baseband signal and causes a data error determination when determining data of demodulated data to be output from the receiver. Can be obtained.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a receiver according to Embodiment 1.

FIG. 2 is an explanatory diagram of a receiver according to Embodiment 1.

FIG. 3 is an explanatory diagram of a receiver according to Embodiment 1.

FIG. 4 is an explanatory diagram of a receiver according to Embodiment 1.

FIG. 5 is an explanatory diagram of a receiver according to a second embodiment.

FIG. 6 is an explanatory diagram of a receiver according to a third embodiment.

FIG. 7 is an explanatory diagram of a receiver according to a third embodiment.

FIG. 8 is an explanatory diagram of a receiver according to a fourth embodiment.

FIG. 9 is an explanatory diagram of a receiver according to a fourth embodiment.

FIG. 10 is an explanatory diagram of a conventional direct conversion receiver.

FIG. 11 is an explanatory diagram of a conventional direct conversion receiver.

[Description of Signs] 16a, 16b Subtractor, 18, 18a, 18b Variable gain amplifier, 20, 20a, 20b Offset voltage control circuit, 22 Voltage generator, 23 Selection switch, 24
Timing control circuit, 201a A / D converter, 20
2a smoothing circuit, 203a offset voltage calculation circuit, 204a hold circuit, 205a D / A converter, 206a comparator, 207a random walk filter, 208a voltage control circuit, 34 average voltage detector, 36, 36a, 36b, fixed voltage Generator.

Continued on the front page (72) Inventor Makoto Miyake 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation

Claims (8)

[Claims] 1. A receiver for receiving a phase shift modulated radio signal, generating a baseband signal, and amplifying the baseband signal in accordance with the power of the radio signal, the receiver having a unique reception circuit for receiving the signal. DC offset voltage output means for outputting a DC offset voltage using means at least equivalent to the means for amplifying the baseband signal, and a DC offset voltage component unique to the receiving circuit generated from a received signal received by the receiving circuit. A DC offset voltage canceling means for canceling the DC offset voltage component output from the DC offset voltage output means from the included baseband signal and outputting the offset signal. 2. The DC offset voltage output means includes a DC offset voltage control circuit that determines a magnitude of a DC offset voltage component unique to a receiving circuit based on an output of the DC offset voltage canceling means in a non-communication state. The receiver according to claim 1, wherein: 3. The DC offset voltage output means based on an average value of an output of the first DC offset voltage canceling means in a non-speech state and an output of the second DC offset voltage cancellation means in a non-speech state. The receiver according to claim 1, further comprising a DC offset voltage control circuit that determines a magnitude of a DC offset voltage component unique to the reception circuit. 4. A DC offset voltage control circuit comprising: an A / D converter for A / D converting an output result of a DC offset canceling unit; a smoothing circuit for smoothing an output of the A / D converter; A DC offset voltage calculation circuit that calculates the magnitude of the DC offset voltage from the output voltage of the smoothing circuit to a level that eliminates the influence of the DC offset voltage component specific to the receiving circuit, and a through signal output from the timing control circuit. The DC offset voltage calculation circuit outputs a DC offset voltage calculated based on the DC offset voltage calculated based on the hold signal output from the timing control circuit, and outputs the DC offset voltage calculated last based on the hold signal output from the timing control circuit. And a D / A converter for D / A converting the output of the hold circuit. The receiver according to claim 2. 5. A DC offset voltage control circuit, comprising: a determination circuit for determining whether the output result of the DC offset canceling means is positive or negative; and counting the number of positive or negative determination results output by the determination circuit to determine whether the output result is positive or negative. When the count value of the random fork filter reaches a predetermined number, a random fork filter that outputs the determination result of the reached count and starts counting again, and a DC offset voltage unique to the receiving circuit based on the output of the random fork filter A voltage adjustment circuit that determines the magnitude of the DC offset voltage to a magnitude that cancels out the components; and a DC offset voltage determined by the voltage adjustment circuit based on a through signal output from the timing control circuit, and the timing control circuit. The voltage adjustment circuit holds and outputs the last determined DC offset voltage based on the hold signal output from 4. The receiver according to claim 2, further comprising a hold circuit, and a D / A converter for D / A converting an output of the hold circuit. 6. The receiver according to claim 4, wherein the timing control circuit outputs a through signal between immediately after power-on and a predetermined time. 7. The receiver according to claim 4, wherein the timing control circuit outputs a hold signal during non-communication. 8. The receiver according to claim 1, wherein the DC offset voltage output means is a fixed voltage generation means for generating a predetermined voltage for canceling a DC offset voltage component unique to the receiving circuit. .