JPH10243404A - Motion vector detector and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a motion vector detector by which a motion vector in the unit of macro blocks and a motion vector in the unit of sub-blocks are obtained with a simpler configuration. SOLUTION: This detector is provided with a plurality of sub-block summing circuits 102a-102d that sum difference absolute values of each picture element obtained by a difference absolute value calculation circuit 101 for each sub- block, a macro block summing circuit 103 that sums the result of sum further, a minimum value decision/motion vector generating circuit 104 to obtain a motion vector based on the calculation result by any summing means, and a control circuit 107 that controls which calculation result is to be used. The difference absolute value for each picture element calculated by the difference absolute value calculation circuit 101 is used to obtain a motion vector in the unit of macro blocks and a motion vector in the unit of sub-blocks so as to eliminate the need for providing separately the difference absolute value calculation circuit 101 to obtain both the motion vectors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion vector detecting device and a recording medium.

[0002]

2. Description of the Related Art In coding a moving image signal, a method of coding a difference between frames by focusing on a high correlation between frames of the moving image signal in order to efficiently compress an amount of information ( Interframe coding) is often employed. That is, one frame is encoded as it is for the first frame in which there is no target frame for which a difference is to be obtained, but for subsequent frames, the encoded information is compared with the immediately preceding frame (reference frame) obtained by further decoding the encoded information. Take the difference,
The difference is encoded.

[0003] However, in this method, the amount of information can be reduced as compared with the case where one screen is directly encoded for all frames. However, the compression of the amount of information is still not enough. Therefore, a method called motion compensation (motion-compensated inter-frame coding) is used in order to more efficiently compress the information amount in consideration of such a case.

[0004] In inter-frame coding without using motion compensation, the difference between frames is calculated at a location where spatial coordinates of both frames to be compared are the same. On the other hand, when motion compensation is used, the spatial coordinates of both frames do not necessarily have to be the same, and the motion of the screen is taken into consideration, and the space between the reference frame and the point where the difference between the frames becomes smaller is considered. The difference is taken. At this time, a motion vector represents a difference between the coordinates of the encoding target portion and the coordinates of the difference portion in the reference frame. This will be described with reference to the drawings.

FIG. 3 is an explanatory diagram of motion-compensated inter-frame prediction and motion vectors. In FIG. 3, reference numeral 301 denotes a reference frame, and 302 denotes a frame to be encoded, in which only the white stars move and the background does not move at all. The encoding target frame 302 is divided into a plurality of small blocks when performing motion compensation inter-frame encoding, and encoding is performed in units of these blocks.

For example, I, which is an encoding standard for moving picture communication,
TU-T Recommendation H. 261 and H.E. In H.263, MPEG1, MPEG2, and MPEG4, which are encoding standards for storing moving images, encoding is performed by dividing the image into 16-pixel units called macroblocks. Reference numeral 303 denotes the encoding target frame 30
2 shows a state in which 2 is divided into a plurality of macro blocks.

[0007] Among the plurality of divided macroblocks of the encoding target frame 303, there is a white star 3
Notice the block 03a. Reference numeral 304 denotes the same reference frame as 301, but the block having the same coordinates as the macroblock 303a is the block of 304a. However, since motion occurs between these frames, the difference in the difference from the macroblock 303a is the smallest in the block located in 304b. At this time, a motion vector is a motion vector 304c representing a difference between the coordinates of the block 304a and the coordinates of the block 304b.

In terms of information compression, the difference between the macroblock 303a in the encoding target frame and the block 304a in the reference frame is encoded, rather than the encoding between the macroblock 303a in the encoding target frame and the reference frame. It is more efficient to encode the difference from the block 304b and the motion vector 304c.

As a method of detecting the motion vector, there is a block matching method as one of the frequently used methods. This means that a search range for detecting a motion vector is set in advance around the position of the coding target block, and the difference between each pixel of the coding target block and each candidate vector within the search range is determined. In this method, the total of the absolute values is calculated, and the candidate block having the minimum total value is adopted as a reference block (corresponding to the block 304b in FIG. 3). This will be described with reference to the drawings.

FIG. 4 is an explanatory diagram of the block matching method. For simplicity, the coding target block is 2 pixels vertically and horizontally, and the search range is a range of +2 pixels in the vertical, horizontal, and horizontal directions around the coding target block. . In FIG.
1 indicates the position of the block to be coded in the frame to be coded, and 402 indicates the search range in the reference frame one frame before. 403 to 427 are blocks for all the candidate vectors in the search range 402. Also, ○
Numerals in parentheses indicate pixel numbers.

In the case of this example, the encoding target block 401
Then, the sum of absolute differences between pixels at corresponding positions between the candidate blocks 403 to 427 in the search range 402 is calculated. Taking the upper left candidate block 403 as an example, | a15-
b1 | + | a16-b2 | + | a21-b7 | + | a22-b8 | Where a ** is the value of the pixel to be coded, b **
Is the value of the reference pixel, and ** corresponds to the pixel number in FIG. The same operation is performed for the other candidate blocks 404 to 427, and the block having the minimum result is adopted as a reference block.

[0012]

In the compression method for obtaining a motion vector as described above, it is conceivable that the motion of an image in a screen is fast. In order to detect a reference block in which the sum of absolute differences for each pixel is as small as possible, the search range may be expanded so that more candidate vectors are included. However, if the search range is widened, the amount of calculation for motion search increases accordingly, and there is a problem that the time required for detecting a motion vector increases.

The present invention has been made to solve such a problem. 261, H .; In coding schemes with motion vector detection such as H.263 and MPEG1, 2, 4, etc., the accuracy of motion vector detection can be improved without increasing the amount of motion search operation (without increasing the time required for operation processing). The aim is to be able to increase.

[0014]

SUMMARY OF THE INVENTION A motion vector detecting apparatus according to the present invention provides a method for detecting a difference between each pixel value in a current block and each pixel value in a reference block candidate block in a motion vector search range. Calculating the absolute value of the difference for each pixel for each sub-block obtained by dividing the block to be encoded into a plurality of blocks, further summing up the sum of the results, and summing the sum for each of the sub-blocks. A motion vector is obtained based on either the result or the sum of all the results.

In another aspect of the present invention, each pixel value in the reference block candidate block is determined according to whether the motion vector in the encoding target block unit or the motion vector in the sub block unit is obtained. Connect the difference absolute value calculation means for each pixel in the encoding target block to the input, or separate only the difference absolute value calculation means in one sub-block in the encoding target block from the others. Switching means for switching between connection and connection.

In another aspect of the present invention, an offset means for adding a predetermined offset when obtaining the motion vector in the sub-block unit, thereby moving a motion vector search range in obtaining the motion vector in the sub-block unit. Is further provided.

According to another aspect of the present invention, each pixel for calculating the absolute value of the difference between each pixel value in the current block and each pixel value in a reference block candidate block in the motion vector search range is calculated. Difference absolute value calculating means, and a plurality of sub-block summing means for summing the difference absolute value for each pixel obtained by the difference absolute value calculating means for each sub-block obtained by dividing the encoding target block into a plurality of sub-blocks A block summing means for summing the respective calculation results in the plurality of sub-block summing means, and determining the reference block based on either the calculation result by the sub-block summing means or the calculation result by the block summing means, A motion vector generating means for obtaining a motion vector; and a control means for controlling the motion vector generating means by a predetermined control signal.

In another aspect of the present invention, each pixel for calculating an absolute value of a difference between each pixel value in a current block and each pixel value in a candidate block of a reference block in a motion vector search range is calculated. Difference absolute value calculating means, and a plurality of sub-block summing means for summing the difference absolute value for each pixel obtained by the difference absolute value calculating means for each sub-block obtained by dividing the encoding target block into a plurality of sub-blocks A block summing means for summing the respective calculation results in the plurality of sub-block summing means, and an input of each pixel value in the candidate block of the reference block, the absolute value of all differences in the encoding target block. A switching means for switching whether to connect the value calculation means or to connect only the difference absolute value calculation means in one of the sub-blocks in the encoding target block separately from the other. A motion vector generating means for determining the reference block based on either the calculation result by the sub-block summing means or the calculation result by the block summing means and obtaining a motion vector; the switching means and the motion vector generating means And control means for controlling the control by a predetermined control signal.

In another embodiment of the present invention, the absolute value of the difference between each pixel value in the current block and each pixel value in a reference block candidate block in the motion vector search range is calculated. A motion vector detection device that determines the reference block based on a result and generates a motion vector, wherein an area having a long distance from the encoding target block in a predetermined rectangular area including the encoding target block position is determined. The calculation is performed using the excluded range as the motion vector search range.

According to another aspect of the present invention, there is provided a motion vector detecting device for generating a motion vector by a block matching method, wherein a plurality of shift registers are connected in series,
Each pixel value in the motion vector search range is sequentially input from the first stage to the last stage of the serially connected shift registers while being input, and the output of each shift register is individually extracted. And a plurality of outputs from the predetermined shift registers in the shift register group, and a plurality of outputs from the predetermined shift registers in the shift register group are selected and selected from among them. And a plurality of selection means for outputting each pixel value in the block to be encoded, and a reference block candidate in the motion vector search range supplied from the selection means or the shift register group. A difference absolute value calculation means for each pixel for calculating a difference absolute value with respect to each pixel value, and a control means for controlling the selection means with a predetermined control signal. And it said that there were pictures.

In another aspect of the present invention, the motion vector search range in which each pixel value is input to the shift register group is set within a predetermined rectangular area including the position of the encoding target block from the encoding target block. Is a range excluding a region where the distance is long.

Further, the recording medium of the present invention calculates the absolute difference between each pixel value in the current block and each pixel value in a reference block candidate block in the motion vector search range. The calculated absolute value of the difference for each pixel is added to each of the sub-blocks obtained by dividing the encoding target block into a plurality, and the sum of the results is further added,
In the motion vector detection device adapted to obtain a motion vector based on either the sum result of each sub-block or the sum result of all of them, a motion vector of the encoding target block unit is obtained or the sub-block unit is obtained. Depending on whether a motion vector is obtained, the connection state of the difference absolute value calculation means for each pixel in the encoding target block with respect to the input of each pixel value in the reference block candidate block is switched, and It is characterized by recording a program for realizing a function of obtaining a motion vector by selecting either the summation result for each block or all the summation results.

In another aspect of the present invention, the motion vector search range is shifted by adding a predetermined offset according to the motion of the image when obtaining the motion vector in sub-block units. A program for causing a computer to further realize a function of reading each pixel value in the program is recorded.

According to another aspect of the present invention, the absolute value of the difference between each pixel value in the current block and each pixel value in a reference block candidate block within the motion vector search range is calculated. In the motion vector detection device that determines the reference block based on a result and generates a motion vector, an area that is far from the encoding target block in a predetermined rectangular area including the encoding target block position is excluded. It is characterized in that a program for causing a computer to realize a function of performing a calculation using the range as the motion vector search range is recorded.

Since the present invention comprises the above technical means, the motion vector for each sub-block is obtained from the calculation results of the plurality of sub-block summing means by using the difference absolute value for each pixel calculated by the difference absolute value calculating means. The motion vector can be obtained, and the motion vector of each macroblock can be obtained from the calculation result of the block summing unit obtained by further summing the sum result of each sub-block. It is possible to obtain both a motion vector and a motion vector for each sub-block. At this time, when obtaining a motion vector for each sub-block, for example, by adding an offset according to the motion of an image, it is possible to move the motion vector search range and perform processing.

According to another feature of the present invention, all difference absolute value calculation means in the current block are connected or
Since switching means for switching whether to connect only the absolute difference value calculating means in one sub-block separately from the other is provided, when obtaining a motion vector in sub-block units,
Each pixel value of the candidate block can be input independently for each sub-block. Thus, for example, even if offsets given to respective sub-blocks are different from each other, it becomes possible to input an appropriate pixel value to each.

According to another feature of the present invention, in a predetermined rectangular area including the position of the block to be coded, the range excluding the area far from the block to be coded is calculated as a motion vector search range. So,
Even if the search range of the rectangular area is expanded more than usual, it is possible to prevent the number of blocks to be subjected to difference absolute value calculation as reference block candidates within the large rectangular area from increasing.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In general, 261, H .; 263
In encoding methods such as MPEG1, MPEG2, MPEG4, and the like, encoding processing after detection of a motion vector (for example, including DCT processing) is performed by dividing a macroblock of 16 pixels vertically and horizontally into 8 sub-blocks called sub-blocks. Is performed in units of In particular, H. In H.263 and MPEG4, not only a motion vector in a macroblock unit but also a motion vector in a subblock unit can be adopted, and the more efficient one can be selected by obtaining both. The motion vector in sub-block units will be described with reference to the drawings.

FIG. 5 is an explanatory diagram of a motion vector in units of sub-blocks. For simplicity, the macroblock to be coded is 4 pixels vertically and horizontally, and the search range is +2 for both the top, bottom, left and right of the macroblock to be coded. It is the range of pixels.
In FIG. 5, reference numeral 501 denotes an encoding target macroblock in the encoding target frame, and reference numeral 502 denotes a search range in units of a macroblock in a reference frame one frame before. Reference numerals 503 to 506 denote sub-blocks obtained by dividing the encoding-target macro block 501 into four, each of which is composed of two pixels vertically and horizontally.

In the case of this example, as for the motion vector in the sub-block unit, when the upper left sub-block 503 is taken as an example, the motion vector is detected for the sub-block 503 in the search range 507 in which +2 pixels are taken up, down, left and right. Results. The method of detecting the motion vector is as described with reference to FIG. Similarly, the motion vectors of the sub-blocks 504 to 506 are the search ranges 50 for those sub-blocks.
8 to 510 are the results of motion vector detection.

Further, H. In H.263 and MPEG4, the center of the search range for detecting a motion vector in units of sub-blocks can be moved by a predetermined amount by adding an offset without making the center of the search target sub-block exactly the same. This will be described with reference to the drawings.

FIG. 6 is an explanatory diagram of motion vector detection when an offset is added to the search range in sub-block units. 6, reference numeral 503 denotes the position of the encoding target sub-block at the upper left shown in FIG. The origin of the search range for detecting the motion vector of the encoding target sub-block 503 is shifted to, for example, the position 601 by adding an offset, and the search range in units of sub-blocks is also adjusted to 6.
02 to the H. 02 position. H.263 and MPEG4 are possible.

Note that the offset value is not limited within the search range 502 for each macroblock.
Depending on the value of the offset, the search range 602 in units of sub-blocks may deviate from the search range 502 in units of macro blocks. According to this, even when the motion of the image is fast and the same image as the image of the encoding target sub-block does not exist within the search range of the original position, the search range is shifted by adding the offset predicted from the motion of the surrounding blocks. Thus, an optimal block in which the same image as the encoding target sub-block exists can be adopted as the reference sub-block.

As described above, H.264, which can also use a motion vector in sub-block units, can be used. H.263 and MPEG4 have only recently been standardized, and at present there are not many products to which they are applied. Therefore, it can be said that how to configure a device for obtaining both the motion vector in the macroblock unit and the motion vector in the subblock unit and selecting the more efficient one will be a future subject.

Therefore, according to the present invention, it is possible to use a motion vector in a unit of a sub-block in consideration of an offset. Prior to the application of H.263 and MPEG4, a first object is to provide a motion vector detection device capable of obtaining a motion vector of a macroblock unit and a motion vector of a subblock unit with a simpler configuration, A first embodiment described below is proposed.

(First Embodiment) FIG. 1 is a block diagram showing a main part of a motion vector detecting device according to a first embodiment. For simplicity, as shown in FIG. It is assumed that the macroblock is 4 pixels vertically and horizontally, and the search range in macroblock units is +2 pixels in both the upper, lower, left, and right directions with respect to the encoding target macroblock.

In FIG. 1, reference numeral 101 denotes a difference absolute value calculation circuit; 102a to 102d, sub-block summation circuits;
3 is a macroblock summation circuit, 104 is a minimum value determination / motion vector generation circuit, 105a and 105b are frame memories, 106a and 106b are readout circuits,
7 is a control circuit.

The image of the encoding target frame is stored in the first frame memory 105a, and each pixel value (hereinafter referred to as encoding) of the encoding target macroblock is stored in accordance with the address output from the first reading circuit 106a. The target macroblock data is read and supplied to the absolute difference calculation circuit 101. The image of the reference frame one frame before the frame to be encoded is the second frame.
Is stored in the frame memory 105b of the
The respective pixel values within the search range (hereinafter referred to as search data) are read out according to the address output from the readout circuit 106b and supplied to the absolute difference value calculation circuit 101.

In the difference absolute value calculation circuit 101, reference numerals 11a to 11p denote difference absolute value calculation circuits (hereinafter, referred to as PDC) for each pixel, reference numerals 12a to 12g denote multiplexers (hereinafter, referred to as MPX), and reference numerals 13a to 13c denote four. This is a four-stage shift register in which two shift registers are connected in series. The positions of the PDCs 11a to 11p correspond to the positions of the pixels of the encoding target macroblock on the actual screen. Therefore, the portion 14a surrounded by the dotted line in FIG.
１４14d correspond to the positions of the respective sub-blocks in the macroblock.

FIG. 2 shows the internal structure of the PDCs 11a to 11p. In FIG. 2, 201 to 203 are shift registers, and 204 is a calculation circuit. The first shift register 201 holds one pixel of the encoding target macro block data read from the first frame memory 105a. The third shift register 203 holds one pixel of search data sent from various circuits at the preceding stage.

The calculation circuit 204 calculates the absolute difference between the macroblock data A for encoding for one pixel held in the first shift register 201 and the search data B for one pixel held in the shift register 203. The value | AB | is calculated, and the calculation result is stored in the second shift register 202. The absolute value of the difference for one pixel held in the second shift register 202 is calculated by the four sub-block summing circuits 10.
The search data B output to the corresponding circuit out of 2a to 102d and held in the third shift register 203 is output to the next stage at the same timing as when the absolute difference value is output.

Since each of the PDCs 11a to 11p is configured as shown in FIG. 2, in each row in the absolute difference calculating circuit 101, the input search data is sequentially transmitted from right to left. The leftmost PDC11 in the second and subsequent rows from the top
The search data output from c, 11i, and 11k is sent to the right end of the line above it. The three four-stage shift registers 13a to 13c are provided on the input side (right side) of each of the PDCs in the remaining three rows except the bottom row.

In the present embodiment, the search range in the macroblock unit is 8 pixels in the horizontal direction, whereas the size of each candidate block in the search range is 4 pixels in the horizontal direction and 4 pixels smaller than the search range. Therefore, the three four-stage shift registers 13a to 13c provided in each row function as storing search data for four pixels in each row that are not used as pixel values in the candidate block.

Further, the MPX 12a has a sub-block 14
a and the sub-block 14b, and selectively outputs either the output from the PDC 11e or the output from the four-stage shift register 13a. MPX12b
Is between the sub-block 14a and the sub-block 14b, and selectively outputs either the output from the PDC 11g or the output from the second frame memory 105b.

The MPX 12c is a four-stage shift register 13
The output from the PDC 11c and the PDC
11g is selectively output. The MPX 12d is provided in a stage preceding the PDC 11h, and selectively outputs either the output from the four-stage shift register 13b or the output from the second frame memory 105b.

The MPX 12e is located between the sub-block 14c and the sub-block 14d, and selectively outputs either the output from the PDC 11m or the output from the four-stage shift register 13c. MPX12f is between sub-block 14c and sub-block 14d,
Output from PDC 11o and second frame memory 105
b is selectively output.

The MPX 12g is a four-stage shift register 13
c, the output from the PDC 11k and the PDC
Either the output from 11o is selectively output. Each of the MPXs 12a to 12g described above can be switched in accordance with a control signal provided from the control circuit 107. When a motion vector in a macroblock unit is obtained, the upper input is selected. The selection state when obtaining the motion vector in sub-block units will be described later.

Thus, when obtaining a motion vector in units of macroblocks, 16 PDCs 11a to 11p are connected in series via three 4-stage shift registers 13a to 13c, and the search data is PDC11
From p, they are sent to the PDC 11a in the upper left. On the other hand, when obtaining a motion vector for each sub-block, four PDCs are connected in series for each sub-block, and search data for each sub-block is shifted from the lower right PDC of each sub-block to the upper left PDC. It will be sent in order.

Each sub-block summing circuit 102a-102
d calculates the sum of the absolute difference values for each pixel calculated in the corresponding sub-blocks 14a to 14d, and supplies the result to the macroblock summation circuit 103 and the minimum value determination / motion vector generation circuit 104. The macro block summation circuit 103 is provided with each sub-block summation circuit 102a.
A calculation is performed to sum all the absolute values of the differences for each sub-block supplied from to 102 d, and the result is supplied to the minimum value determination / motion vector generation circuit 104.

Minimum value determination / motion vector generation circuit 104
Determines the minimum value among the sums of absolute difference values given for each candidate block from each of the sub-block summation circuits 102a to 102d or the macroblock summation circuit 103. Then, the candidate block having the minimum total value is adopted as a reference block, and a motion vector is generated.

Here, when obtaining a motion vector for each macroblock, one motion vector is obtained using the total value from the macroblock summing circuit 103, and when obtaining a motion vector for each subblock, each subblock summation is obtained. Four motion vectors are obtained using the total value from the circuits 102a to 102d. Minimum value determination / motion vector generation circuit 104
Is controlled by a control signal provided from the control circuit 107.

Next, the operation of the motion vector detecting device according to the present embodiment configured as described above will be described. First, encoding target macroblock data is input from the first frame memory 105a to the absolute difference calculation circuit 101, and the data of each pixel is stored in the corresponding PDC 11a to
It is held in the first shift register 201 in 11p.
The encoding target macroblock data is held in the first shift register 201 as it is during the processing period of the same macroblock.

The input of the macroblock data to be encoded from the first frame memory 105a is performed until the first data arrives at the upper leftmost PDC 11a in FIG. It should just be completed.

Next, a case where data of a search range is input to the difference absolute value calculation circuit 101, and a case where a motion vector is obtained for each macroblock will be described first. In this case, search data in macroblock units is input to the difference absolute value calculation circuit 101. Here, since ± 2 pixels are searched for a macroblock to be coded having 4 pixels vertically and horizontally, the size of search data is 8 pixels vertically and horizontally (5 in FIG. 5).
02).

Further, all the MPXs 12a to 12x in FIG.
In 12g, the upper input is selected according to the control signal from the control circuit 107. Thereby, the four-stage shift registers 13a to 13c in the difference absolute value calculation circuit 101
The PDCs 11a to 11p for each pixel are connected in series from bottom to top on a horizontal row basis and from right to left in each row.

Here, when search data in macroblock units (data within the search range 502 in FIG. 5) is input in raster scan order from the input side of the last row, the first data (pixel number 1 at the upper left of the search range) When the data arrives at the upper left PDC 11a, the upper left candidate block (pixel numbers 1-4, 9-12, 17-20, 25-28)
Is a block composed of 16 pixels, and corresponds to the candidate block 403 in FIG. 4).
11p is input.

At this time, the calculation circuit 204 in each of the PDCs 11a to 11p calculates the absolute value of the difference between the macroblock data to be encoded and the search data in macroblock units for each pixel, and the result is stored in the second shift register. 202
Is held. These absolute differences are calculated for each sub-block 1
Sub-block summation circuit 10 corresponding to each of 4a to 14d
The sums of the absolute values of the differences in sub-block units are obtained by being input to 2a to 102d and summed.

Further, each sub-block summing circuit 102a
The sum of the absolute difference values in sub-block units obtained in steps 102 to 102d is input to the macroblock summation circuit 103 and summed, thereby obtaining the sum of the absolute difference values in macroblock units. The sum of the absolute difference values in macroblock units obtained in this way is input to the minimum value determination / motion vector generation circuit 104 and held in an internal register (not shown).

Next, when the next search data for one pixel is input from the input side of the last row, the next candidate block (candidate block 40 in FIG.
4) is input. In this case as well, the sum of the difference absolute values in the macroblock unit is calculated in the same manner, and this is used as the minimum value determination / motion vector generation circuit 1.
04 is input. Minimum value determination / motion vector generation circuit 1
In step 04, the sum of the difference absolute values input this time is compared with the sum of the difference absolute values held in an internal register (not shown) last time, and the smaller value is held again in the register.

In the same manner, search data is sequentially input from the input side of the last row, and the sum of absolute differences in macroblock units is calculated. By the way, when search data for five pixels is input, counting from the time when the data of the first candidate block is input to each of the PDCs 11a to 11p, five candidate blocks having the same horizontal position (candidate blocks in FIG. 403 to 407) for each PDC 11a
To 11p in order.

When the search data for the next three pixels is input, the calculation of the sum of the absolute difference values is irrelevant. However, when the search data for the subsequent five pixels are sequentially input, the five previously input five search data are obtained. Five candidate blocks (corresponding to candidate blocks 408 to 412 in FIG. 4) whose horizontal position is one pixel lower than the candidate blocks are PDCs 11a to 1a.
1p are sequentially input. By sequentially inputting search data in this way, search data of all candidate blocks is sequentially input to each of the PDCs 11a to 11p.

At this time, the minimum value determination / motion vector generation circuit 104 performs the above-described processing of comparing the magnitude and updating and storing the data in the register every time the sum of the absolute difference values in macroblock units is calculated for each candidate block. Finally, the candidate block having the smallest sum of absolute difference values among the candidate blocks is determined as the reference block. Then, a motion vector corresponding to the determined reference block is generated and output to the outside as a motion vector in macroblock units.

If the origin of the search range for detecting a motion vector in sub-block units is at the same position as the sub-block to be encoded (if there is no offset), the minimum value determination / motion vector generation circuit 104 is
By performing the same processing as the above-described processing in units of macroblocks for each subblock using the sum of absolute differences in units of subblocks obtained by the respective subblock summation circuits 102a to 102d, four subblock units are obtained. Can be obtained.

As described above, when there is no offset related to the search range, it is possible to obtain both the motion vector in the macro block unit and the motion vector in the sub block unit without switching the selection in each of the MPXs 12a to 12g. it can. Therefore, when trying to construct a simple system that does not consider the offset at all, each MPX1
It is not necessary to provide 2a to 12g.

Even if an offset is provided, if the offset is the same in each of the sub-blocks 14a to 14d,
By re-inputting search data in units of macroblocks according to the offset under the control of the second read circuit 106b, it is possible to obtain a motion vector in units of subblocks.

Next, a description will be given of the operation in the case where a motion vector is obtained for each sub-block and the offsets are different from each other in each of the sub-blocks 14a to 14d. In this case, since the search data may be completely different for each sub-block, the search data is input from the second frame memory 105b to the difference absolute value calculation circuit 101 independently for each sub-block. The input of the search data is controlled by the second read circuit 106b.

First, the case where the motion vector of the upper left sub-block 14a is obtained will be described. In this case, MP
X12a, 12b select the lower input, MPX12c
Selects the upper input, other MPX12d ~ 12g
Is unquestioned (don't care). By doing this,
The search data in sub-block units read from the second frame memory 105b is directly input to the PDC 11d, and the search data output from the PDC 11c is the MPX1
2c, input to the PDC 11b via the four-stage shift register 13a and the MPX 12a.

This corresponds to the P and P pixels corresponding to four pixels in the vertical and horizontal directions, which were previously formed when detecting the motion vector in units of macroblocks.
The connection of DCs 11a to 11p is reduced to the connection of PDCs 11a to 11d corresponding to two pixels vertically and horizontally. Therefore, the difference absolute value calculation circuit 101 instructs the search data in sub-block units (± 2 pixels are searched for the encoding target sub-block data of 2 pixels vertically and horizontally, so the size of the search data is 6 pixels vertically and horizontally. 5 is input in a raster scan order, and only the output of the sub-block summation circuit 102a is processed by the minimum value determination / motion vector generation circuit 104, whereby a motion vector in sub-block units can be obtained. it can.

Similarly, a motion vector for each sub-block can be obtained for each of the upper right, lower left, and lower right sub-blocks 14b to 14d. When the motion vector of the upper right sub-block 14b is obtained, MPX
The input on the lower side is selected in 12c and 12d, and the other MPX is not considered (don't care), and only the output of the sub-block summation circuit 102b needs to be processed by the minimum value determination / motion vector generation circuit 104.

When the motion vector of the lower left sub-block 14c is to be obtained, the lower input is selected by the MPXs 12e and 12f, the upper input is selected by the MPX 12g, and the other MPXs are not questioned (don't care). ,
Only the output of the sub-block summation circuit 102c needs to be processed by the minimum value determination / motion vector generation circuit 104.

Further, when the motion vector of the lower right sub-block 14d is obtained, the lower input is selected by the MPX 12g, and the other MPXs are not considered (don't care), and only the output of the sub-block summing circuit 102d is determined. The processing may be performed by the minimum value determination / motion vector generation circuit 104. As described above, it is possible to detect a motion vector in sub-block units for all sub-blocks.

A series of operations described above, that is, the first operation
Of the macroblock data to be encoded from the frame memory 105a of the second frame memory 105b
Of search data from the MPXs 12a to 12g
The selection switching operation and the processing in the minimum value determination / motion vector generation circuit 104 are controlled by the control circuit 107.

The control circuit 107 may be constituted by hardware, but may also be constituted by a microcomputer comprising, for example, a CPU, a ROM and a RAM. In this case, a program describing a sequence for performing a series of processes as described above is stored in the ROM, and a CPU is executed in accordance with the program stored in the ROM.
Works. R storing the work program of this CPU
The OM constitutes the recording medium of the present invention.

A hard disk may be connected to the microcomputer via a peripheral interface, and the work program of the CPU may be stored in the hard disk. The work program can be externally supplied to the hard disk. In this case, a hard disk and a means for supplying the work program, for example, a recording medium storing the work program are also recording media of the present invention. Configure.

As a recording medium for storing the work program, in addition to a ROM and a hard disk, for example, a floppy disk, an optical disk, a magneto-optical disk,
A D-ROM, a magnetic tape, a nonvolatile memory card, or the like can be used.

As described above, according to the present embodiment, the H.264 is used. 2
In an encoding method such as 63 or MPEG4, for example, a motion vector is obtained for each sub-block by adding an offset for each sub-block according to the motion of an image, so that the search range is expanded and the amount of calculation is not increased (the Without increasing the time required for processing), it is possible to increase the detection accuracy of the motion vector and more efficiently compress the information amount.

In the above embodiment, for simplicity of description, the macroblock to be coded is 4 pixels vertically and horizontally, and the search range in units of macroblock is +2 pixels in both the upper, lower, left and right directions around the macroblock to be coded. However, the present invention is not limited to this. As described in the conventional example, H.264. In H.263 and MPEG4, the macroblock to be encoded is actually composed of 16 pixels in the vertical and horizontal directions, so that the PDC, MPX, shift registers, etc. may be configured according to the number.

In the above embodiment, both the outputs of the sub-block summation circuits 102a to 102d and the output of the macroblock summation circuit 103 are input to the minimum value determination / motion vector generation circuit 104, and the minimum value determination / The control circuit 10 determines which information is used in the motion vector generation circuit 104.
7, but the present invention is not limited to this. For example, the control circuit 107 controls each of the sub-block summation circuits 102a to 102d,
The output destination may be switched to the macroblock summation circuit 103 or the minimum value determination / motion vector generation circuit 104.

(Second Embodiment) Next, a second embodiment of the present invention will be described. The present invention relates to the above H.264. 2
H.63, MPEG4, etc. 26
Motion vector detection that can increase the detection accuracy of motion vectors without increasing the amount of operation for motion search even in other encoding methods that do not use motion vectors in sub-block units, such as MPEG1, MPEG1, and MPEG2 For the second purpose of providing an apparatus, a second embodiment described below is proposed.

As described above, if the search range is simply widened in order to increase the accuracy of motion vector detection, the number of candidate vectors increases by that amount, and the amount of calculation for motion search increases. Thus, in the second embodiment, by increasing the search range and selecting candidate blocks within the range, it is possible to suppress an increase in the number of candidate vectors and an increase in the time required for detecting a motion vector. Like that.

FIG. 7 shows that the search range is expanded to 8 pixels vertically and horizontally as compared to the search range of 6 pixels vertically and horizontally shown in the example of FIG. Instead, this is an example in which a block far from the encoding target block is excluded from the candidate blocks.

In FIG. 7, reference numeral 701 denotes the position of an encoding target block of 2 pixels vertically and horizontally in the encoding target frame.
02 indicates a search range of 8 pixels vertically and horizontally in the reference frame one frame before. A range 703 surrounded by a dotted line is a true motion vector search range in which a block far from the coding target block 701 is excluded from the candidate blocks, and reference numerals 704 to 728 denote the motion vector search range 703.
Is a block for all the candidate vectors. The numbers in the circles indicate the pixel numbers.

In FIG. 8, the search range is weighted in the horizontal direction, and instead of expanding the search range to the range of +4 pixels on the left and right with respect to the encoding target block as compared with the example of FIG.
This is an example of a case where a block far from the encoding target block is excluded from the candidate blocks. In the example of FIG. 8, when shooting with a camera to obtain image data, the camera is often moved in the horizontal direction, and the image display screen itself has a horizontally long shape. Is highly correlated.

In FIG. 8, reference numeral 801 denotes the position of an encoding target block of two pixels vertically and horizontally in the encoding target frame.
02 is 6 pixels vertically and 1 horizontally in the reference frame one frame before.
The search range of 0 pixel is shown. In addition, 8 surrounded by a dotted line
A range 03 is a true motion vector search range in which a block far from the encoding target block 801 is excluded from the candidate blocks. Reference numerals 804 to 828 denote blocks for all the candidate vectors in the motion vector search range 803. is there. The numbers in the circles indicate the pixel numbers.

As in the examples of FIGS. 7 and 8, instead of expanding the search range for obtaining a motion vector, candidate blocks within the range are selected to reduce the number of candidate blocks in the case of FIG. It is the same as 25. As a result, the search range can be widened and the detection accuracy of the motion vector can be increased without increasing the amount of calculation in the motion search.

The configuration of the motion vector detecting device according to the second embodiment which can cope with such a search range of a non-square or rectangular motion vector will be described below. FIG.
FIG. 11 is a block diagram showing a main configuration of a motion vector detecting device according to a second embodiment. For simplification, as shown in FIG. In the range of +4 pixels in both the upper, lower, left and right directions around the block (a wider range than in FIG. 5 where the upper, lower, left, and right sides are +2 pixels), it is assumed that a block far from the encoding target block is excluded from candidates. ing.

In FIG. 10, reference numeral 1001 denotes an encoding target block in the encoding target frame, and 1002 denotes a wide search range of +4 pixels in the upper, lower, left, and right directions of the encoding target block in the reference frame one frame before. Is shown. Further, a range 1003 surrounded by a dotted line indicates a true motion vector search range in which a block far from the encoding target block 1001 is excluded from the candidates from the wide search range 1002 described above. The blocks for all the candidate vectors within the motion vector search range 1003 are shown. In the following description, the term “search range” simply refers to a true motion vector search range 1003 in which blocks farther away are excluded from candidates.

In FIG. 9, 901a and 901b are frame memories, 902a and 902b are read circuits, 903 is a difference absolute value calculation circuit, 904 is a shift register group, 905 is a block summation circuit, and 906 is a minimum value determination / motion vector generation. A circuit 907 is a control circuit.

The image of the encoding target frame is stored in the first frame memory 901a, and each pixel value of the encoding target block (hereinafter referred to as encoding target) is stored in the first frame memory 901a according to the address output from the first reading circuit 902a. Block data) is read out and the absolute difference calculating circuit 90 is read out.
3 is supplied. Also, 1 from the above encoding target frame
The image of the reference frame before the frame is stored in the second frame memory 901b, from which each pixel value (hereinafter referred to as search data) within the search range is read in accordance with the address output from the second readout circuit 902b. And supplied to the shift register group 904.

FIG. 11 shows the internal configuration of the difference absolute value calculation circuit 903. In FIG. 11, 1101a to 1101
Reference numeral 11 denotes a multiplexer (hereinafter referred to as MPX), and reference numerals 1102a to 1102p denote difference absolute value calculation circuits (hereinafter referred to as PDC) for each pixel. The above PDC11
The positions 02a to 1102p correspond to the actual pixel positions of the current block on the screen, that is, the positions of the current block 1001 in FIG.

A plurality of output signals from the shift register group 904 are input to the input terminals of the MPXs 1101a to 1101l, and one of them is selected. The selection signals output from the MPXs 1101a to 1101l are provided to the corresponding PDCs 1102a to 1102a, respectively.
It is input to 2l. These MPX1101a
To 1101l are switched according to a control signal given from the control circuit 907.

Out of the 16 PDCs 1102a to 1102p, the 12 PDCs 1102a to 1102l include the output signal (search data) from the shift register group 904 selected by the corresponding MPXs 1101a to 1101l, and The absolute value of the difference from the encoding target block data read from the first frame memory 901a is calculated for each pixel, and the calculation result is calculated by the block summation circuit 905.
To supply.

The remaining four PDCs 1102m to 1102m
An output signal (search data) from the shift register group 904 is directly input to the input terminal 02p. These four PDCs 1102m to 1102p are:
The absolute value of the difference between the search data directly input from the shift register group 904 and the block data to be encoded read from the first frame memory 901a is calculated for each pixel, and the calculation result is sent to the block summation circuit 905. Supply.

Further, the PDCs 1102a to 1102
FIG. 12 shows the internal structure of p. In FIG.
Reference numerals 1 and 1203 are shift registers and 1202 is a calculation circuit. The first shift register 1201 holds one pixel of the encoding target block data read from the first frame memory 901a.

The calculation circuit 1202 calculates the one-pixel encoding target block data A held in the first shift register 1201 and the one-pixel search data B input from the MPXs 1101a to 11011 or the shift register group 904. Is calculated, and the result of the calculation is held in the second shift register 1203. Second
The absolute value of the difference for one pixel held in the shift register 1203 is output to the block summing circuit 905.

Next, the internal configuration of the shift register group 904 is shown in FIG. In FIG. 13, 1301 to 1340
Denotes a shift register, and these forty shift registers 1301 to 1340 are connected in series. In the example of FIG. 13, 36 shift registers 1301 to 13
36 are constituted by three lines such that 12 (corresponding to the maximum number of the search range 1003 in the horizontal direction) are arranged in one line,
The remaining four shift registers 1337 to
1340 is provided.

Since the shift register group 904 is configured as described above, the search data read for each pixel from the second frame memory 901b is sequentially sent from right to left in each line. . The leftmost shift registers 1313, 1325, 1337 after the second from the top
Are sent to the right end of the line above them. As a result, the input search data is sequentially sent from the lower right shift register 1340 to the upper left shift register 1301.

Further, in the process of sequentially sending the search data, the outputs of the shift registers 1301 to 1340 are individually taken out, and the difference absolute value calculating circuit 9 shown in FIG.
MPXs 1101a to 1101l and PDC
The signals are supplied to input terminals of 1102m to 1102p. Here, each shift register 13 in FIG.
01 which is assigned in order from the output closest to the latter stage of 01 to 1340
The numbers 40 to 40 correspond to the numbers 1 to 40 shown in FIG. 11, and the outputs of the shift registers 1301 to 1340 are output from the MPXs 1101a to 1101l and the PDC 11
It is input to the input terminal of the corresponding number from 02m to 1102p.

The block summation circuit 905 is provided for each PDC 11
The sum of the absolute difference values for each pixel calculated in 02a to 1102p is obtained, and the result is supplied to the minimum value determination / motion vector generation circuit 906. The minimum value determination / motion vector generation circuit 906 determines the minimum value from the sum of absolute difference values given from the block summation circuit 905 for each candidate block. Then, the candidate block having the minimum total value is adopted as a reference block, and a motion vector is generated.

Next, the operation of the motion vector detecting device according to the present embodiment configured as described above will be described. First, the encoding target block data is input from the first frame memory 901a to the difference absolute value calculation circuit 903, and the data of each pixel is stored in the corresponding PDC 1102a to
It is held in the first shift register 1201 in 102p. The block data to be encoded remains unchanged during the processing of the same block by the first shift register 1201.
Is held.

The input of the block data to be encoded from the first frame memory 901a is performed until all the search data for the first candidate block is input to the shift register group 904 in the search data described below. It just needs to be completed.

Next, search data is input from the second frame memory 901b to the shift register group 904. Here, the data within the search range 1003 shown in FIG. 10 is read out from the top for each line in the horizontal direction, one pixel at a time from left to right on the same line, and input to the shift register group 904. That is, 1 shown in FIG.
１０４104 are input in the order of the pixel numbers.

FIG. 14 shows the state transition of the shift register group 904 when such search data input processing is continued for pixel numbers 1 to 104. 14, each square square corresponds to each shift register 1301 to 1340 in FIG. The upper numbers separated by diagonal lines in the measure indicate the number of each shift register,
Similarly, the lower numeral indicates the pixel number of the input search data.

That is, as shown in FIGS. 11 and 13, four shift registers 1337 to 1337-1 close to the input stage.
The output of 340 is connected to the PDCs 1102m to 1102p, respectively, and the state when valid search data (search data of blocks that can be adopted as candidate blocks 1004 to 1044 in the search range 1003) is held therein, This is shown at 1401 to 1409 in FIG.

This will be described with reference to FIG. 10. A state 1401 indicates that the calculation for the candidate block 1004 can be performed.
The state 1402 indicates that the calculation for the candidate block 1005 can be performed. Hereinafter, each candidate block 1008, 1013, 1020, 1029, 103
6, 1041, 1044 can be calculated 1403, 1404, 1405, 1406, 140 respectively
7, 1408, and 1049.

In FIG. 14, the shift registers in four continuous cells enclosed by a thick frame are four PDCs continuous in the horizontal direction, that is, PDCs 1102a to 1102.
d, 1102e to 1102h, 1102i to 1102
1, shift registers holding search data respectively input to 1102m to 1102p. For example, 1
In the state 401, the shift registers 1316 to 131
9,1321-1324,1328-1331,133
From 7 to 1340, pixel numbers 1 to 4, 6 to 9, 13 to 1
6, 22 to 25 search data are PDC1102a to 1
102p.

As is apparent from FIG. 14, four Ps
The shift registers holding the search data input to the DCs 1102m to 1102p are fixed to four shift registers 1337 to 1340 close to the input stage in FIG. 13 (for this reason, MPX is not provided correspondingly). On the other hand, the other shift registers that hold the search data input to the PDCs 1102a to 1102l are any of the remaining 36 shift registers 1301 to 1336, and are not fixed (for that reason, the MPX 1101a
１１０1101l are provided correspondingly).

That is, the second frame memory 901b
, The search data is read out pixel by pixel, and sequentially input to the shift register group 904, the pixel numbers 1 to 2
At the time point when the 25 pieces of search data of No. 5 are read out, the state becomes 1401 in FIG. At this point, candidate block 100
For example, shift registers 1316 to 1319 are provided with all search data capable of calculating the absolute value of the difference with respect to No. 4, and hold search data input to the PDCs 1102a to 1102d, for example.

Therefore, the control circuit 907 controls the MPX1
A control signal is generated so as to select the output from the shift register 1316 (the output of number 16) as the output of 101a. MPX1101b to 1101d
So that outputs from the shift registers 1317 to 1319 (outputs of numbers 17 to 19) are respectively selected as outputs of
Generate a control signal.

In the state of 1401 in FIG. 14,
A shift register holding search data input to the PDCs 1102e to 1102h is a shift register 1321.
１３1324. Therefore, the control circuit 907 uses M
Control signals are generated such that outputs (outputs of numbers 21 to 24) from the shift registers 1321 to 1324 are respectively selected as outputs of the PXs 1101e to 1101h.

Further, shift registers holding search data input to PDCs 1102i to 1102l are shift registers 1328 to 1331. Therefore,
The control circuit 907 generates a control signal such that outputs from the shift registers 1328 to 1331 (outputs of numbers 28 to 31) are respectively selected as outputs of the MPXs 1101i to 1101l.

At this time, each of the PDCs 1102a to 1102
The absolute value of the difference between the encoding target block data and the search data is calculated for each pixel by the calculation circuit 1202 in p, and the result is held in the second shift register 1203. These difference absolute values are input to the block summing circuit 905 and summed to obtain the sum of the difference absolute values in block units. The sum of the absolute values of the differences obtained in block units thus obtained is input to the minimum value determination / motion vector generation circuit 906, and held in an internal register (not shown).

During the next nine clocks (while search data for nine pixels from pixel number 26 is newly input, that is, until transition from the state 1401 to the state 1402 in FIG. 14), the absolute difference value is obtained. Is not calculated, so MPX
The selection state of 1101a to 1101l is unquestioned (don't care), but in the state of 1402, all the search data for calculating the absolute difference value for the next candidate block 1005 are complete, for example, PDCs 1102a to 1102d.
The shift register that holds the search data input to
The shift registers are 1310 to 1313.

Therefore, the control circuit 907 controls the MPX1
A control signal is generated so as to select the output from the shift register 1310 (the output of number 10) as the output of 101a. MPX1101b to 1101d
So that outputs from the shift registers 1311 to 1313 (outputs of numbers 11 to 13) are respectively selected as outputs of
Generate a control signal.

In the state of 1402 in FIG. 14,
A shift register holding search data input to the PDCs 1102e to 1102h is a shift register 1317.
~ 1320. Therefore, the control circuit 907 uses M
Control signals are generated so as to select outputs (outputs of numbers 17 to 20) from shift registers 1317 to 1320 as outputs of PXs 1101e to 1101h, respectively.

Further, the shift registers holding the search data input to the PDCs 1102i to 1102l are shift registers 1326-1329. Therefore,
The control circuit 907 generates a control signal such that outputs from the shift registers 1326 to 1329 (outputs of numbers 26 to 29) are respectively selected as outputs of the MPXs 1101i to 1101l.

Also in this case, similarly, each PDC 1102
The sum of the absolute values of the differences in block units is calculated by the calculation circuit 1202 and the block summation circuit 905 in a to
6 is input. Minimum value determination / motion vector generation circuit 90
In step 6, the sum of the difference absolute values input this time is compared with the sum of the difference absolute values held in an internal register (not shown) last time, and the smaller value is held again in the register. This process is similarly performed for all the subsequent candidate blocks.

During the subsequent two clocks, all search data for calculating the absolute difference between the candidate blocks 1006 and 1007 are prepared. At this time, each MPX 1101a ~
The control circuit 907 keeps the state of the control signal in the same state as that of the candidate block 1005 because the selection state of 1101l can be left as it is.

Since the calculation of the absolute difference value is not performed during the next 10 clocks, the selection state of the MPXs 1101a to 1101l is irrelevant. All the search data that can be performed are available, for example, PDCs 1102a-11
The shift registers holding the search data input to 02d are shift registers 1305 to 1308.

Therefore, the control circuit 907 controls the MPX1
A control signal is generated so as to select the output from the shift register 1305 (output of number 5) as the output of 101a. Also, control signals are generated so as to select outputs (outputs of numbers 6 to 8) from shift registers 1306 to 1308 as outputs of MPXs 1101b to 1101d, respectively.

In the state of 1403 in FIG. 14,
A shift register holding search data input to the PDCs 1102e to 1102h is a shift register 1314.
~ 1317. Therefore, the control circuit 907 uses M
Control signals are generated such that outputs (outputs of numbers 14 to 17) from the shift registers 1314 to 1317 are respectively selected as outputs of the PXs 1101e to 1101h.

Further, the shift registers holding search data input to PDCs 1102i to 1102l are shift registers 1325 to 1328. Therefore,
The control circuit 907 generates a control signal so as to select each of the outputs from the shift registers 1325 to 1328 (the outputs of numbers 25 to 28) as the outputs of the MPXs 1101i to 1101l.

During the subsequent four clocks, all search data from which the absolute difference values for the candidate blocks 1009 to 1012 can be calculated are prepared. At this time, each MPX 1101a ~
The control circuit 907 keeps the state of the control signal in the same state as that of the candidate block 1008 because the selected state of 1101l can be left as it is.

Since the calculation of the absolute difference value is not performed during the next 10 clocks, the selection state of the MPXs 1101a to 1101l is irrelevant, but when the state becomes 1404, the calculation of the absolute difference value for the next candidate block 1013 is stopped. All the search data that can be performed are available, for example, PDCs 1102a-11
The shift registers that hold the search data input to 02d are shift registers 1302-1305.

Therefore, the control circuit 907 controls the MPX1
A control signal is generated so as to select the output from the shift register 1302 (the output of number 2) as the output of 101a. Also, control signals are generated so as to select outputs (outputs of numbers 3 to 5) from shift registers 1303 to 1305 as outputs of MPXs 1101b to 1101d, respectively.

In the state of 1404 in FIG. 14,
A shift register holding search data input to the PDCs 1102e to 1102h is a shift register 1313.
１３1316. Therefore, the control circuit 907 uses M
Control signals are generated such that outputs (outputs of numbers 13 to 16) from the shift registers 1313 to 1316 are respectively selected as outputs of the PXs 1101e to 1101h.

Further, the shift registers holding search data input to PDCs 1102i to 1102l are shift registers 1325 to 1328. Therefore,
The control circuit 907 generates a control signal so as to select each of the outputs from the shift registers 1325 to 1328 (the outputs of numbers 25 to 28) as the outputs of the MPXs 1101i to 1101l.

During the following six clocks, all search data from which the absolute difference values for the candidate blocks 1014 to 1019 can be calculated are prepared. At this time, each MPX 1101a ~
Since the selection state of 1101l can be left as it is, the control circuit 907 keeps the state of the control signal in the same state as that of the candidate block 1013.

Since the calculation of the absolute value of the difference is not performed during the next 10 clocks, the selection state of the MPXs 1101a to 1101l is irrelevant. All the search data that can be performed are available, for example, PDCs 1102a-11
The shift registers holding the search data input to 02d are shift registers 1301 to 1304.

Therefore, the control circuit 907 controls the MPX1
A control signal is generated so as to select the output from the shift register 1301 (output of number 1) as the output of 101a. Also, control signals are generated so as to select outputs (outputs of numbers 2 to 4) from shift registers 1302 to 1304 as outputs of MPXs 1101b to 1101d, respectively.

In the state of 1405 in FIG. 14,
A shift register holding search data input to the PDCs 1102e to 1102h is a shift register 1313.
１３1316. Therefore, the control circuit 907 uses M
Control signals are generated such that outputs (outputs of numbers 13 to 16) from the shift registers 1313 to 1316 are respectively selected as outputs of the PXs 1101e to 1101h.

Further, the shift registers holding search data input to PDCs 1102i to 1102l are shift registers 1325 to 1328. Therefore,
The control circuit 907 generates a control signal so as to select each of the outputs from the shift registers 1325 to 1328 (the outputs of numbers 25 to 28) as the outputs of the MPXs 1101i to 1101l.

During the subsequent eight clocks, all search data from which the absolute difference values for the candidate blocks 1021 to 1028 can be calculated are prepared. At this time, each MPX 1101a ~
Since the selection state of 1101l may be left as it is, the control circuit 907 keeps the state of the control signal in the same state as that of the candidate block 1020.

Since the calculation of the absolute value of the difference is not performed during the next 11 clocks, the selection state of the MPXs 1101a to 1101l is irrelevant. All the search data that can be performed are available, for example, PDCs 1102a-11
The shift registers that hold the search data input to 02d are shift registers 1302-1305.

Therefore, the control circuit 907 controls the MPX1
A control signal is generated so as to select the output from the shift register 1302 (the output of number 2) as the output of 101a. Also, control signals are generated so as to select outputs (outputs of numbers 3 to 5) from shift registers 1303 to 1305 as outputs of MPXs 1101b to 1101d, respectively.

Also, in the state of 1406 in FIG. 14,
A shift register holding search data input to the PDCs 1102e to 1102h is a shift register 1314.
~ 1317. Therefore, the control circuit 907 uses M
Control signals are generated such that outputs (outputs of numbers 14 to 17) from the shift registers 1314 to 1317 are respectively selected as outputs of the PXs 1101e to 1101h.

Further, shift registers holding the search data input to PDCs 1102i to 1102l are shift registers 1326-1329. Therefore,
The control circuit 907 generates a control signal such that outputs from the shift registers 1326 to 1329 (outputs of numbers 26 to 29) are respectively selected as outputs of the MPXs 1101i to 1101l.

During the following six clocks, all search data for calculating the absolute difference value for the candidate blocks 1030 to 1035 are prepared. At this time, each MPX 1101a ~
Since the selection state of 1101l may be left as it is, the control circuit 907 keeps the state of the control signal in the same state as that of the candidate block 1029.

Since the calculation of the absolute difference value is not performed during the next nine clocks, the selection state of the MPXs 1101a to 1101l is irrelevant, but when the state becomes 1407, the calculation of the absolute difference value for the next candidate block 1036 is stopped. All search data that can be performed are available, for example, PDCs 1102a to 1102.
The shift registers that hold the search data input to 2d are shift registers 1305 to 1308.

Therefore, the control circuit 907 controls the MPX1
A control signal is generated so as to select the output from the shift register 1305 (output of number 5) as the output of 101a. Also, control signals are generated so as to select outputs (outputs of numbers 6 to 8) from shift registers 1306 to 1308 as outputs of MPXs 1101b to 1101d, respectively.

In the state of 1407 in FIG. 14,
A shift register holding search data input to the PDCs 1102e to 1102h is a shift register 1317.
~ 1320. Therefore, the control circuit 907 uses M
Control signals are generated so as to select outputs (outputs of numbers 17 to 20) from shift registers 1317 to 1320 as outputs of PXs 1101e to 1101h, respectively.

Further, shift registers that hold search data input to PDCs 1102i to 1102l are shift registers 1328 to 1331. Therefore,
The control circuit 907 generates a control signal such that outputs from the shift registers 1328 to 1331 (outputs of numbers 28 to 31) are respectively selected as outputs of the MPXs 1101i to 1101l.

During the subsequent four clocks, all search data from which the absolute difference values for the candidate blocks 1037 to 1040 can be calculated are prepared. At this time, each MPX 1101a ~
The control circuit 907 keeps the state of the control signal in the same state as that of the candidate block 1036 because the selected state of 11011l can be left as it is.

Since the calculation of the absolute value of the difference is not performed during the next seven clocks, the selection state of the MPXs 1101a to 1101l is irrelevant. All search data that can be performed are available, for example, PDCs 1102a to 1102.
The shift registers holding the search data input to 2d are shift registers 1310 to 1313.

Therefore, the control circuit 907 controls the MPX1
A control signal is generated so as to select the output from the shift register 1310 (the output of number 10) as the output of 101a. MPX1101b to 1101d
So that outputs from the shift registers 1311 to 1313 (outputs of numbers 11 to 13) are respectively selected as outputs of
Generate a control signal.

In the state of 1408 in FIG. 14,
A shift register holding search data input to the PDCs 1102e to 1102h is a shift register 1321.
１３1324. Therefore, the control circuit 907 uses M
Control signals are generated such that outputs (outputs of numbers 21 to 24) from the shift registers 1321 to 1324 are respectively selected as outputs of the PXs 1101e to 1101h.

Further, shift registers holding the search data input to the PDCs 1102i to 1102l are shift registers 1330 to 1333. Therefore,
The control circuit 907 generates a control signal such that outputs from the shift registers 1330 to 1333 (outputs of numbers 30 to 33) are respectively selected as outputs of the MPXs 1101i to 1101l.

In the subsequent two clocks, all search data for calculating the absolute difference between the candidate blocks 1042 and 1043 are prepared. At this time, each MPX 1101a ~
Since the selection state of 1101l can be left as it is, the control circuit 907 keeps the state of the control signal in the same state as that of the candidate block 1041.

Since the calculation of the absolute value of the difference is not performed during the next five clocks, the selection state of MPXs 1101a to 1101l is irrelevant. All search data that can be performed are available, for example, PDCs 1102a to 1102.
The shift registers holding the search data input to 2d are shift registers 1316 to 1319.

Therefore, the control circuit 907 controls the MPX1
A control signal is generated so as to select the output from the shift register 1316 (the output of number 16) as the output of 101a. MPX1101b to 1101d
So that outputs from the shift registers 1317 to 1319 (outputs of numbers 17 to 19) are respectively selected as outputs of
Generate a control signal.

In the state of 1409 in FIG. 14,
A shift register holding search data input to the PDCs 1102e to 1102h is a shift register 1325.
１３1328. Therefore, the control circuit 907 uses M
Control signals are generated so as to select outputs (outputs of numbers 25 to 28) from the shift registers 1325 to 1328 as outputs of the PXs 1101e to 1101h, respectively.

Further, the shift registers holding the search data input to the PDCs 1102i to 1102l are shift registers 1332 to 1335. Therefore,
The control circuit 907 generates a control signal such that outputs from the shift registers 1332 to 1335 (outputs of numbers 32 to 35) are respectively selected as outputs of the MPXs 1101i to 1101l.

As described above, all candidate blocks 1004
The calculation of the absolute value of the difference with respect to. At this time, the minimum value determination / motion vector generation circuit 906 performs the above-described processing of magnitude comparison and update storage in the register every time the sum of the absolute difference values is calculated for each candidate block, so that the final value is obtained. The candidate block having the smallest sum of absolute difference values among the candidate blocks is determined as the reference block. Then, a motion vector corresponding to the determined reference block is generated.

In the above operation, the output from shift registers 1309 and 1336 is
Also not used in 1102a to 1102p. Therefore, in this case, these shift registers 1309 and 133
It is not necessary to arrange to take out the outputs of 6 individually.

The series of operations described above, that is, the first
Of block data to be encoded from the frame memory 901a, search data from the second frame memory 901b, and MPXs 1101a to 1101
The control circuit 907 controls the selection switching operation at 1 and the processing in the minimum value determination / motion vector generation circuit 906.

The control circuit 907 may be constituted by hardware, but may also be constituted by a microcomputer comprising, for example, a CPU, a ROM and a RAM. In this case, a program describing a sequence for performing a series of processes as described above is stored in the ROM, and a CPU is executed in accordance with the program stored in the ROM.
Works. R storing the work program of this CPU
The OM constitutes the recording medium of the present invention.

Further, a hard disk may be connected to the microcomputer via a peripheral interface, and the work program of the CPU may be stored in the hard disk. The work program can be externally supplied to the hard disk. In this case, a hard disk and a means for supplying the work program, for example, a recording medium storing the work program are also recording media of the present invention. Configure.

As a recording medium for storing the work program, in addition to a ROM and a hard disk, for example, a floppy disk, an optical disk, a magneto-optical disk,
A D-ROM, a magnetic tape, a nonvolatile memory card, or the like can be used.

As described above, according to the present embodiment, the H.264 is used. 2
61 and H. In H.263 or MPEG1, 2, 4, etc., while expanding the search range for obtaining the motion vector, the search range is selected by selecting candidate blocks to be used for calculating the absolute difference value within the range. Even if it is expanded, without increasing the amount of calculation (without increasing the time required for calculation processing), the detection accuracy of the motion vector is improved,
The amount of information can be compressed more efficiently.

In the above embodiment, the coding target block and the candidate block are shown in FIG.
Although the case shown as 0 has been described, the present invention is not limited to this. H. 261 and H.E. 263, MPEG1, 2, 4
Then, since the encoding target block is actually composed of 16 pixels in the vertical and horizontal directions, PDC, MPX, etc. may be configured according to the number (in this case, 256 PDCs and 2 MPXs).
40). Further, the shape of the motion vector search range including the candidate block is not limited to the rhombus as shown in FIG. 10, but may be any shape.

When the range in which the candidate block exists is large, the maximum number of search data input directions (horizontal direction in the above embodiment) (1 in the above embodiment).
Assuming that 2) is n, the size (4 in the above embodiment) of the search data input direction of the encoding target block is a, and the other size (4 in the above embodiment) is b, nx
A shift register group consisting of the number of shift registers given by (b-1) + a may be prepared. Further, when the candidate block selection method is different, the number of inputs to the MPX, the output of the shift register input to the MPX, and the control of the MPX may be configured in accordance with each.

[0162]

As described above, according to the present invention, a plurality of sub-block summing means for summing the difference absolute value for each pixel obtained by the difference absolute value calculating means for each sub-block, Block summing means for summing the respective calculation results by the means, a motion vector generating means for obtaining a motion vector based on either the calculation result by the sub-block summation means or the calculation result by the block summation means, and which calculation result is used Control means for controlling whether to perform a motion vector for each sub-block from the calculation results of the plurality of sub-block summation means, using the difference absolute value for each pixel calculated by the difference absolute value calculation means. The motion vector for each macroblock can be obtained from the calculation result of the block summation unit that further sums the sum result of each sub-block. It is possible to obtain the. Accordingly, it is not necessary to separately provide a difference absolute value calculating means for obtaining a motion vector in a macroblock unit and a motion vector in a subblock unit, and the two types of motion vectors can be obtained with a simpler configuration. it can. At this time, for example, by adding an offset according to the motion of the image, the motion vector can be obtained by moving the motion vector search range in sub-block units, and the motion vector can be obtained without expanding the search range and increasing the calculation time. Detection accuracy can be improved.

According to another feature of the present invention, all difference absolute value calculation means in the current block are connected or
Since switching means for switching whether to connect only the absolute difference value calculating means in one sub-block separately from the other is provided, when obtaining a motion vector in sub-block units,
Each pixel value of the candidate block can be input independently for each sub-block, and appropriate data can be input to each of the sub-blocks even if the offset given to each sub-block is different from each other. Thereby, even when constructing an encoding system in which a different offset can be added to the search range of each sub-block, the motion vector detecting device of the present invention is applied to apply a motion vector in a macro block unit and a motion vector in a sub block unit. Both the motion vector and the motion vector can be obtained with a simpler configuration, and the detection accuracy of the motion vector can be improved without increasing the calculation time.

According to another feature of the present invention, in a predetermined rectangular area including the position of the block to be coded, the calculation is performed with a range excluding a region far from the block to be coded as a motion vector search range. So,
Even if the search range of the rectangular area is expanded more than usual, the number of blocks for which the absolute difference calculation is performed as a reference block candidate in the motion vector search range included in the large rectangular area is not increased. Can be. As a result, the search range can be expanded and the detection accuracy of the motion vector can be increased without increasing the calculation amount of the motion search.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main configuration of a motion vector detection device according to a first embodiment of the present invention.

FIG. 2 is a circuit for calculating a difference absolute value for each pixel (P shown in FIG. 1);
FIG.

FIG. 3 is a diagram for explaining motion compensation inter-frame prediction and motion vectors.

FIG. 4 is a diagram for explaining a block matching method which is one of the methods for detecting a motion vector.

FIG. 5 is a diagram for explaining a motion vector in sub-block units.

FIG. 6 is a diagram for describing motion vector detection when an offset is added to a search range in units of sub-blocks.

FIG. 7 is a diagram for explaining features of a motion vector detection device according to a second embodiment of the present invention.

FIG. 8 is a diagram for explaining features of a motion vector detection device according to a second embodiment of the present invention.

FIG. 9 is a block diagram illustrating a main configuration of a motion vector detection device according to a second embodiment of the present invention.

FIG. 10 is a diagram for explaining an example of a block matching method performed by the motion vector detection device according to the second embodiment of the present invention.

11 is a configuration diagram of the absolute difference calculating circuit shown in FIG. 9;

12 is a configuration diagram of a difference absolute value calculation circuit (PDC) for each pixel shown in FIG. 11;

FIG. 13 is a configuration diagram of a shift register group shown in FIG. 9;

FIG. 14 is a diagram illustrating a state transition of a shift register group when input processing of search data is continued.

[Explanation of symbols]

 11a to 11p PDC 12a to 12g MPX 13a to 13c Four-stage shift register 14a to 14d Subblock position 101 Difference absolute value calculation circuit 102a to 102d Subblock summation circuit 103 Macroblock summation circuit 104 Minimum value decision / motion vector generation circuit 105a, 105b Frame memory 106a, 106b Readout circuit 107 Control circuit 201-203 Shift register 204 Calculation circuit 901a, 901b Frame memory 902a, 902b Readout circuit 903 Difference absolute value calculation circuit 904 Shift register group 905 Block summation circuit 906 Minimum value determination / moving vector Generation circuit 907 Control circuit 1102a to 1102p PDC 1101a to 11011 MPX 1201, 1203 Shift register 1202 Calculation circuit 13 1-1340 shift register

Claims (21)

[Claims] An absolute value of a difference between each pixel value in an encoding target block and each pixel value in a reference block candidate block in a motion vector search range is calculated, and the calculated difference for each pixel is calculated. The absolute value is summed for each sub-block obtained by dividing the encoding target block into a plurality, and the sum of the sums is further summed, based on either the sum of the sub-blocks or the sum of all of them. A motion vector detecting device, wherein a motion vector is obtained. 2. The method according to claim 1, wherein the input of each pixel value in a block that is a candidate for the reference block is performed according to whether a motion vector of the encoding target block is obtained or a motion vector of the sub block is obtained. Switching between connecting all the difference absolute value calculation means for each pixel in the encoding target block or connecting only the difference absolute value calculation means in one sub-block in the encoding target block separately from the others. 2. The apparatus according to claim 1, further comprising switching means.
4. A motion vector detecting device according to claim 1. 3. The method according to claim 1, further comprising: an offset unit for adding a predetermined offset when obtaining the motion vector in the sub-block unit, thereby moving a motion vector search range in obtaining the motion vector in the sub-block unit. The motion vector detection device according to claim 2, wherein 4. A difference absolute value calculating means for each pixel, which calculates a difference absolute value between each pixel value in a coding target block and each pixel value in a reference block candidate block in a motion vector search range. A plurality of sub-block summing means for summing the difference absolute value of each pixel obtained by the difference absolute value calculation means for each sub-block obtained by dividing the encoding target block into a plurality of pieces; and the plurality of sub-blocks A block summation means for summing the respective calculation results in the summation means; and a motion vector for determining the reference block based on either the calculation result by the sub-block summation means or the calculation result by the block summation means, and obtaining a motion vector. A motion vector detection device comprising: a generation unit; and a control unit that controls the motion vector generation unit by a predetermined control signal. 5. A difference absolute value calculating means for each pixel for calculating a difference absolute value between each pixel value in a coding target block and each pixel value in a block which is a candidate for a reference block in a motion vector search range. A plurality of sub-block summing means for summing the difference absolute value of each pixel obtained by the difference absolute value calculation means for each sub-block obtained by dividing the encoding target block into a plurality of pieces; and the plurality of sub-blocks A block summing means for summing the respective calculation results by the summing means, and all difference absolute value calculating means in the encoding target block are connected to the input of each pixel value in the reference block candidate block. Switching means for switching whether only the absolute difference value calculating means in one sub-block in the encoding target block is connected separately from the other, and A motion vector generating means for determining the reference block based on either the calculation result by the calculation means or the calculation result by the block summing means and obtaining a motion vector; And a control means for controlling the motion vector. 6. The difference absolute value calculation means for each pixel is provided at a position corresponding to each pixel in the encoding target block, and the plurality of difference absolute value calculation means are provided by the switching means and a predetermined number of shift registers. Are connected in series via the input terminal, and while inputting each pixel value in the encoding target block to one input terminal of the absolute difference value calculating means for each pixel, the differential absolute value calculating means for each pixel The other input terminal is characterized in that each pixel value within the motion vector search range is input while being sequentially sent from the first stage to the last stage of the differential absolute value calculating means connected in series. The motion vector detection device according to claim 5, wherein 7. The block according to claim 5, wherein the reference block candidate block is a plurality of blocks within a motion vector search range shifted by adding a predetermined offset. Motion vector detector. 8. The motion vector detecting device according to claim 7, wherein the predetermined offset is set according to the motion of the image. 9. Reading out each pixel value in the motion vector search range, which is input to a difference absolute value calculation means for each pixel, from an image memory of a reference frame including each pixel value in the motion vector search range. The motion vector detecting device according to any one of claims 1 to 8, further comprising a reading unit that controls the motion vector. 10. An encoding method according to H.264. 263 or MP
EG4, characterized in that it is EG4.
A motion vector detection device according to the item. 11. An absolute difference between each pixel value in an encoding target block and each pixel value in a block that is a candidate for a reference block in a motion vector search range is calculated, and the reference value is calculated based on the calculation result. A motion vector detection device that determines a block and generates a motion vector, wherein the motion vector detection device includes a predetermined rectangular area including the position of the current block and excluding an area that is far from the current block. A motion vector detection device, wherein calculation is performed as a vector search range. 12. A motion vector detecting apparatus for generating a motion vector by a block matching method, wherein a plurality of shift registers are connected in series, and each pixel value in a motion vector search range is connected to the serially connected shift register. The shift register group is designed to input while sequentially sending from the first stage to the last stage, and the output of each shift register is taken out individually, and at a predetermined pixel position in the encoding target block A plurality of selection means provided in correspondence with each other, for inputting a plurality of outputs from a predetermined shift register in the shift register group, and selectively outputting any one of the plurality of outputs; A pixel value and a block supplied as a reference block candidate in the motion vector search range supplied from the selection means or the shift register group. Motion vector detection, comprising: a difference absolute value calculation means for each pixel for calculating a difference absolute value from each pixel value in the lock; and a control means for controlling the selection means by a predetermined control signal. apparatus. 13. A block summing means for summing the difference absolute value for each pixel obtained by the difference absolute value calculation means for each pixel, and the reference block is determined based on a calculation result by the block summing means. 13. The motion vector detecting device according to claim 12, further comprising: a motion vector generating means for obtaining a motion vector. 14. The motion vector search range in which each pixel value is input to the shift register group is defined as an area that is far from the encoding target block within a predetermined rectangular area including the encoding target block position. 13. The motion vector detecting device according to claim 12, wherein the motion vector is excluded. 15. The method according to claim 15, wherein the predetermined rectangular area is a rectangular area similar or dissimilar to the encoding target block, and the motion vector search range is a rhombic area inscribed in the rectangular area. Item 15. A motion vector detecting device according to item 14. 16. A reading means for controlling reading of each pixel value in the motion vector search range input to the shift register group from an image memory of a reference frame including each pixel value in the motion vector search range. The motion vector detecting device according to any one of claims 12 to 15, further comprising: 17. An encoding method according to H.264. 261, H .; 26
17. The motion vector detection device according to claim 11, wherein the motion vector detection device is MPEG1, MPEG2, or MPEG4. 18. An absolute difference between each pixel value in the encoding target block and each pixel value in a reference block candidate block in a motion vector search range is calculated, and the calculated difference for each pixel is calculated. The absolute value is summed for each sub-block obtained by dividing the encoding target block into a plurality, and the sum of the sums is further summed, based on either the sum of the sub-blocks or the sum of all of them. In a motion vector detection device adapted to determine a motion vector, according to whether to determine the motion vector for the encoding target block or the motion vector for the sub-block unit,
Switching the connection state of the difference absolute value calculation means for each pixel in the encoding target block with respect to the input of each pixel value in the candidate block of the reference block, and the sum result for each sub-block or all of them A computer-readable storage medium storing a program for causing a computer to realize a function of selecting any of the summation results and obtaining a motion vector. 19. A motion vector search range is moved by adding a predetermined offset according to the motion of an image when obtaining a motion vector in sub-block units, and each pixel value in the motion vector search range is determined. 19. The computer-readable recording medium according to claim 18, wherein a program for causing a computer to further realize a function of reading is recorded. 20. An absolute difference between each pixel value in an encoding target block and each pixel value in a reference block candidate block in a motion vector search range is calculated, and the reference value is calculated based on the calculation result. In the motion vector detecting device that determines a block and generates a motion vector, the motion vector search is performed in a predetermined rectangular area including the position of the current block, excluding an area that is far from the current block. A computer-readable recording medium in which a program for causing a computer to perform a function of performing a calculation as a range is recorded. 21. The motion vector detection device, wherein a plurality of shift registers are connected in series, and each pixel value within the motion vector search range is sequentially sent from the first stage to the last stage of the serially connected shift registers. And a shift register group in which the output of each shift register is individually taken out, and provided corresponding to a predetermined pixel position in the encoding target block, respectively. A plurality of selecting means for inputting a plurality of outputs from a predetermined shift register in the shift register group and selectively outputting any one of the plurality of outputs; each pixel value in the encoding target block; Calculate the absolute value of the difference between each pixel value in a block that is a reference block candidate in the motion vector search range and is supplied from the shift register group. Means for calculating a difference absolute value for each pixel, reading each pixel value in the motion vector search range from the image memory of the reference frame including each pixel value in the motion vector search range, and inputting the pixel value to the shift register group 21. The computer-readable recording medium according to claim 20, wherein a program for causing a computer to implement a function of controlling a selection operation by said selection means is recorded.