JPH10242927A - Method for allocating time slot in multiplexing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a time slot allocating method in a multiplexing device capable of improving the application efficiency of time slots for high speed data and reducing the number of communication lines in the case of converting low speed data into high speed data. SOLUTION: Two of the terminal boards (1a, 1b) to (6a, 6b) of plural terminal parts are regarded as one 128kbps terminal board and a multiplexing part stores the 64kbps low speed data of a 1st channel out of the 64kbps low speed data of two channels transmitted from one terminal board of each terminal part in an (n-1) position out of time slots T1 to T24 when n is an integer >=2 and stores 64kbps low speed data of the 1st channel out of the 64kbps low speed data of two channels transmitted from the outer terminal board in an (n+1) position out of the time slots T1 to T24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for converting low-speed data of 64 × n (n is an integer of 2 or more) Kbps into predetermined high-speed data, multiplexing the data, and transmitting (64 × n)
Kbps low-speed data, for example, 6.312 Mbps
The present invention relates to a time slot allocation method in a multiplexer adapted to be accommodated in the position of the time slot.

[0002]

2. Description of the Related Art Various attempts have been made to reduce the communication cost by increasing the use efficiency of a communication line. As an example, a multiplexing device that collectively transmits a plurality of communication signals and transmits the communication signal through one communication line is used. Various types have been developed.

[0003] As data applied to such a multiplexing device, a transmitting terminal converts low-speed data of 64 Kbps and a multiple thereof of 128 Kbps into high-speed data of 6.312 Mbps by a multiplexing device, and converts the data to a high-speed data of 6.312 Mbps. A multiplexing device for transmitting data to a terminal unit has been put to practical use.

[0004] In this case, two terminal boards that transmit low-speed data of 64 Kbps to one board are regarded as one unit in the terminal on the transmitting side, and a plurality of low-speed data of 64 Kbps and a plurality of multiples of 128 Kbps are considered. There is a multiplexing apparatus that combines the low-speed data with the low-speed data to multiplex and transmit the multiplexed data to a terminal on the receiving side.

FIG. 2 is a block diagram showing the configuration of one conventional application example of such a multiplexing device. In FIG. 2, the terminal units 1 to 6 on the transmitting side have two terminal boards 1a and 1 respectively.
b, 2a and 2b, 3a and 3b... 6a and 6b, and these two terminal boards 1a and 1b, 2a and 2b, 3a
, 3b... 6a and 6b are respectively arranged on one substrate and regarded as one unit, and are referred to as terminal units 1 to 6.

That is, each terminal board 1a and 1b, 2a and 2b
b, 3a and 3b... 6a and 6b transmit data on two channels, respectively. Therefore, each of the terminal units 1 to 6 multiplexes low-speed data of 64 Kbps or 128 Kbps on four channels, respectively. To be forwarded to.

In this manner, the terminal boards 1a and 1b, 2a and 2b, 3a and 3b,.
multiplexes the low-speed data of 64 Kbps or 128 Kbps from a and 6b by the multiplexing unit 7 to 6.312 Mbps
After converting the data into high-speed data, the data is transmitted to a receiving-side multiplexing unit (not shown).
(Or 128 Kbps) and returns the data to each terminal on the receiving side.

In the multiplexing unit 7 on the transmitting side in FIG.
5. Low-speed data of Kbps (or 128 Kbps)
When converting the data into high-speed data of 312 Kbps, the positions of the time slots T1 to T24 are allocated as shown in FIG.

FIG. 3 shows terminal boards 1a and 1b of each of the terminal units 1 to 6.
6A and 6B are frame configuration diagrams showing a time slot allocation situation when transmitting low-speed data of 64 Kbps or 128 Kbps from 6a and 6b. In normal time, 128 Kbps data of the terminal board 1a in the terminal unit 1 is the time slot T1 and T2. The 128 Kbps data of the terminal board 1b is accommodated in the positions C and D of the time slots T3 and T4, and similarly, the 128 Kbps data of the terminal boards 6a and 6b in the terminal section 6 are accommodated in the positions A and B. Time slots T21 and T22, T23 and T24 are accommodated in positions V and W, and X and Y, respectively.

Thus, there is no waste in using the time slots when converting the low-speed data of 128 Kbps from the terminal boards 1a and 1b of the terminal units 1 to 6 to 6b and 6b to the high-speed data of 6.312 Mbps. Transmits low-speed data of 64 Kbps from terminals 1 to 6 to 6.312 Mb.
When converting to high-speed data of 64 ps, the terminal units 1 to 6 transmit 64 Kbps data only from one of the terminal boards 1 a and 1 b to one of the terminal boards 6 a and 6 b, and transmit the odd-numbered data. Time slots T1, T3,
.. Time slots of T23 are allocated, and positions A, A of these time slots T1, T3,.
C, E... X accommodate low-speed data of 64 Kbps.

On the other hand, low-speed data of 64 Kbps is not transmitted from the terminal boards 1b to 6b of the terminal units 1 to 6, and therefore, even-numbered time slots T2, T4,.
.. Y do not contain low-speed data of 64 Kbps and become empty.

[0012] As described above, the vacant state can be created only in 12
Terminal board handling low-speed data of 8Kbps and 64Kbp
This is because, when a terminal board handling low-speed data of s is mixed, both terminal boards handle 128 Kbps.

[0013]

In such a multiplexing apparatus, when a multiplexing apparatus system is constructed only with a terminal panel for transmitting low-speed data of 64 Kbps, the two terminal boards in each terminal section are required. The time slot corresponding to the transmission of low-speed data of one of the terminal panels (see FIG.
In the even-numbered time slots T2 to T24) are useless data.

The unnecessary data is discarded as unnecessary data in the terminal on the receiving side. However, the multiplexing unit 7 on the transmitting side converts the data into high-speed data of 6.312 Mbps and converts the data into high-speed data of 6.312 Mbps. In this case, only half of the time slots are used, and the use efficiency is deteriorated. As a result, reduction in the number of used lines is hindered.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and has a 64 × n (n is an integer of 2 or more) K
It is an object of the present invention to provide a time slot allocation method in a multiplexer capable of improving the use efficiency of a time slot and consequently reducing the number of used lines when converting low-speed data of bps into predetermined high-speed data. I do.

[0016]

In order to achieve this object, a time slot allocation method in a multiplexing apparatus according to the present invention uses two terminal boards 1a and 1b to handle low-speed data of 64 Kbps on one board. 64 × n (n is an integer of 2 or more) K, where 6a and 6b are each regarded as one unit
In the time slot allocation method in the multiplexer for converting low-speed data of bps into predetermined high-speed data, the allocation positions of the time slots T1 to T24 of the low-speed data of the two terminal boards 1a, 1b to 6a and 6b are determined. It has it at the positions of (n-1) and (n + 1).

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a multiplexing apparatus according to an embodiment of the present invention; FIG. 1 is a frame configuration diagram showing data accommodating time slots for explaining this embodiment. FIG. 1 is a diagram showing the configuration of the multiplexer shown in FIG. In the description of the embodiments, description will be made with the help of.

First, the terminal panel 1a of each of the terminal units 1 to 6 in FIG.
6 transmitted from 6b and 1b, 2a and 2b,... 6a and 6b
A case where low-speed data of 4 Kbps is accommodated in the time slots T1 to T24 of the frame in FIG. 1 will be described. In this embodiment, the terminal board 1a of each of the terminal units 1 to 6
, 1b, 2a and 2b,..., 6a and 6b are each regarded as one 128 Kbps terminal board.
Kbps terminal boards can also be connected.

In FIG. 2, each terminal unit 1 to 6 is a terminal panel 1
.a and 1b, 2a and 2b,... 6a and 6b, and these terminal boards 1a and 1b, 2a and 2b,.
When the low-speed data of 64 Kbps is transmitted to the multiplexing unit 2 by two channels at a time, 64 channels of the two channels transmitted from the terminal board 1a of the terminal unit 1 to the multiplexing unit 7 are transmitted.
64 Kb of the first channel among low-speed data of Kbps
The low-speed data of ps is accommodated in the multiplexing unit 7 at the position A of the time slot T1 in FIG. 1, and of the low-speed data of two channels of 64 Kbps transmitted from the terminal panel 1b to the multiplexing unit 7, The low-speed data of 64 Kbps is accommodated in the multiplexing unit 7 at the position B of the time slot T2 in FIG.

Also, the second terminal board 1a of the terminal unit 1
The low-speed data of 64 Kbps of the channel is accommodated in the position C of the time slot T3. Similarly, low-speed data of 64 Kbps of the second channel of the terminal board 1b in the terminal unit 1 is accommodated in the position D of the time slot T4.

Similarly, when two channels of 64 Kbps of low-speed data transmitted from the terminal boards 2a and 2b to 6a and 6b in the terminal units 2 to 6 are transmitted to the multiplexing unit 7, The low-speed data of 64 Kbps of the first channel of the boards 2a and 2b to 6a and 6b is accommodated in the position of the {n (n is an integer of 2) -1} time slot.
The low-speed data of 64 Kbps of the second channel of each of the terminal boards 2a and 2b to 6a and 6b is accommodated in the position of the (n + 1) th time slot.

By doing so, the conventional 64 Kb
In the case where low-speed data of ps and 128 Kbps are mixed and transmitted from the terminal boards 1a and 1b to 6a and 6b of each of the terminal units 1 to 2 to the multiplexing unit 2 by two channels respectively, 64 Kb is used.
In this embodiment, data for one terminal board for low-speed data of 128 Kbps or data for two terminal boards for low-speed data of 64 Kbps is accommodated in a portion where the accommodation position of the low-speed data of ps is an empty slot. can do.

According to the above embodiment, for example, when four terminal boards for handling low-speed data of 128 Kbps and two terminal boards for handling low-speed data of 64 Kbps are mounted on the multiplexing unit, At this time, the vacant time slot is equivalent to two terminal boards for handling low-speed data of 128 Kbps. Therefore, a multiplexing device is used in the upper layer of the multiplexing hierarchy, and the multiplexing device has a terminal board 2 for handling low-speed data of 64 Kbps. Conventionally, two lines are required when connecting one card and one terminal board for handling low-speed data of 128 Kbps. However, according to the present invention, one line can be accommodated.

In the above embodiment, the transmission speed of the applied data is 64 Kbps and 128 Kb for convenience of explanation.
Although the case of two types of ps has been described as an example, the present invention is not limited to this, and data of 64 × n (n is an integer of 2 or more) Kbps can be applied, Further, it goes without saying that the high-speed data for converting the low-speed data to the high-speed data can also be applied to high-speed data other than the 6.312 Mbps.

[0025]

According to the time slot allocating method in the multiplexing apparatus of the present invention, 64 × n (n is an integer of 2 or more) Kbps is regarded as one unit for each of two terminal boards handling low-speed data of 64 Kbps. When the low-speed data is converted into predetermined high-speed data, the time slot allocation positions of the low-speed data of the two terminal boards are set to (n-1) and (n + 1). The data of another (64 × n) Kbps terminal board can be accommodated in the position of the time slot which can be regarded as “(time slot)”.

Therefore, 64 Kbps and (64 × n)
Even when converting low-speed data in which Kbps is mixed into high-speed data, it is possible to improve the use efficiency of time slots for high-speed data. Accordingly, the number of communication lines can be reduced, and the communication cost can be reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a frame configuration showing data accommodating time slots for explaining an embodiment of a time slot allocation method in a multiplexing apparatus of the present invention.

FIG. 2 is a block diagram showing a configuration of a multiplexing device for explaining a time slot allocation method in a conventional multiplexing device.

FIG. 3 is an explanatory diagram of a frame configuration showing data accommodating time slots for explaining a time slot allocation method in a conventional multiplexer.

[Explanation of symbols]

 1 to 6 terminal unit 1a to 6a, 1b to 6b terminal board T1 to T24 time slot AX Position for storing data

Claims (2)

[Claims] 1. The two terminal boards (1a) and (1b) to (6a) and (6b) which handle low-speed data of 64 Kbps on one board are regarded as one unit, and 64 × n (n is 2 or more) Integer) K
In a time slot allocation method in a multiplexer for converting low-speed data of bps to predetermined high-speed data, the time of low-speed data of each of the two terminal boards (1a) and (1b) to (6a) and (6b) A time slot allocation method in a multiplexing apparatus, characterized in that slots (T1) to (T24) are allocated at positions (n-1) and (n + 1), respectively. 2. The time slot allocation method in a multiplexing apparatus according to claim 1, wherein said (64 × n) of said terminal boards (1a) and (1b) to (6a) and (6b).
A time slot allocating method in a multiplexing apparatus, wherein low-speed data is accommodated at a position of a time slot of 6.312 Mbps high-speed data when converting low-speed data of Kbps to high-speed data of 6.312 Mbps.