JPH10242414A - Dynamic semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To properly suppress high concentration of a substrate and to improve a retention characteristic without increasing a manufacture process by including not only the transistors of a memory cell but also transistors used in a peripheral circuit and using p-type polysilicon as gate electrodes. SOLUTION: Since a polysilicon film 32 constituting the gate electrodes of the respective transistors is formed by covering a silicon oxide film 30 and the polysilicon film 32 becoming the gate electrode in a subsequent stage is set to be the p-type polysilicon film, BF2 ions are driven. Then, a silicon oxide film 34 is formed by covering the p-type polysilicon film 32. Then, a patterning processing for forming the gate electrode 32 of the nMOS transistor of the memory cell, the gate electrode 32b of the nMOS transistor of the peripheral circuit and the gate electrode 32c of the pMOS transistor is executed. The respective source/drain areas of the nMOS transistors of the memory cell and the nMOS transistors of the peripheral circuit are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device (D) using dynamic memory cells for storing information.
More particularly, the present invention relates to a configuration of a gate electrode of an insulated gate field effect transistor used for a DRAM, that is, a MIS (metal-insulator-semiconductor) transistor, generally a MOS (metal-oxide-semiconductor) transistor.

2. Description of the Related Art Along with the high integration of DRAMs, which are unavoidable, MIS (MOS) as a built-in device has been increasing.
Transistors are required to be increasingly miniaturized. On the other hand, due to the miniaturization of the transistor accompanying the reduction in the cell area, it is necessary to increase the concentration of the substrate on which the cell is formed in order to obtain a desired threshold voltage of the transistor. . However, if the substrate concentration is too high, there arises a problem that the retention characteristics deteriorate (that is, the data retention time cannot satisfy the standard value) as described later. Therefore, there is a demand for a technique for suppressing the increase in the substrate concentration without causing such a problem.

[0003]

2. Description of the Related Art First, a description will be given of a technical background in which the substrate concentration is increased. According to a well-known scaling rule of a MOS transistor, the internal electric field of the MOS transistor is kept constant by setting the power supply voltage, the channel length and the gate oxide film thickness to 1 / K times and the substrate concentration to K times.

However, in the case of a DRAM cell transistor (generally, an nMOS transistor), it is necessary to suppress a leak current when the transistor is off.
There is a restriction that the threshold voltage must be kept almost constant. This threshold voltage (referred to as Vth) is expressed by the following equation, as is well known to those skilled in the art.

Vth = Vfb + φsi + γ (φsi + Vsb) ^1/2 where Vfb is a flat band voltage determined by a work function difference between a gate electrode material and a substrate material under the gate electrode, φsi is a surface potential, γ is a substrate effect coefficient, and Vsb Represents a substrate bias voltage, and is represented as follows. Vfb = −0.56-φf φf = (kT / q) ln (Nb / ni) φsi = 2φf γ = (2εo · εsi · qNb) ^1/2 / Cox where Nb is the substrate concentration and ni is the intrinsic carrier. Concentration, k
Is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, εo is the dielectric constant of vacuum, εsi is the dielectric constant of the substrate, and Cox is the capacitance of the gate oxide film (however, the capacitance per unit area).

[0006] Note that these relations is to use a sufficiently high concentration (e.g., 10 ²⁶ m ^-3 or higher) n-type polysilicon as a gate electrode, also interface charge is assumed when sufficiently small. The S (sub-threshold) coefficient is represented by the following equation. S ≒ 2.3 (kT / q) (1 + Cd / Cox) Here, Cd represents a depletion layer capacitance (however, a capacitance per unit area). The capacitance Cd of the depletion layer and the capacitance Cox of the gate oxide film are expressed as follows.

Cd = εo · εsi / Xd Cox = εo · εox / tox where Xd = {2εo · εsi (φsi + Vsb) / qNb} where tox is the thickness of the gate oxide film and Xd is the thickness of the depletion layer. Is represented. Here, for example, it is set as a design standard that the leakage current when the cell transistor is turned off at room temperature is 10 digits smaller than the current flowing when Vgs (gate voltage with respect to source) = Vth (threshold voltage).

Here, it is assumed that -1 V is applied as a substrate bias voltage (Vsb). A solution that satisfies this design criterion can be found by computer to find that the gate oxide film (gate insulating film)
8 can be obtained as the relationship between the thickness tox and the substrate concentration Nb. By the way, it is known from the technical trend that the gate oxide film becomes thinner for each DRAM generation. This thinning of the gate oxide film
It is absolutely necessary to suppress the short channel effect accompanying miniaturization of transistors. However, even in this case, the short channel effect cannot be completely suppressed, and the threshold voltage Vth is reduced to some extent and the S coefficient is deteriorated.
To compensate for this, a substrate concentration higher than the substrate concentration shown in FIG. 8 is actually required.

However, on the other hand, there is a motivation to not completely suppress the short-channel effect, but rather use the region where the short-channel effect occurs to some extent. That is, as shown in FIG. 9 as an example, the substrate bias voltage Vsb
(In the illustrated example, a change from −3 V to −1 V) in the threshold voltage Vth is caused by a region where the channel length L is shorter than a region where the channel length L is longer (that is, a region where the short channel effect occurs). Is smaller (ΔV in the illustrated example).
1 to ΔV2). That is, if the short channel effect occurs, there is an advantage that the dependence of the threshold voltage on the substrate bias is reduced.

Under these circumstances, when the thickness tox of the gate oxide film becomes 10 nm or less as shown in FIG. 8, the substrate concentration Nb becomes 10 ²³ m ^-3 or more, and the concentration becomes extremely high. Of course, depending on the setting of the design standard, it is natural that there is a choice to use a higher substrate concentration or a lower substrate concentration even for the same gate oxide film thickness.

Here, as a temporary worst case,
When the thickness of the gate oxide film is 10 nm or less, the problem is that the substrate concentration becomes high. A problem when the substrate concentration is unnecessarily high is, for example, a decrease in retention time. Regarding such a problem, for example, IED
M95, p915 (T. Hamamoto, S. Sugiura, and S.
Sawada). If the retention time is reduced, it is not possible to follow the above-mentioned technical trend (the gate oxide film becomes thinner for each DRAM generation). Therefore, even if the generation of the DRAM advances, a technique for suppressing the increase in the substrate concentration is required.

Conventionally, as one technique for suppressing an increase in substrate concentration, a so-called minus reset method is known in which the potential of a word line for selecting a memory cell is fixed to a negative potential when not selected. Have been. However, this method is complicated in circuit and the control for it is also difficult, so if there is a simpler method, there is no better way.

It is conceivable that the MOS transistor of the memory cell is formed as an n-channel type in the conventional technology.
This n-channel MOS transistor (hereinafter simply referred to as “nM
OS transistor ". ) Is configured with an n-type gate, but a p-type gate is applied instead of the n-type gate. Cell transistor has p-type gate n
The technology using MOS transistors has already been proposed by the present applicant (see Japanese Patent Application No. 7-181178).

In this prior art, an nMOS transistor and a p-channel MOS transistor (also simply referred to as a “pMOS transistor”) used in a peripheral circuit (row decoder, column decoder, column gate, etc.) for controlling the operation of a memory cell. )), An n-type gate is employed as before, but a p-type gate is employed for the cell transistor in order to suppress the substrate bias dependence of the threshold voltage. That is, by applying a p-type gate to the cell transistor, the increase in the substrate concentration is suppressed, and the dependence of the threshold voltage on the substrate bias is suppressed.

[0015]

As described above, the prior art filed by the present applicant (Japanese Patent Application No. 7-181178) is merely one method for suppressing the dependence of the threshold voltage on the substrate bias. It describes that a p-type gate is used only for the cell transistor. However, as described with reference to FIG. 9, the dependence of the threshold voltage on the substrate bias can be appropriately reduced by actively using the region where the short channel effect occurs. Therefore, there is no strong motivation to adopt a p-type gate for the cell transistor merely because of the suppression of the dependence of the threshold voltage on the substrate bias.

In this prior art, the cell transistor is limited to a p-type gate, and the transistors of the peripheral circuit are limited to using an n-type gate as in the prior art. Therefore, when forming a gate electrode of a transistor, a step for manufacturing a p-type gate and a step for manufacturing an n-type gate (so-called gate formation) are required. this is,
It is not preferable because it causes a problem that the whole manufacturing process as a memory becomes complicated and also leads to a significant increase in cost.

The present invention has been made in view of the above-mentioned problems in the prior art, and has substantially no increase in the number of overall manufacturing steps, and has a substrate concentration required for achieving a desired threshold voltage. It is an object of the present invention to provide a dynamic semiconductor memory device capable of appropriately suppressing the increase in the density of the semiconductor device and eventually improving the retention characteristics.

[0018]

In order to solve the above-mentioned problems of the prior art, a dynamic semiconductor memory device according to the present invention includes not only transistors of memory cells but also transistors used in peripheral circuits. hand,
All use p-type polysilicon as the gate electrode.

However, in order to make the threshold voltage of the transistor of the peripheral circuit a desired value, it is necessary to use the same well profile as that of the n-type gate used in the prior art. become unable. Therefore, in order to obtain a desired threshold voltage, it is necessary to optimize ion implantation (ion implantation energy and dose) for adjusting the threshold voltage. In this connection, in some cases, the channel region of the nMOS transistor of the peripheral circuit is formed in the form of a so-called “buried channel”, and the channel region of the pMOS transistor is formed in the form of a normal surface channel. The setting opposite to the conventional setting may be performed.

As described above, according to the present invention, the gate electrodes of all the MOS transistors used are of a single conductivity type (p-type). Is unnecessary. That is, in the above-mentioned prior art (Japanese Patent Application No. 7-181178), the gate electrode of the cell transistor is p-type polysilicon, while the gate electrode of the transistor of the peripheral circuit is n-type polysilicon. Need to be manufactured in a separate step. It is also conceivable that the gate electrodes of the cell transistor and the pMOS transistor of the peripheral circuit are made of p-type polysilicon, and the gate electrode of the nMOS transistor of the peripheral circuit is made of n-type polysilicon. A manufacturing process is required. That is, in the present invention, at least the step of forming the gate electrode can be simplified.

Not only the nMOS transistor of the memory cell but also the nMOS transistor and the pMOS transistor of the peripheral circuit have a further advantage that the gate electrode is made of p-type polysilicon. That is, since electrons generally have higher mobility than holes, the nMOS transistor has better driving power than the pMOS transistor. When an n-type gate is used, the nMOS transistor is a surface channel type and the pMOS transistor is a buried channel type. However, in general, the absolute value of the threshold voltage cannot be set lower in the buried channel type than in the surface channel type. This means that as the voltage is reduced in the future, the buried channel type will have a lower driving force than the surface channel type. From the above two points, when an n-type gate is used, p
The MOS transistor has much lower driving power than the nMOS transistor, and the imbalance between the two will be remarkable under a future low voltage. Therefore, when a p-type gate is adopted, the above two effects are offset to some extent, and the direction becomes well balanced.

Further, since a p-type gate is used for a transistor of a memory cell, the above-mentioned prior art (Japanese Patent Application No.
As described in US Pat. No. 181178), it is possible to suppress the increase in the substrate concentration, thereby suppressing the dependence of the threshold voltage on the substrate bias. The suppression of the increase in the substrate concentration greatly contributes to preventing the retention characteristics from deteriorating.

[0023]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 schematically shows a cross-sectional configuration of a main part (transistor) in a dynamic semiconductor memory device according to one embodiment of the present invention.
In FIG. 1, reference numeral 12 denotes a field insulating film for separating each element (that is, the nMOS transistor Qa of the memory cell, the nMOS transistor Qb and the pMOS transistor Qc of the peripheral circuit).

The nMOS transistor Qa of the memory cell
A gate insulating film 30a, a p-type gate electrode 32a formed on a channel region with the gate insulating film 30a interposed therebetween, and n-type source regions 38a formed on both sides of the substrate with the channel region interposed therebetween. And n-type drain region 40a
It is comprised including. Also, the nMOS of the peripheral circuit
The transistor Qb includes a gate insulating film 30b and an n-type channel region (buried channel) 2 formed on the substrate surface.
6, a p-type gate electrode 32b formed on the n-type channel region 26 with the gate insulating film 30b interposed therebetween, and an n-type source region 38b formed on both sides of the n-type channel region 26 in the substrate. And an n-type drain region 40b.

Similarly, the pMOS transistor Qc of the peripheral circuit includes a gate insulating film 30c and the gate insulating film 30c.
and a p-type gate electrode 32c formed on the channel region with c in between, and a p-type source region 38c and a p-type drain region 4 formed on both sides of the substrate with the channel region in between.
0c. FIG. 2 schematically shows the entire configuration of the dynamic semiconductor memory device according to the present embodiment.

In FIG. 1, reference numeral 1 denotes a memory cell array in which a plurality of word lines and a plurality of bit lines are arranged in a matrix, and an intersection of each word line WLi and each bit line BLj has a capacitor C for charge storage. And nMO for charge transfer
Dynamic memory cell M having S transistor Q
C is provided. Reference numeral 2 denotes a row address buffer for buffering a row address signal RAD included in an external address signal ADD. Reference numeral 3 denotes a column address buffer for buffering a column address signal CAD also included in the address signal ADD. A row decoder for decoding a row address signal RAD from the row address buffer 2 and selecting one of a plurality of word lines, a decoder 5 decodes a column address signal CAD from the column address buffer 3 and a plurality of bit line pairs Column decoder for selecting any one pair of
Is a sense amplifier (S / A) circuit for sensing and amplifying data read from a memory cell connected to the selected word line and bit line, and 7 is a bit line pair (for example, BL) selected by the column decoder 5. ₁ , BLX ₁ ) to a corresponding data line pair (DL ₁ , DLX ₁ ). In the column gate circuit 7, as shown, a pair of nMOS transistors (Q ₁ , QX ₁ ) responding to a column signal from the column decoder 5
Are provided for a corresponding pair of bit lines.
Each data line DL ₁ , DLX _{1 to} DLn, DLXn (data bus DB) is connected to a data input / output (I / O) buffer 8.
_Is connected to the data input / output terminals D _IN / D _OUT via the.

In the configuration of FIG. 2, the charge transfer nMOS transistor Q forming the memory cell MC corresponds to the nMOS transistor Qa of the memory cell shown in FIG. The nMOS transistor Q ₁ (or QX ₁ ) in the column gate circuit 7 is the nMOS transistor Q ₁ (or QX ₁ ) of the peripheral circuit shown in FIG.
It corresponds to MOS transistor Qb. In the configuration of FIG. 2, the pMOS transistor Q of the peripheral circuit shown in FIG.
The transistor corresponding to c is not shown.

As shown in FIG. 1, according to the configuration of the present embodiment, not only the nMOS transistor Qa of the memory cell but also all the nMOS transistors Qb and pMOS transistors Qc used in the peripheral circuits are included. M
Since only the p-type gate electrode of the OS transistor is used, the step of “separate gate formation” as in the conventional type is not required, and at least the step of forming the gate electrode can be simplified.

Further, since a p-type gate is employed for the nMOS transistor Qa of the memory cell, as described in the prior art proposed by the present applicant (see Japanese Patent Application No. 7-181178), It is possible to appropriately suppress the increase in the concentration and suppress the dependence of the threshold voltage on the substrate bias. The suppression of the increase in the substrate concentration contributes to preventing the retention characteristics from deteriorating.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The manufacturing process of each transistor (the nMOS transistor Qa of the memory cell, the nMOS transistor Qb of the peripheral circuit and the pMOS transistor Qc) in the embodiment shown in FIG. 1 will be described in detail with reference to FIGS. explain. First, referring to FIG. 3, in step (A), a p-type semiconductor, for example, silicon (Si)
Field insulating film (in the illustrated example, a silicon oxide film; Si
O ₂ ) 12 is formed. This is achieved by forming, for example, a silicon nitride film (not shown) in a region (active region) where each transistor is formed on the semiconductor substrate 10 and selectively oxidizing a region (inactive region) other than the active region. Is realized.

In the next step (B), the semiconductor substrate 10
A p-type well 1 for forming an nMOS transistor of a memory cell and an nMOS transistor of a peripheral circuit.
6 is formed. This is realized by forming a resist 14 on an active region where a pMOS transistor of a peripheral circuit is formed, and then ion-implanting boron (B) into the entire substrate. After forming the p-type well 16, the resist 14 is removed.

In the next step (C), an n-type well 20 for forming a pMOS transistor of a peripheral circuit is similarly formed in the semiconductor substrate 10. This corresponds to the nMOS transistor of the memory cell and the nMO of the peripheral circuit.
A resist 18 is formed on the active region where the S transistor is formed.
Is formed, ion implantation of phosphorus (P) is performed on the entire substrate. Although phosphorus (P) was used in this embodiment, arsenic (As) was used instead.
May be used. Similarly, after forming the n-type well 20, the resist 18 is removed.

It is needless to say that the order of step (B) and step (C) may be reversed. In addition, it is needless to say that the well forming step and the field oxide film forming step may be reversed. Next, referring to FIG. 4, in a step (D), a silicon oxide film (Si
O ₂ ) 22 are formed. In this embodiment, the thickness of the silicon oxide film 22 is 12 nm.

In the next step (E), the nM
In order to adjust each threshold voltage of the OS transistor and the pMOS transistor, a channel doping process is performed. This is realized by forming a resist 24 on an active region where an nMOS transistor of a memory cell is formed, and then implanting phosphorus (P) ions into the entire substrate. This ion implantation was performed under the conditions of an energy of 20 keV and a dose of 2.5 × 10 ¹⁶ m ⁻² .

In this step (E), since an n-type material (phosphorus) is used as a dopant, n
As shown, the channel region of the MOS transistor
It becomes a region of the conductivity type (n type) opposite to the conductivity type (p type) of the well 16, and the buried channel 26 is formed. On the other hand, the channel region of the pMOS transistor in the peripheral circuit has the same conductivity type as the conductivity type (n-type) of the well 20, and a normal surface channel is formed. Although phosphorus (P) was used in this embodiment, arsenic (A) was used instead.
s) may be used. After the channel doping process, the resist 24 is removed.

In the next step (F), channel doping is similarly performed to adjust the threshold voltage of the nMOS transistor of the memory cell. This is realized by forming a resist 28 on the active region where the nMOS transistor and the pMOS transistor of the peripheral circuit are formed, and then ion-implanting boron (B) into the entire substrate. This ion implantation
Energy is 20 keV and dose is 3 × 10 ¹⁶ m ^-2
Was performed under the following conditions.

In this step (F), since a p-type material (boron) is used as a dopant, the channel region of the nMOS transistor of the memory cell is
Region of the same conductivity type (p type) as above, and a normal surface channel is formed. Similarly, after performing the channel doping process, the resist 28 is removed. Note that, of course, the order of step (E) and step (F) may be reversed.

Next, referring to FIG. 5, step (G)
Then, the silicon oxide film 22 formed in the step (D) is removed. In the next step (H), a silicon oxide film (SiO ₂ ) 30 is formed on the entire substrate by thermal oxidation. The silicon oxide film 30 constitutes a gate insulating film of each transistor. In this embodiment, the thickness of the silicon oxide film 30 is 6.5 nm.

In the next step (I), a polysilicon film (poly-Si) is formed so as to cover the silicon oxide film 30.
32 are formed. The polysilicon film 32 constitutes a gate electrode of each transistor. In this embodiment, the thickness of the polysilicon film 32 is set to 150 nm. Next, referring to FIG. 6, in a step (J), a process for converting the polysilicon film 32 to be a gate electrode into a “p-type” polysilicon film in a later stage is performed. This is realized by ion-implanting boron fluoride (BF ₂ ) into the polysilicon film 32. This ion implantation has an energy of 20 keV and a dose of 5 × 1.
The test was performed under the condition of 0 ¹⁹ m ^-2 . Note that boron (B) alone can be used as the ion to be used. However, since boron (B) is extremely light, unless it is implanted with sufficiently low energy, it reaches the substrate. Therefore, in this embodiment,
Boron (B) was bonded to fluorine (F), which has no other effect, and used.

In the next step (K), a silicon oxide film (SiO ₂ ) 3 covering the p-type polysilicon film 32 is formed.
4 is formed. In this embodiment, the silicon oxide film 34
Was 100 nm in thickness. In the next step (L),
Gate electrode 32 of nMOS transistor of memory cell
a, Gate electrode 32 of nMOS transistor of peripheral circuit
A patterning process for forming the gate electrodes 32c of the b and pMOS transistors is performed. This is realized by forming a mask (not shown) on silicon oxide films 34a, 34b, and 34c corresponding to portions of the p-type polysilicon film to be left as a gate electrode, and then performing etching or the like. You.

Finally, referring to FIG. 7, in step (M), source / drain regions of the nMOS transistor of the memory cell and the nMOS transistor of the peripheral circuit are formed. This is realized by forming a resist 36 on an active region where a pMOS transistor of a peripheral circuit is formed, and then ion-implanting phosphorus (P) into the entire substrate. This ion implantation was performed under the conditions of an energy of 20 keV and a dose of 1 × 10 ¹⁷ m ⁻² .

By this step (M), the n-type source region 38a and the n-type drain region 40a of the nMOS transistor of the memory cell and the n-type source region 38b and the n-type drain region 40b of the nMOS transistor of the peripheral circuit
Is formed. Although phosphorus (P) is used in this embodiment, arsenic (As) may be used instead. After forming the source / drain regions, the resist 36 is removed.

In the next step (N), source / drain regions of pMOS transistors of the peripheral circuit are formed in the same manner. This is realized by forming a resist 42 on an active region where an nMOS transistor of a memory cell and an nMOS transistor of a peripheral circuit are formed, and then ion-implanting boron fluoride (BF ₂ ) over the entire substrate. Is done. This ion implantation was performed under the conditions of an energy of 20 keV and a dose of 1 × 10 ¹⁷ m ⁻² .

By this step (N), p of the peripheral circuit is
A p-type source region 38c and a p-type drain region 40c of the MOS transistor are formed. Step (M)
Needless to say, the order of and (N) may be reversed. In the last step (P), resist 4
Remove 2. As a result, a p-type gate is used for the nMOS transistor of the memory cell, and n
This means that a memory using a p-type gate for each of the MOS transistor and the pMOS transistor has been manufactured.

As a result of the process simulation and the device simulation, the concentration near the channel of the nMOS transistor of the memory cell is 2 × 10 ²³ m ⁻³ , and when the gate length is 0.18 μm, the threshold voltage is 1. 3
V (substrate bias voltage; -1 V) and a sufficiently large value could be easily obtained. For the nMOS transistor of the peripheral circuit, when the gate length is 0.3 μm,
The threshold voltage is 0.4V (substrate bias voltage; -1V)
Met. The threshold voltage of the pMOS transistor of the peripheral circuit was 0.7 V (substrate bias voltage; 1 V) when the gate length was 0.3 μm.

Although the thickness of the gate insulating film is set to 6.5 nm in the above embodiment (see step (H)), the thickness of the gate insulating film is set to 1.5 nm to 10 nm.
Is suitably selected in the range between 3 and 7 nm. The lower limit (1.5 nm) in this case is
For example, the upper limit (10 nm) is determined from the content described in IEDM96, p105, and the upper limit (10 nm) is determined from the content of the prior art of the present invention.

Further, in the above-described embodiment, the case where the source / drain regions having a relatively low concentration are formed has been described. However, in the subsequent steps, various processes well known to those skilled in the art may be appropriately added. The good thing is, of course. For example, another silicon oxide film (SiO ₂ ) is formed on the side surface of each gate electrode (32a, 32b and 32c) and each silicon oxide film (34a, 34b and 34c) formed thereon.
Alternatively, a sidewall spacer is formed by depositing a silicon nitride film (SiN), and then a higher concentration impurity is implanted into each source / drain region to form a lightly doped drain (LDD) structure. It is thought that the development to.

As a modification of the above-described embodiment, the p-type gate electrodes (32a, 32b and 32c)
A relatively low-resistance conductive material (for example, a silicide compound composed of tungsten (W) and silicon (Si), titanium (Ti) and silicon (S)
It is also possible to adopt a structure in which a silicide compound (i)) is deposited. With such a structure, the resistance of the entire gate electrode is reduced, so that power consumption can be reduced and operation speed can be improved.

Further, in the above embodiment, the case where the silicon oxide film is used as the gate insulating film has been described, but the gate insulating film may be formed of a material other than the silicon oxide film. In particular, in order to prevent boron (B) in the p-type gate from diffusing into the substrate through the gate insulating film, it is preferable to use a silicon nitride film (SiN), a silicon oxynitride film (SiON), or the like. In this case, the thickness of the gate insulating film formed of the material is 1.5 nm to 10 nm in terms of a silicon oxide film as described above.
The thickness is selected in the range between nm and the converted film thickness with respect to the silicon oxide film is represented by (film thickness of the material × relative permittivity of the silicon oxide film / relative permittivity of the material).

[0050]

As described above, according to the present invention, since the gate electrodes of all the MOS transistors used are of the p-type, it is possible to achieve the desired operation without substantially increasing the entire manufacturing process. It is possible to appropriately suppress the increase in the substrate concentration required for realizing the threshold voltage. This makes it possible to prevent the retention characteristics from deteriorating.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically showing a configuration of a main part (transistor) in a dynamic semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is a block diagram schematically showing an overall configuration of a dynamic semiconductor memory device according to one embodiment of the present invention.

FIG. 3 is a cross-sectional view (part 1) illustrating a process for manufacturing each transistor illustrated in FIG. 1;

FIG. 4 is a sectional view (part 2) illustrating a process for manufacturing each transistor illustrated in FIG. 1;

FIG. 5 is a sectional view (3) showing a step of manufacturing each transistor shown in FIG. 1;

FIG. 6 is a sectional view (part 4) showing a step of manufacturing each transistor shown in FIG. 1;

FIG. 7 is a cross-sectional view (No. 5) showing a step of manufacturing each transistor shown in FIG. 1;

FIG. 8 is a diagram showing a relationship between a thickness of a gate insulating film and a substrate concentration.

FIG. 9 is a diagram for explaining a substrate bias dependence of a threshold voltage with respect to a channel length.

[Explanation of symbols]

 Qa: nMOS transistor of memory cell Qb: nMOS transistor of peripheral circuit Qc: pMOS transistor of peripheral circuit 12: field insulating film (oxide film) for element isolation 26: n-type channel region (buried channel) 30a, 30b, 30c ... gate insulating films 32a, 32b, 32c ... p-type gate electrodes 38a, 38b ... n-type source regions 38c ... p-type source regions 40a, 40b ... n-type drain regions 40c ... p-type drain regions

Claims (9)

[Claims] 1. A memory cell having a charge storage capacitor and a charge transfer n-channel MIS transistor, and an n-channel transistor for controlling the operation of the memory cell.
A dynamic semiconductor memory device having a peripheral circuit having an IS transistor and a p-channel MIS transistor, wherein a gate electrode of an n-channel MIS transistor of the memory cell is formed of p-type polysilicon, and an n-channel MIS transistor of the peripheral circuit is provided. And a gate electrode of the p-channel MIS transistor is also formed of p-type polysilicon. 2. The dynamic semiconductor memory device according to claim 1, wherein said memory cell has an n-channel MIS.
A dynamic semiconductor memory device, wherein the thickness of the gate insulating film of each of the transistor and the n-channel MIS transistor and the p-channel MIS transistor of the peripheral circuit is selected in a range between 1.5 nm and 10 nm. . 3. The dynamic semiconductor memory device according to claim 2, wherein a thickness of a gate insulating film of each of said transistors is preferably selected in a range between 3 nm and 7 nm. Dynamic semiconductor memory device. 4. The dynamic semiconductor memory device according to claim 3, wherein said memory cell has an n-channel MIS.
The channel region of the transistor is formed in the form of a surface channel, the channel region of the n-channel MIS transistor of the peripheral circuit is formed in the form of a buried channel,
A dynamic semiconductor memory device, wherein a channel region of a p-channel MIS transistor of the peripheral circuit is formed in the form of a surface channel. 5. The dynamic semiconductor memory device according to claim 3, wherein an n-channel MIS of said memory cell is provided.
The gate electrode of each of the transistor and the n-channel MIS transistor and the p-channel MIS transistor of the peripheral circuit has a structure in which a relatively low-resistance conductive material is deposited on the p-type polysilicon layer. Dynamic type semiconductor memory device. 6. The dynamic semiconductor memory device according to claim 5, wherein said conductive material having a relatively low resistance is:
A dynamic semiconductor memory device comprising a silicide compound comprising tungsten and silicon. 7. The dynamic semiconductor memory device according to claim 5, wherein said relatively low-resistance conductive material is
A dynamic semiconductor memory device comprising a silicide compound comprising titanium and silicon. 8. The dynamic semiconductor memory device according to claim 3, wherein a gate insulating film of each of said transistors is formed of a silicon oxide film. 9. The dynamic semiconductor memory device according to claim 3, wherein when the gate insulating film of each of said transistors is formed of a material other than a silicon oxide film, the equivalent silicon oxide film thickness of said material is used. Is represented by (film thickness of the material × relative permittivity of the silicon oxide film / relative permittivity of the material).