JPH10242260A - Element isolating region for semiconductor device and its formation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of forming an element isolating region easily and with high accuracy without roughening an active region or jutting out to this. SOLUTION: An insulator 18 is made to fill the groove 14 of a substrate 10. The insulator 18 is provided with a projection 18b projecting over an etching stopper film 12 from the main body part 18a. The projection regulates the lateral step d toward inside of the insulator. A surface layer 19 which covers the etching stopper film 12 and the surface of the insulator 18 including the projection 18b is made in roughly equal thickness at the step d. The surface layer is removed until the etching stopper film 12 is exposed by etching, and a side wall part 18c which never juts out to an active region is made in the insulator 18 by the surface part remaining at the step part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an element isolation region used for a semiconductor device such as a semiconductor integrated circuit and a method for forming the same.
The present invention relates to an element isolation region suitable for element isolation of a so-called deep submicron level highly integrated IC circuit and a method of manufacturing the same.

[0002]

2. Description of the Related Art An integrated circuit incorporated in a semiconductor substrate uses an element isolation technique for electrically isolating element regions on the semiconductor substrate from each other. One of the element isolation technologies is a shallow trench isolation (Sh
allow Trench Isolation: hereinafter referred to as STI).

According to this STI, IEDM Nos. 57-6
As introduced on page 0, a groove is formed in a silicon substrate whose surface is covered with a nitride film, and an oxide, that is, an insulator for forming an element isolation region is buried in the groove. The surface of the buried insulator protruding from the silicon substrate is subjected to an etching process, and when this etching process causes a step at the edge of the insulator protruding from the semiconductor surface, the insulator constituting the element isolation region causes a step. The active region of the partitioned semiconductor substrate may be damaged.

In order to prevent a step from being formed at the edge of the surface of the buried insulator by the etching process, the edge of the insulator is removed beforehand by this etching process. Later, a sidewall portion protruding into the active region is formed. Since the sidewall portion is raised in advance in a portion where a step is likely to be generated by the etching process, a step is prevented from being generated in this portion by the above-described etching process. According to this STI, for example, it is possible to partition the active region at an arrangement pitch smaller than 0.6 μm.

[0005]

However, in the conventional STI as described above, a sidewall portion is formed at an edge portion of the insulator prior to an etching process of the insulator to fill the concave groove, so that the semiconductor is formed. The nitride film covering the surface of the substrate is removed. Therefore, since the insulator on which the sidewall portion is formed is subjected to the etching process in a state where the surface of the semiconductor substrate is exposed, the active region of the semiconductor substrate may be damaged by the etching process.

The sidewall portion is formed so as to protrude laterally from an edge portion of the insulator to an active region outside the sidewall portion. Therefore, even by the above-described etching treatment of the insulator, the sidewall portion may partially remain in the active region as a part of the insulator. Since the protrusion of the insulator into the active region makes it impossible to perform element separation with high precision, it is necessary to reliably prevent the protrusion of the insulator into the active region. However, accurate dimensional control by etching of the insulator protruding into the active region is not easy.

Therefore, a method of forming an element isolation region with high accuracy and high integration relatively easily without roughening the active region of the semiconductor and without protruding into the active region, and the appearance of such an element isolation region are desired. Was rare.

[0008]

The present invention adopts the following constitution in order to solve the above points. <Structure> The element isolation method according to the present invention is a method for forming an element isolation region for partitioning an active region on a semiconductor substrate, comprising the steps of: A semiconductor substrate having a surface covered with an etching stopper film and having a groove defining an active region formed in the surface is provided with a body portion filling the groove and the etching stopper layer integrally formed from the body portion. Is formed for the isolation region having a protrusion defined by a lateral step d of a predetermined size between the peripheral wall of the main body portion and the protrusion. Next, a surface layer having a thickness substantially equal to the dimension of the step d and made of the same material as the insulator is formed on the etching stopper film and on the surface of the insulator protruding from the etching stopper film. Is done. This surface layer is removed by anisotropic etching until the etching stopper film is exposed. After that, the etching stopper film is removed.

<Operation> In the element isolation method according to the present invention,
The insulator formed to fill the groove of the semiconductor substrate has a projection projecting beyond the etching stopper film from its main body, and this projection is insulated without protruding toward the active region. The dent has a lateral step d inward of the body. Further, since the thickness of the surface layer covering the surface of the insulator including the etching stopper film and the protrusion protruding from the stopper film is formed substantially equal to the lateral step d, anisotropic etching is used. By removing the surface layer until the etching stopper film is exposed, the sidewall portion that does not protrude into the active region can be easily formed on the insulator due to the surface layer portion remaining in the step portion. .

[0010] Therefore, since the sidewall portion that does not protrude into the active region can be formed relatively easily and with high precision, the sidewall portion can be appropriately formed at the edge of the insulator. An element isolation region that does not damage the active region can be formed relatively easily and with high precision. Further, in the etching treatment of the surface layer, since the active layer is protected by the etching stopper layer, damage to the active layer in this etching treatment can be reliably prevented.

<Structure> The element isolation region according to the present invention is filled in a groove formed on the surface of the semiconductor substrate to define an active region in the semiconductor substrate and projects from the groove. Including the insulator formed. In the element isolation region according to the present invention, the insulator filled in the concave groove and protruding from the concave groove covers the silicon nitride and the bottom and the peripheral wall of the silicon nitride facing the wall surface of the concave groove. A surface layer made of a silicon oxide film, and an outer edge of a top portion in a peripheral wall portion of the surface layer film on the same plane as a top portion of the silicon nitride is rounded off at a corner.

<Action> An insulator having a rounded surface layer at the outer edge of the top of the insulator ensures that the active region is electrically isolated without damaging the active region. . Further, since the body of the insulator is made of silicon nitride, for example, a so-called B doped with boron and phosphorus is used as an interlayer insulating film formed on the element isolation region.
Even if an interlayer insulating film such as PSG is employed, the insulator containing silicon nitride as a main body effectively suppresses the diffusion of boron and phosphorus. The change in the threshold value of an active element such as a transistor due to the diffusion of boron or phosphorus can be reliably prevented. Furthermore, since silicon nitride has a higher etching selectivity of polysilicon as a gate electrode material than that of a silicon oxide film,
This is advantageous in that it has excellent etching resistance during gate patterning.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. Embodiment 1 FIG. 1 shows a method for forming an element isolation region according to the present invention. In the formation method of the present invention, as shown in FIG. 1A, for example, the surface of a silicon substrate 10 is subjected to thermal oxidation, and a silicon oxide film (SiO ₂₎ having a thickness of 10 nm to 20 nm is formed on the surface. ) 11 is formed. Using this silicon oxide film 11 as a pad oxide film,
For example, the silicon nitride film 12 (Si ₃ N) is formed by using a low pressure chemical vapor deposition method (hereinafter, referred to as an LP-CVD method).
₄ ) is formed to have a thickness of 150 nm to 200 nm. The silicon nitride film 12 is used as an etching stopper film when forming a sidewall portion on an insulator for element isolation described later.

The silicon oxide film 11 and the silicon nitride film 12 are patterned by well-known photolithography and etching techniques. By this patterning, portions of the silicon oxide film 11 and the silicon nitride film 12 corresponding to the regions where the element isolation regions are to be formed are selectively removed, whereby the mask openings 13 are formed. A predetermined region of the substrate 10 opened to the opening 13 is etched by anisotropic etching using the silicon oxide film 11 and the silicon nitride film 12 in which the opening 13 is formed as a mask. As a result, the substrate 10 has the configuration shown in FIG.
As shown in (a), for example, a trench, that is, a concave groove 14 having a width dimension and a depth dimension of about 0.3 μm is formed.

After the formation of the groove 14, as shown in FIG. 1B, a silicon oxide film is formed on the surface of the groove 14 and the silicon nitride film 12 which is opened by, for example, the LP-CVD method. 15 is formed to a thickness dimension of, for example, 50 nm. After the formation of the silicon oxide film 15, the silicon oxide film 1
The plug-shaped polysilicon 16 is filled in the concave groove 14 whose surface is covered with 5. Prior to the filling of the polysilicon 16, a portion of the silicon oxide film 15 covering the surface of the concave groove 14 is used as a protective film. It is desirable to implant boron into the periphery of the concave groove 14 of the substrate 10 as a well-known channel stopper by, for example, an ion implantation method.

In order to fill the trenches 14 with the polysilicon 16, polysilicon is deposited to a thickness of, for example, 500 nm on the silicon oxide film 15 including the trenches 14 by, for example, a CVD method. A portion deposited on the silicon nitride film 12 of polysilicon, that is, a portion deposited on the substrate 10 excluding a portion (16) in the concave groove 14 is removed by chemical mechanical polishing (CMP) or chemical etching. . As a result, a plug-shaped polysilicon 16 filling the inside of the concave groove 14 is formed. The top surface of the polysilicon 16 is flattened so as to be substantially flush with the surface of the silicon oxide film 15 on the substrate 10, that is, the surface of the silicon oxide film 15 on the silicon nitride film 12. In removing the unnecessary polysilicon on the silicon oxide film 15,
The portion of the silicon oxide film 15 on the silicon nitride film 12 is used as an etching stopper film.

Thereafter, as shown in FIG. 1C, the portion of the silicon oxide film 15 exposed on the substrate 10 is removed by etching using the polysilicon 16 as an etching stopper. The silicon oxide film 1
5, the upper edge of the silicon oxide film 15 which surrounds the peripheral surface of the polysilicon 16 and is exposed from the polysilicon 16 has a height lower than the surface position of the silicon nitride film 12, that is, the top position of the polysilicon 16. To the position. As a result, polysilicon 1
Step 17 is formed between the top surface of silicon oxide film 6 and the upper edge of silicon oxide film 15 remaining on the peripheral surface.

Next, the polysilicon 16 undergoes a thermal oxidation process to become silicon oxide. By this thermal oxidation treatment, FIG.
As shown in FIG. 3D, the polysilicon 16 which has become silicon oxide is integrated with the silicon oxide film 15 remaining on the peripheral surface, thereby forming an insulator 18 made of silicon oxide.

Polysilicon 16 and silicon oxide film 1
The insulator 18 formed by the integration of the protrusions 5 is integrally formed with the projecting portions 18a which protrude beyond the silicon nitride film 12 from the main body portion 18a filling the inside of the concave grooves 14 by the step portions 17 described above.
b is defined. Therefore, a predetermined lateral step d is formed on both edges of the protruding portion 18b between the protruding portion 18b and the main body portion 18a.

After the formation of the insulator 18 having the lateral step d, the silicon nitride film 12 and the surface of the insulator 18 protruding from the silicon nitride film 12 are formed on the surface of the insulator 18 as shown by a virtual line in FIG. For example, a surface layer 19 made of a silicon oxide film having a thickness substantially equal to the dimension of the lateral step d is formed by, eg, CVD.

The surface layer 19 embeds the lateral step d, and its thickness dimension is substantially equal to the dimension of the step d. Therefore, by using the silicon nitride film 12 as an etching stopper, the surface layer 19 is removed by anisotropic etching, and when the silicon nitride film 12 is exposed, this etching process is stopped, thereby obtaining the state shown in FIG. As described above, the side wall portion 18c is formed, in which the step d is buried and does not protrude from the groove 14 into the active region laterally outward, and the upper edge portion is rounded.

In the etching for forming the side wall portion 18c, the active region excluding the concave groove 14 of the substrate 10 is covered with the silicon nitride film 12 functioning as an etching stopper film. The active region is not damaged by the etching for forming the side wall portion 18c.

Thereafter, as shown in FIG. 1F, the silicon nitride film 12 is removed using, for example, hot phosphoric acid, and after the silicon nitride film 12 is removed, as shown in FIG. As a result, the silicon oxide film 11 is removed.
As a result, the edge is rounded without protruding from the groove 14 to the laterally outward active region, and an element isolation region consisting of the insulator 18 projecting from the surface of the substrate 10 at a height of, for example, 30 to 50 nm is completed. .

In the method of the first embodiment, as described above, the surface layer 19 having a thickness dimension substantially equal to the lateral step d is used.
Then, an etching process is performed using the silicon nitride film 12 thereunder as an etching stopper film, and the etching process is stopped by exposing the silicon nitride film 12, thereby protruding from the concave groove 14 into the active region laterally outward. In addition, the sidewall portion 18c whose upper edge is rounded can be formed reliably and relatively easily.
Further, since the active region of the substrate 10 is securely protected by the silicon nitride film 12 during the etching of the sidewall portion 18c, damage to the active region below the silicon nitride film 12 can be reliably prevented. .

Therefore, according to the method of the present invention, it is possible to relatively easily manufacture an element isolation region of, for example, 0.3 μm or less, which is suitable for element isolation of a so-called deep submicron level highly integrated IC circuit. .

FIG. 2 shows another method of forming the element isolation region according to the present invention. In the example shown in FIG.
As shown in (a), for example, LP-CVD is performed on a substrate 10 via a pad oxide film 11 similar to that described above.
A polysilicon layer 20 having a thickness of 100 nm is laminated by the method. The polysilicon layer 20 is used as an etching stopper film when forming a sidewall portion on an insulator for element isolation described later.

The substrate 10 covered with the pad oxide film 11 made of silicon oxide and the polysilicon layer 20 is provided with a mask opening 13 formed on the polysilicon layer 20 by well-known photolithography and etching techniques.
Is subjected to an anisotropic etching process using the resist 21 having By this etching, a concave groove 14 having a width dimension and a depth dimension of, for example, about 0.3 μm is formed in the substrate 10 through the silicon oxide film 11 and the polysilicon layer 20 thereon.

It is desirable to implant the same channel stop ions as described above into the peripheral portion of the concave groove 14 of the substrate 10. Also, instead of using the resist 21,
A stacked body of the silicon oxide film 11 and the polysilicon layer 20 can be used as an etching mask.

After the resist 21 is removed, as shown in FIG. 2B, the silicon oxide film 15 is formed on the concave groove 14 and the surface of the polysilicon layer 20 which is opened by, for example, the LP-CVD method. Is formed with a thickness dimension of, for example, 50 nm. After the formation of the silicon oxide film 15, a silicon nitride film having a thickness of, for example, 300 nm is grown on the silicon oxide film 15 including the inside of the concave groove 14 by, for example, the LP-CVD method.

Unnecessary portions of the silicon nitride film on the silicon oxide film 15 except for the inside of the concave groove 14 are removed from the silicon nitride film, and as a result, as shown in FIG. The groove 14 is formed on the silicon oxide film 15 in the inside.
A silicon nitride 22 filling the inside is formed. The upper surface of silicon nitride 22 is flattened so as to be substantially flush with the surface of silicon oxide film 15 on polysilicon layer 20.

Next, as shown in FIG. 2C, the portion of the silicon oxide film 15 exposed on the substrate 10 is removed by etching using the silicon nitride 22 as an etching stopper. The silicon oxide film 1
5 surrounds the peripheral surface of the silicon nitride 22, and the upper edge of the silicon oxide film 15 exposed from the silicon nitride 22 is positioned higher than the surface position of the silicon nitride 22, that is, the top position of the silicon nitride 22. It is etched to a lower height. As a result, a step 17 is formed between the top surface of silicon nitride 22 and the upper edge of silicon oxide film 15 remaining on the peripheral surface.

Of the silicon nitride 22 and the silicon oxide film 15 remaining on the peripheral surface, a portion 22b above the step 17 forms a protruding portion protruding from the polysilicon layer 20, and the remaining portion is in the concave groove 14. Of the main body portion 22a. Between the main body portion 22b and the protruding portion 22a,
The step 17 defines a step d similar to that described above.

Therefore, the surface film 1 made of a silicon oxide film
And a body portion 22a filling the groove 14 and projecting beyond the polysilicon layer 20 integrally from the body portion and having a predetermined dimension between the body portion 22a and the peripheral wall of the body portion. An insulator 18 'having a protruding portion 22b defined by the step d is formed.

After the formation of the insulator 18 'having the lateral step d, the polysilicon layer 20 and the insulator 18' protruding from the polysilicon layer 20 are formed as shown by a virtual line in FIG. A surface layer 19 'made of a silicon oxide film having a thickness substantially equal to the dimension of the lateral step d is formed on the surface by, for example, a CVD method.

The surface layer 19 'has a thickness substantially equal to the lateral step d. Therefore, the surface layer 19 'is removed by anisotropic etching using the polysilicon layer 20 as an etching stopper, as in the above-described example.
By stopping the etching process by exposing the polysilicon layer 20, the step d is buried as shown in FIG. And the side wall portion 18 ′ c having a rounded upper edge is formed by the silicon oxide film 15.
Formed integrally with the upper edge.

Thereafter, as shown in FIG. 2E, the polysilicon layer 20 is removed by anisotropic etching while leaving the silicon oxide film 11 to protect the active region of the substrate 10, and Then, the silicon oxide film 11 is removed. As a result, the edge portion is rounded without protruding from the groove 14 to the laterally outward active region, and the insulator 1 protruding from the surface of the substrate 10 at a height of, for example, 30 to 50 nm.
An element isolation region consisting of 8 'is completed.

Therefore, according to the method of the second embodiment, as in the first embodiment, the side wall does not protrude from the concave groove 14 into the active region laterally outward and has a rounded upper edge. The portion 18'c can be formed reliably and relatively easily. In addition, this sidewall portion 1
Since the active region of the substrate 10 is surely protected by the polysilicon layer 20 during the etching of 8'c,
Damage to the active region below the polysilicon layer 20 can be reliably prevented.

As shown by a virtual line in FIG. 2E, a polysilicon layer 24 for the gate is formed on the element isolation region made of, for example, the insulator 18 'via the gate oxide film 23, for example. However, the silicon nitride 22, which is the main body of the insulator 18 'in Example 2, has higher resistance to the etching for patterning the polysilicon 24 than the silicon oxide. In this regard,
The element isolation region made of the insulator 18 'shown in the specific example 2 is
It is advantageous.

The element isolation region made of the insulator 18 'shown in the specific example 2 is formed on the element isolation region because the silicon nitride constituting the main body effectively suppresses the diffusion of boron and phosphorus. Even if an interlayer insulating film such as so-called BPSG to which boron and phosphorus are added is employed, the diffusion of boron and phosphorus is effectively suppressed. Therefore, diffusion of boron and phosphorus into an active element such as a transistor formed in the element isolation region is prevented, and a change in the threshold value of the active element due to the diffusion can be reliably prevented.

[0040]

According to the method for forming an element isolation region according to the present invention, as described above, a sidewall portion that does not protrude into an active region can be formed relatively easily and with high accuracy. The sidewall portion can be appropriately formed at the edge portion of the semiconductor device, whereby an element isolation region that does not damage the active region can be formed relatively easily and with high precision. Further, in the etching treatment of the surface layer, since the active layer is protected by the etching stopper layer, damage to the active layer in this etching treatment can be reliably prevented.

According to the element isolation region of the present invention, as described above, the insulator having the rounded surface layer at the outer edge at the top of the insulator damages the active region. Without providing the active region, the active region is reliably electrically separated, and the body of the insulator made of silicon nitride effectively suppresses the diffusion of boron and phosphorus contained in the interlayer insulating film such as BPSG. Therefore, diffusion to these active regions can be effectively suppressed.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram showing a method for forming an element isolation region according to the present invention.

FIG. 2 is a manufacturing process diagram showing another method for forming an element isolation region according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Substrate 12, 20 Etching stopper film 14 Groove 18, 18 'Insulator 18a, 22a Body part 18b, 22b Projection part 18c, 18'c Side wall part 19, 19' Surface layer

Claims (6)

[Claims] 1. A method for forming an element isolation region defining an active region on a semiconductor substrate, comprising: an etching stopper film made of an insulating material having an etching resistance different from that of an insulating material forming the element isolation region. The groove of the semiconductor substrate, the surface of which is covered with a groove defining an active region formed on the surface, protrudes beyond the etching stopper layer integrally from the main body portion filling the groove and the main body portion, and Forming an insulator for an element isolation region having a protrusion defined by a lateral step d having a predetermined size between the peripheral wall of the main body portion and the etching stopper film and projecting from the etching stopper film; Forming a surface layer having a thickness dimension substantially equal to the dimension of the step d on the surface of the insulator and made of the same material as the insulator; Removing the surface layer by exposing the etching stopper film until the etching stopper film is exposed, forming a sidewall portion in the insulator at the stepped portion without protruding into the active region, removing the etching stopper film A method for forming an element isolation region for a semiconductor device, comprising: 2. The method according to claim 1, wherein said etching stopper film is formed of a silicon nitride film, and said insulator is formed of silicon oxide. 3. The semiconductor having the protruding portion, wherein the surface of the silicon nitride film and the surface of the silicon nitride film are covered with the semiconductor substrate having the groove formed thereon. Forming an oxide film; filling the trench covered with the silicon oxide film with polysilicon; removing the polysilicon until the silicon oxide film on the silicon nitride film is exposed; Flattening the upper surface of the polysilicon remaining in, removing a portion of the silicon oxide film covering the surface of the silicon nitride film, oxidizing the polysilicon remaining in the trench, 3. The method for forming an element isolation region according to claim 2, wherein a silicon oxide integrated with the remaining silicon oxide film is formed. 4. The method according to claim 1, wherein said etching stopper film is formed of a polysilicon film, and said insulator is formed of silicon nitride and a silicon oxide film covering a peripheral surface thereof. 5. The semiconductor device according to claim 5, wherein the insulator having the protruding portion includes a semiconductor substrate having a surface covered with the polysilicon film and having the groove formed thereon, a silicon covering a surface of the groove and a surface of the polysilicon film. Forming an oxide film, filling the trench covered with the silicon oxide film with silicon nitride, removing the silicon oxide film until the polysilicon is exposed, 5. The method for forming an element isolation region according to claim 4, wherein the method comprises removing a portion covering a surface of the silicon nitride film. 6. An element isolation region including an insulator filled in and protruding from a recess formed in a surface of the semiconductor substrate to define an active region in the semiconductor substrate. The insulator includes a silicon nitride, and a surface film made of a silicon oxide film covering a bottom portion and a peripheral wall portion facing the wall surface of the concave groove of the silicon nitride,
An element isolation region, wherein an outer edge of a top portion of a peripheral wall portion of the surface layer film on the same plane as a top portion of the silicon nitride is rounded at a reduced angle.