JPH1024147A - Chip collating device for controlling game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chip collating device with a simple mechanism which checks the abusing of a chip carried on a control substrate of a game machine. SOLUTION: In a game machine which incorporates a chip comprising a memory means 2 to store a program for control and a CPU3 to control game machines based on the program, there are arranged an IC clip for inspecting the chip, a signal input cable 6 and a signal input section 7 to input a data buss signal of the chip, a normal CPU9 to collate the chip, a memory means 8, a signal comparator circuit 10 for comparison and collation of signals, an error detection circuit 12 for detecting errors and a display section 14 which comes on when an error is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention inspects whether or not a CPU and a ROM mounted on a control board of a gaming machine such as a pachinko machine that have been type-approved have been tampered with after manufacture. And a collation device for the

[0002]

2. Description of the Related Art A gaming machine such as a pachinko machine is controlled by a control board constituted by a CPU and a storage means for storing a program for controlling the CPU. It is necessary to receive type approval as to whether or not a jackpot occurs with a predetermined probability. However, since the program may be modified after the type approval, a microcomputer chip (hereinafter referred to as a microcomputer chip having a predetermined algorithm for checking whether the contents of the program at the start of the gaming machine has been modified in order to prevent such illegality). A chip has been invented (Japanese Patent Application No. 03-118120). Therefore, in a gaming machine using such a chip, an illegal operation of a program incorporated in the storage means is almost impossible.

[0003]

However, recently, a control CPU and a storage means (RO) for a control program have been developed.
M) may be replaced with a different one from the one used when the type was approved, or an external device may be configured to drive an incorrect CPU and ROM while wearing the same appearance as a legitimate CPU and ROM. However, there is an inconvenience that this cannot be easily checked. Therefore, the present invention has been made in view of the drawbacks of the prior art, and
Provided is a collation device capable of checking for illegality even if U or ROM is modified.

[0004]

That is, the present invention has a storage means for storing a control program for controlling a game machine and a game machine which is controlled based on the program stored in the storage means. In a gaming machine incorporating a gaming machine control chip composed of a CPU and a CPU, an IC clip for connecting the chip to a pin of the chip for inspecting the chip, and data of the chip connected by the IC clip A signal input cable and a signal input unit for inputting a bus signal, a legitimate CPU and storage means certified by a third-party inspection organization mounted for verification of the gaming machine control chip, and Signal comparison circuit for comparing and comparing the data bus signal of the gaming machine control chip input through the unit with the data bus signal of the regular CPU and the storage means An error detection circuit that detects an error when the deviation of the signal detected by the signal comparison circuit continues for several clock periods or more, and a display unit that lights an abnormal signal when an error is detected by the error detection circuit. This object is achieved by a gaming machine control chip collating device configured to collate the data to be inspected with the data of a regular chip by clipping the IC clip to a chip installed in the gaming machine. .

[0005]

The present invention is based on the following premise. That is, if the storage means and the chip mounted on the verification device are the same (authorized) as those inspected by the third party accredited organization, the chip mounted on the gaming machine control board must perform the same operation. Must. In the collating apparatus according to the present invention, for example, the game machine to be controlled is connected to the pin of the chip mounted on the gaming machine control board while the power of the gaming machine is turned off. After the regular chip and storage means are installed, the power of the gaming machine is turned off.
When switching from FF to ON, the chips of the gaming machine and the matching device are turned on, and the Japanese Patent Application No. 03-118120 is disclosed.
In the gaming machine control chip disclosed in the above publication, a security check is performed by scanning and encrypting a user program stored in a storage means in accordance with a predetermined encryption algorithm incorporated in the chip. Then, the security code is collated in both chips at the beginning of the start. In the device according to the present invention, data such as the security code of the gaming machine data bus is transmitted to the signal comparison circuit via the input circuit, and the collation device is used. The data is also input to the signal comparison circuit from a legitimate CPU and a copy ROM mounted on the CPU. The data on the data bus input from both sides is compared in a signal comparison circuit. As a result, illegality when the CPU or the storage means is simply replaced is checked. Note that the CPU of the gaming machine and the C
It is impossible to completely synchronize the PU with the PU, and it is inevitable that a slight shift will occur. A clock is used to correct for data deviations of several clocks, and an error is displayed when they do not match continuously.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. In FIG. 1, reference numeral 1 denotes a control board mounted on a gaming machine. The control board 1 has a ROM 2 storing programs and the like, and a CPU 3 for controlling the gaming machine according to the programs stored in the ROM 2 mounted thereon. In the control board 1, an application program, a certification code indicating that the application program has been authenticated, and the like are stored in the ROM 2 in advance, and the CPU 3 stores the program stored in the ROM 2 before the operation of the gaming machine. An algorithm for checking whether or not is an authorized one is provided in an identification circuit in the CPU 3, and scans an application program in the ROM 2 to calculate a predetermined authentication code, and the authentication code is calculated in advance. If the authentication code matches, the application It is configured to operate the gaming machine by executing the ram.

Next, in FIG. 1, reference numeral 4 denotes an IC clip 5 (FIG. 2) for extracting a signal by connecting to a pin of the CPU 3 of the control board 1 to be inspected and a signal extracted by the IC clip 5 A signal input cable 6 for transmitting to the verification device, and a signal input circuit 7 for supplying a signal or the like transmitted from the signal input cable 6 to an internal circuit.
A legitimate CPU 9 and a legitimate copy ROM 8 connected to the signal input circuit 7;
CP connected to U8 and the copy ROM 8 to be inspected
Data on data bus transmitted from U3 and regular CP
A signal comparing circuit 10 for taking in and comparing data on a data bus transmitted from U9, and a filter of 8-bit number of clocks oscillated from a 24 MHz clock 13 disposed therein for detecting a deviation signal detected by the signal comparing circuit 10. , An error detection circuit 12 that detects an error when the data shift continues for, for example, eight clocks or more, and a power LED 14a that is turned on while the power of the gaming machine is ON, and the error detection circuit 12 detects an error. Time, abnormal LE
The display unit 14 turns on D14b and turns on the end LED 14c when the verification is completed. Normally, the verification is terminated normally by the end signal of the regular CPU 9.

Hereinafter, the operation of the apparatus according to the present embodiment will be described with reference to the drawings shown in FIGS. (1) As shown in FIG. 4, the apparatus according to the present embodiment is supplied with power and external control bus signals (SRSTO, URST).
And the clock signal (CLKOA) is supplied and SRS
Collation is started from the rise of TO. (2) Each input signal of data, address, control signal, and clock signal from the CPU 3 to be inspected is input to the comparison circuit via a driver (for example, 74HC541) (FIG. 5). (3) Since the signal on the data bus of the CPU 3 to be inspected is considered to be different from the other signals and different from the signal on the data bus of the CPU 9 of the verification device, an enable pulse is generated at the timing of the memory read signal. And
These are latched (FIG. 6). (4) Each signal of the CPU 9 inside the collation device and each signal of the CPU 3 to be inspected are compared by the comparison circuit in the signal comparison circuit 10, and a signal deviation is set as an “H” level signal in each signal block unit. Detect (FIG. 7). (5) In order to determine whether the signals detected by each signal comparison circuit 10 are the same or not, an 8-bit shift register is operated with a 24 MHz clock and continuously operates at 24 MHz.
If the deviation of the signal during the period of 8 clocks of Hz is "H",
The compared signals are determined to be different signals, detected as errors, the error holding signal is held as "H", and output as an abnormal signal (FIG. 8). (6) The collation device built-in CPU 9 ends the security check, detects the M1 signal when the operation code in the ROM 8 is fetched, and outputs this as an end signal, thereby completing the collation. In addition, the transition of the end signal gates the error signal and the end signal, and inhibits holding of a new error. (7) As a result, the power LED is turned on when the power is turned on, the abnormal LED E is turned on when an abnormal signal in the data bus is output, and the end LED is turned on when the security check is completed. An inspection can be performed to determine whether the CPU 3 and the ROM 2 to be inspected are genuine.

Although the above description has been made on the chip collation during the security check, the collation device according to the present embodiment does not terminate the collation after the security check is completed, and compares the data on the data bus even during the game. It is also possible to collate a gaming machine that has performed an illegal act such as switching the chip on the gaming machine control board from an authorized one to an unauthorized one after the security check is completed.

[0010] In this case, C
The data on the data bus transmitted from the PU 9 must be controlled so that when the CPU 3 to be inspected reads and writes data from / to the I / O, only the CPU 3 to be inspected performs this operation. And only the data match needs to be compared. Therefore, as shown in FIG. 3, the data bus to be inspected is connected to the verification device through the tri-state circuit 16, and the tri-state circuit is turned ON only when the read signal RD other than the instruction fetch is active.
You can do it.

[0011]

As described above, the apparatus according to the present invention is mounted on the control board of the gaming machine to be inspected by mounting the type-certified regular CPU and the copy ROM on the verification apparatus. Since the system is configured to verify whether the CPU or ROM is genuine, the operator can easily perform the inspection simply by turning on the power after connecting the IC clip of the verification device to the pin of the CPU. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram of an apparatus showing an embodiment of the apparatus according to the present invention.

FIG. 2 is a front view of the apparatus showing an embodiment of the apparatus according to the present invention.

FIG. 3 is a circuit diagram showing a connection relationship between a data bus of a gaming machine to be inspected and a data bus of a verification device.

FIG. 4 shows the CPU of the gaming machine to be inspected and the CP of the verification device.
FIG. 4 is a circuit diagram showing a connection relationship of U.

FIG. 5 is a circuit diagram for inputting a signal of each bus of a CPU of a gaming machine to be inspected to a comparison circuit.

FIG. 6 is a time chart showing a method of latching a signal on a data bus.

FIG. 7 is a time chart showing detection of a signal deviation in the signal comparison circuit.

FIG. 8 is a time chart when an abnormal state is detected from a signal shift.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 gaming machine control board 2 ROM (gaming machine) 3 CPU (gaming machine) 4 verification device 5 IC clip 6 signal input cable 7 signal input circuit 8 regular ROM 9 regular CPU 10 signal comparison circuit 12 error detection circuit 14 display unit

Claims (1)

[Claims] 1. A storage device in which a control program for controlling a gaming machine is stored, and a C configured to control the gaming machine based on the program stored in the storage device.
In a gaming machine having a microcomputer chip (hereinafter referred to as a chip) for controlling a gaming machine including a PU, an IC clip for connecting the chip to a pin of the chip for inspecting the chip, and the IC clip. A signal input cable and a signal input unit for inputting a signal of a data bus of the connected chip, and a regular CPU and a memory, which have been certified by a third-party inspection organization and which are mounted for verifying the gaming machine control chip. Means, a signal comparison circuit for comparing and comparing the data bus signal of the gaming machine control chip input through the signal input unit with the data bus signal of the legitimate CPU and the storage means, and detection by the signal comparison circuit An error detection circuit that detects an error when the deviation of the detected signal continues for several clock periods or more, and an error detected by the error detection circuit. A display unit for lighting an abnormal signal when issued, wherein the IC clip is configured to be checked by clipping the IC clip to a chip installed in the game machine. apparatus.