JPH10240622A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory controller capable of a protective processing and an unprotective processing to a flash memory by the normal read access to a CPU. SOLUTION: The CPU 10 supplies the low-order addresses of plural address signals to be supplied to the flash memory 50 at the time of performing the protective processing and the unprotective processing to a low-order address setting register 14 beforehand. Even in the case that the bit width of the internal data bus of the CPU 10 is larger than the bit width of an external data bus and plural addresses are outputted from the CPU 10 in the read access of one time, since the low-order addresses are replaced in an address selection circuit 15, the protective processing or the unprotective processing is performed by the normal read operation of the CPU 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device for controlling a data read / write operation with respect to a nonvolatile memory device, and more particularly, to a data write permission or a write inhibition with respect to a flash memory. The present invention relates to a memory control device for controlling.

[0002]

2. Description of the Related Art When erasing and writing stored data in a flash memory which is a nonvolatile semiconductor memory capable of electrically writing and erasing data, the flash memory is provided to prevent erroneous writing. It is necessary to cancel the write-protection function that has been performed. Such a process is hereinafter referred to as an unprotect process.

After the necessary data has been written, the write inhibit function must be activated again. Such processing is hereinafter referred to as protection processing.

In the protection processing and the unprotection processing of the flash memory, as described below, a read operation (hereinafter, referred to as read access) is performed on a plurality of predetermined addresses in a predetermined order (combination). It is performed by

FIG. 3 shows a central processing unit (hereinafter referred to as a CPU).
FIG. 2 is a diagram conceptually showing data exchange when the flash memory 50 is directly connected to the flash memory 50.

First, the operation of reading data from or writing data to the flash memory 50 will be briefly described below.

In a data read operation, the CPU 10 activates a read control signal for the flash memory 50 and also supplies an address signal Add [15. . 0]. In response, flash memory 50 returns read data from the memory cell selected by the address signal to CPU 10, thereby completing one read operation. However, as described later, when the number of bits of the internal data bus of the CPU does not match the number of bits of the external data bus, one unit of the read operation period includes a plurality of data read operations.

In the data write operation, the CPU 10 activates a write control signal for the flash memory 50 and also sends an address signal Add [15. . 0]. In response, flash memory 50 completes one read operation by writing the write data given from CPU 10 to the memory cell selected by the address signal.

Next, the protection processing of the flash memory is performed, for example, by inputting an address as O in hexadecimal notation.
x1823, Ox1820, Ox1822, Ox0418, Ox041B, Ox041
This is implemented by performing read access in the order of address 9, address Ox040A.

[0010] The unprotect processing is performed in hexadecimal notation at addresses Ox1823, Ox1820, and Ox182.
Address 2, Ox0418, Address Ox041B, Ox0
This is implemented by performing read access in the order of address 419 and address Ox041A.

SPARK (Scalable Proc)
essor ARArchitecture (registered trademark))
Architecture CPU has 32 internal data buses
On the other hand, if the external data bus is used as 16 bits, a total of 32 bits of data are read by reading 16-bit data twice for consecutive addresses during read access.

That is, in this case, two data read operations are included in one unit read operation period.

[0013] In order to maintain consistency with the operation of the cache memory existing in the CPU, the data size of 32 bits must be maintained regardless of whether the data size is 8 bits or 16 bits. This is because reading must be performed.

When the CPU connects a flash memory with an external data bus of 16 bits or 8 bits, the read access to the target address is performed when the above-described sequence of the protect processing or the unprotect processing is performed. If this operation is performed, a read cycle (referred to as a plurality of read accesses for reading data of 32 bits in total) for consecutive addresses also occurs, so that it is impossible to realize the protect processing and the unprotect processing.

That is, in the cycle in which the CPU 10 reads data from the address Ox1823 of the flash memory, for example, when the external data bus has 16 bits, the CPU operates at the addresses Ox1820 and Ox1822.
Address 2 if the external bus is 8 bits
This is because four addresses of x1820, Ox1821, Ox1822, and Ox1823 are continuously output.

Therefore, conventionally, there are the following two methods for realizing the protection processing / unprotection processing of the flash memory by read access from the CPU of the SPARC architecture.

First, when the external data bus is 32 bits and is the same as the internal data bus of the CPU,
This is based on the fact that the read operation of the CPU is completed in one cycle.

FIG. 4 is a conceptual diagram showing an example of a configuration for matching the number of bits of the internal data bus in the CPU 10 with the number of bits of the external data bus.

That is, the data length of the data input / output of the flash memory is 8 bits, and the flash memory 1
When the data bus per unit is 8 bits, at least four flash memories are connected to the CPU 10 as shown in FIG. With such a configuration, the bit length of the external data bus as viewed from the CPU 10 is 8 × 4 = 32 bits, which matches the number of bits of the internal data bus. As a result, the read operation of the CPU 10 is completed in one cycle, and the CPU 10 can give the address to the flash memory 50 one address at a time in the read operation for the protection process or the unprotect process.

However, such a configuration requires a plurality of flash memories, which is disadvantageous in that the cost and the mounting area increase.

Second, when the CPU 10 performs a write operation on data having a size equal to or less than the bit width of the external data bus, it utilizes the fact that an access cycle occurs only once. For this purpose, an interface circuit having the following special functions controlled by the CPU 10 is interposed between the CPU 10 and the flash memory.

That is, when performing the protect processing or the unprotect processing, the pulse of the write control signal from the CPU 10 is switched to the read control input terminal of the flash memory and applied.

However, in such a configuration, the CP
Since U10 performs a write operation to the outside and the flash memory performs a read operation to the outside, if the CPU 10 and the flash memory 50 are connected by the same data bus, data collision will occur. For this reason, the above-mentioned interface circuit includes the flash memory 50 and C
It is necessary to have a circuit configuration capable of disconnecting the data bus between the PUs 10, and there is a problem that the number of external pins increases when such an interface circuit is realized by a custom LSI.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is possible to perform a protect process or an unprotect process for a nonvolatile memory such as a flash memory by a normal read operation of a CPU. It is to provide a memory control device.

Another object of the present invention is to provide a memory control device capable of suppressing an increase in the number of input / output pins even when an interface between a CPU and a flash memory or the like is connected.

[0026]

According to a first aspect of the present invention, there is provided a memory control device, wherein a data write enable instruction and a data write inhibit instruction are designated by a predetermined combination of read operations for a plurality of predetermined addresses. A memory control device for controlling a data read operation and a write operation for a nonvolatile memory device having a word length of a first bit number, wherein the length of the second bit number is larger than the first bit number In the operation of fetching data from the external memory, the lower bit of the read address given to the external memory during the unit read operation is continuously changed so that the second bit Arithmetic processing means for controlling the read operation of the external memory so as to take in a number of data, and storage for holding lower addresses of a plurality of predetermined addresses in association with a predetermined combination In the case where the stage and the arithmetic processing means exchange data with a nonvolatile memory device as an external memory, when giving a write enable instruction and a write inhibit instruction, the lower address of the output read address is set. Address replacement means for sequentially replacing by a lower address of a plurality of predetermined addresses held in the storage means for each unit read operation period.

According to a second aspect of the present invention, in addition to the configuration of the first aspect, the storage means further comprises:
A register memory having a storage capacity of at least the number of bits of the lower address of the number of address signals corresponding to the predetermined combination is provided. Operation mode control means for controlling the replacement of the lower address of the read address and detecting the output of the read inhibit instruction, and counting the number of unit read operations of the arithmetic processing means under the control of the operation mode control means, Counting means for selecting a corresponding lower address in the storage means, and receiving the lower address of the read addresses from the arithmetic processing means and the lower address selected in the storage means under the control of the operation mode control means, An address that outputs one of the data to the nonvolatile memory device according to whether the data write enable instruction or the write inhibit instruction is output. And a select means.

According to a third aspect of the present invention, in the memory controller according to the second aspect, the lower address of the address corresponding to the predetermined combination is stored in accordance with the write control from the arithmetic processing means. The means are provided from the arithmetic processing means.

[0029]

FIG. 1 is a schematic block diagram showing a configuration of a memory control device 1000 according to an embodiment of the present invention.

Referring to FIG. 1, memory control device 1000
The CPU 10 controls the operation of reading or writing data from or to the flash memory 50, and, as will be described later, during a protection process or an unprotect process, a lower address Add [1] of an address signal given to the flash memory during the process. . . 0] are stored in correspondence with the given order, for example, a lower address setting register 14 including seven registers,
Each time a read control signal is input from the PU 10, the read register selection circuit 12 counts the number and sequentially instructs a plurality of registers in the lower address setting register 14 to output data, and a lower address Add from the CPU 10.
[1. . 0] and the lower address Add [1. . 0], and controls an interface operation between the CPU 10 and the flash memory 50 at the time of protection processing or unprotection processing to output one of them, and performs a switching operation of the lower address of the address selection circuit 15. An operation mode control register 13 for controlling and controlling the reset operation of the read register selection circuit 12 is included.

FIG. 2 is a block diagram showing the configuration of the read register selection circuit 12 and the lower address setting register 14 in more detail in the configuration shown in FIG.

Referring to FIG. 2, lower address setting register 14 stores a lower address Add [1... Of an address given to flash memory 50 at the time of protect processing or unprotect processing. . 0] and a plurality of (seven in FIG. 2) registers 18 to 24, and a CPU.
10 from the write control signal and the address signal Add.
[2. . 0] in response to the address signal Add [2. . 0], and a selector circuit 17 that outputs the data to any one of the registers 18 to 24 selected by [0].

The read register selection circuit 12 is controlled by the operation mode control register 13, and when the CPU 10 instructs the start of the protection processing or the unprotection processing, the readout register selection circuit 12 counts the count value according to the counter reset signal from the operation mode control register 13. And a counter circuit 26 for counting the number of times the count-up signal output from the operation mode control register 13 is activated each time the read control signal from the CPU 10 is activated,
6 includes a selector circuit 15 for sequentially selecting the output values of the registers 18 to 24 according to the output of the selector 6 and outputting the selected output value to the address selection circuit 15.

Next, the operation of the memory control circuit 1000 will be described. First, the CPU 10 assigns the lower addresses Add [1... Of the addresses to be given to the flash memory to the registers 18 to 24 depending on whether to perform the protect processing or the unprotect processing. . 0] is written in advance.

In the example shown in FIG.
For Ox02, Ox01, Ox03, Ox00,
Ox02, Ox00, and Ox03 are set. This is because, when the flash memory is connected to the 8-bit bus, in the protection processing, addresses that need to be continuously given to the flash memory 50, addresses Ox1823, Ox1820, Ox1822, and Ox041
8, Ox041B, Ox0419, Ox0
Lower 2 bits of address 40A. However, this association is, as described later, with the lower two addresses of Ox040A.
The bit is Ox02, the lower two bits of address Ox0419 are Ox01, and so on.
The order corresponds in reverse, such as the lower two bits of the address being Ox03.

When performing a protect process or an unprotect process on the flash memory 50 from the CPU 10, the register 1 in the lower address setting register 14
8 to 24, a predetermined lower address Add [1. . 0], the CPU 10 sets the operation mode control register 13
Make the settings for

Accordingly, the operation mode control register 13
The reset operation is instructed to the counter 26 in the read register selection circuit 12 and the output from the lower address setting register 14 is sent to the flash memory 5 to the address selection circuit 15.
An instruction to select a state to be given to 0 is given.

Thereafter, the CPU 10 stores the addresses Ox1823, Ox1820,
The read operation is performed in the order of addresses Ox1822, Ox0418, Ox041B, Ox0419, and Ox040A.

At this time, the CPU 10 reads, for example, Ox1823 in order to fetch 32-bit data from the outside.
In the read operation for the address of the address, Ox1
820 address, Ox1821 address, Ox1822 address, O
The four addresses of x1823 are continuously output.

Here, the lower two bits Add [1. . 0] is the value from the register 24 in the lower address setting register 14, Ox
Replace with 03.

Next, when the CPU 10 performs a read operation on the address Ox1820, the count value of the counter 26 in the read selection register 12 is incremented by one.
The Ox00 held in the register 23 is stored in the lower two bits Add [1. . 0] to the flash memory 50.

By repeating the same read access a total of seven times, a read address necessary for protection / unprotection can be given to the address input of the flash memory, and the flash memory 50 is directly connected to the data bus of the CPU 10. Even in this case, it is possible to realize the protection processing or the unprotection processing.

[0043]

As described above, according to the present invention,
By connecting a non-volatile memory such as a flash memory directly to the data bus of the CPU, the protection processing / unprotection processing can be realized by ordinary CPU read access.

Further, the number of input / output pins can be reduced even when the interface between the CPU and the flash memory is constituted by an ASIC (IC for specific use).

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing a configuration of a memory control device 1000 of the present invention.

FIG. 2 is a block diagram showing a configuration of a read register control circuit 12 and a lower address setting register 14 shown in FIG.

FIG. 3 is a conceptual diagram showing a configuration of a conventional interface between a CPU 10 and a flash memory 50.

FIG. 4 is a schematic block diagram showing a configuration that enables a protection process with normal read access of a conventional CPU 10.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 CPU 12 Read register selection circuit 13 Operation mode control register circuit 14 Lower address setting register circuit 15 Address selection circuit 17, 25 Selector circuit 18-24 Register 26 Counter circuit 50 Flash memory 1000 Memory control device

Claims (3)

[Claims] A nonvolatile memory in which a data write enable instruction and a data write inhibit instruction are designated by a predetermined combination of read operations for a plurality of predetermined addresses, and a word length of input / output data is the first number of bits. A memory control device for controlling a data read operation and a data write operation with respect to a device, comprising: an internal data bus having a length of a second bit number larger than the first bit number; In the fetch operation, the lower address of the read address given to the external memory is continuously changed during the unit read operation, so that the data of the second number of bits is fetched. Arithmetic processing means for controlling a read operation of the external memory; storage means for holding lower addresses of the predetermined plurality of addresses in association with the predetermined combination; When the stage transmits / receives data to / from the non-volatile memory device as the external memory, and gives the write enable instruction and the write inhibit instruction, the lower address of the output read address is A memory control device comprising: an address replacement unit that sequentially replaces the predetermined plurality of addresses stored in the storage unit with lower addresses for each unit read operation period. 2. The storage unit includes a register memory having a storage capacity of at least the number of bits of the lower address of the number of address signals corresponding to the predetermined combination. An operation mode control means for detecting the output of a data write enable instruction and a data write inhibit instruction under the control of the means, and controlling a replacement process of a lower address of the read address; Counting means for counting the number of unit read operations of the arithmetic processing means, and selecting the corresponding lower address in the storage means; controlled by the operation mode control means, In response to the lower address of the read addresses and the lower address selected in the storage means, a data write enable instruction and a write Inhibition instruction, depending on whether is output, and an address selecting means for outputting either said non-volatile memory device, the memory control device according to claim 1. 3. The arithmetic processing unit according to claim 2, wherein a lower address of an address corresponding to the predetermined combination is provided from the arithmetic processing unit to the storage unit in accordance with write control from the arithmetic processing unit. Memory controller.