JPH10240184A - Fluorescent light display drive control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a noise level by sequentially drive-controlling ON and/or OFF each of plurality of active elements for lightning one digit or segment of a fluorescent light display part based on a fixed order. SOLUTION: A segment/digit drive-control circuit 6 has a means of connecting plural segment and digits and n-pieces of high-voltage-resistant transistors provided for each segment and each digit, etc. Also, from the plural segments and digits, those to be controlled ON/OFF are designated according to fixed selection signals. And, to each designated segment and digit, according to signals from a rising edge synchronizing circuit 4 and a falling edge synchronizing circuit 5, the n-pieces of the high-voltage-resistant transistors provided for each segment and digit are sequentially controlled ON/OFF, and thus, the segment or digit is driven.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive control device for a fluorescent display unit having digits, segments and the like.

[0002]

2. Description of the Related Art A fluorescent display tube having digits and segments has been conventionally known as one of display devices. FIG. 5 shows a conventional driving device for such a fluorescent display tube.
This will be described with reference to FIG.

That is, as shown in FIG. 5, a digit or segment terminal 100 is a terminal of one digit or one segment in a fluorescent display tube. The high breakdown voltage transistor 111 is a driving transistor for driving one digit or one segment.
The data signal 112 is a signal for turning on and off the high voltage transistor 111. Also, pull-down resistor 11
Reference numeral 3 denotes a resistor for lowering the power supply level to a high withstand voltage when the digit or segment is turned off. The protection transistor 114 is a protection transistor for protecting against surge (external noise) destruction.

Next, the operation of the above configuration will be described.

That is, one digit or one segment terminal 100 is driven by one high breakdown voltage transistor 111. When a plurality of digits or segments are simultaneously turned on / off, the number and the number of the terminals are determined. The same number of high voltage transistors 111 are simultaneously turned on / off by the timing of the data signal 112.
The drive control is performed.

[0006]

However, in such a conventional configuration, when the number of digits or segment terminals is small, the possibility of leakage light emission due to noise generated at the time of ON / OFF is low. When the number of segments increases, for example, due to the simultaneous change of a plurality of segment terminals, a sudden rise of the segment signal causes noise in the digit signal due to the capacitance and resistance components of the fluorescent display tube. However, there is a problem that leakage light emission occurs.

[0007] Here, the mechanism of occurrence of leakage light emission will be described.

FIG. 6 shows a segment and a segment capacitance component (CSEG-SEG in the figure) inside the fluorescent display tube driven by the LSI having the configuration shown in FIG. 5, and a segment and digit capacitance component (FIG. 5). , CSEG-DGT
), The segment resistance component (RSE in the figure)
FIG. 2 is a circuit diagram modeled using G) and a digit resistance component (shown as RDGT in the figure).

FIG. 7 shows one transistor level simulation when the conventional driving circuit shown in FIG. 5 is connected to a modeling circuit for a fluorescent display tube (see FIG. 6). FIG. 4 shows an output waveform from the drive circuit for each terminal to a segment terminal and one digit terminal, and a noise waveform generated from the segment and the digit. In FIG. 7, the vertical axis is voltage (V),
The horizontal axis is time (μS). As described above, the conventional drive circuit shown in FIG. 5 is a circuit in which one segment and one digit are each constituted by one drive transistor 111 inside the LSI.

Referring to FIG. 7, one segment is turned from a lighting state (ON state) to a light OFF (OF) centering on one segment.
(F state) and the noise generated when the lighting state is set again will be described.

That is, as shown in FIG. 2, the input waveform 12 to the high breakdown voltage transistor 111 is between the horizontal axis 0 and t1.
1 indicates 0V. During this time, the output waveform 122 from the drive circuit to the segment terminal 100 indicates 5 V, and this segment is in a lighting state.

Next, at time t1, an input waveform 121 to the high voltage transistor 111 (data signal 1 shown in FIG. 5)
(Corresponding to 12 waveforms) changes from 0V to 5V. At this time, the segment is turned off. That is, the output waveform 122 from the drive circuit to the segment terminal 100 is from −5 V to −40.
It shows a drastic change of falling to V. Therefore, the segment noise waveform 1
As shown by 23, noise occurs as a change from -40V to about -52V.

Further, at time t2, the input waveform 121 to the high breakdown voltage transistor 111 changes from 5V to 0V again. At this time, the segment lights up again. That is, the output waveform 122 from the drive circuit to the segment terminal 100 is
It shows a very rapid change, that is, a sudden rise from -40V to 5V. Therefore, with the rapid change, as shown by the segment noise waveform 123, -40V
Noise occurs as a sudden change from about to 5V.

[0014] Due to the generation of such noise, digit noise is generated in the digit signal.

That is, in FIG. 1, the digit noise waveform 124 generated at t2 is from -40V to about -2V.
Is a noise waveform showing a rapid change between the above, and the digit noise voltage due to this is about 38V.

Therefore, the digit noise waveform 124
The level exceeds the filament bias level of the fluorescent display tube, and a digit that is not displayed with characters is weakly lit (this is called leakage light emission).

An object of the present invention is to provide a fluorescent display unit drive control device capable of further reducing the noise level as compared with the related art in consideration of such problems of the conventional device.

[0018]

According to the present invention, there is provided a fluorescent display unit having digits and / or segments, and a plurality of units for turning on and / or off one digit or segment of the fluorescent display unit. A fluorescent display comprising: a plurality of drive elements; and control means for performing drive control for sequentially turning on and / or sequentially turning off each of the plurality of drive elements based on a predetermined order. It is a unit drive control device.

According to a second aspect of the present invention, the driving element is a transistor, and in the predetermined order, when each of the transistors is sequentially turned on, a smaller one of the currents flowing through each of the transistors is smaller. The transistor that flows is turned on earlier, and the transistors are sequentially turned on.
2. The fluorescent display unit drive control device according to claim 1, wherein, when performing FF, among the respective currents flowing through the respective transistors, a transistor having a larger current flows is turned off first.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a fluorescent display unit drive control device according to the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram of a fluorescent display unit drive control device according to an embodiment of the present invention. FIG. 1 is a diagram mainly showing a portion for generating a timing signal used for driving a plurality of segments and digits. FIG. 2 is a diagram showing a part of the segment digit drive circuit 6, which is a part of FIG. 1, in further detail.
That is, FIG. 2 is a circuit configuration diagram of a plurality of high breakdown voltage transistors for driving (turning on / off) one segment or one digit out of the plurality of segments or digits. The circuit configuration of other segments and digits of the plurality of segments and digits is basically the same as that of FIG. In addition, the same reference numerals are given to basically the same components as those described in FIG. The configuration of the present embodiment will be described with reference to these drawings.

As shown in FIG. 1, the frequency dividing circuit 1 is a circuit for dividing the frequency of the reference clock 11. The rising time setting decoder 2 includes a driving high breakdown voltage transistor TR1 provided for each segment digit, which will be described later.
TRn (see FIG. 2). The fall time setting decoder 3 is a means for setting the fall time of the high voltage transistors TR1 to TRn for driving. Each of these decoders 2 and 3 operates in synchronization with the output signal from the frequency divider 1. The rising edge synchronization circuit 4
This is a circuit for synchronizing the output signal of the rising time setting decoder 2 with the rising edge of the reference clock 11. The falling edge synchronizing circuit 5 is a circuit for synchronizing the output signal of the rising time setting decoder 3 with the falling edge of the reference clock 11.

The segment / digit drive circuit 6 is a circuit provided with means for connecting to a plurality of segments and digits, and n high voltage transistors provided for each of the plurality of segments and digits. is there. The segment / digit drive circuit 6 specifies a plurality of segments or digits from a predetermined select signal (not shown) to specify a segment or digit to be subjected to ON / OFF control, and specifies the specified segment or digit. For the rising edge synchronization circuit 4
And n high-voltage transistors provided for each segment or digit, based on the timing signal from the edge synchronization circuit 5 and ON / OFF sequentially.
This is a means for driving a segment or digit.

With respect to the rise / fall time of each segment or digit, the rise time setting decoder 2 / fall time setting decoder 3
Is a configuration in which control is performed by setting rise / fall times of n high breakdown voltage transistors TR1 to TRn provided for each segment.

A plurality of segments are composed of an X group and a Y group.
Separated into groups. The segments separated into these two groups are separated from the timing signal by n signals generated by the rising edge synchronizing circuit 4 and the falling edge synchronizing circuit 5 for a different purpose, for n purposes. Each high breakdown voltage transistor TR1 to TRn
Are turned on / off, respectively (see FIG. 3). By turning on / off in this manner, a time difference of half a clock can be provided, and further, simultaneous changes can be reduced, and the effect that leakage light emission can be prevented can be exhibited. Here, FIG. 3 shows ON / OF of each segment divided into the X group and the Y group.
It is a figure for explaining timing of F.

Next, the configuration of n high breakdown voltage transistors for driving one segment or one digit will be described with reference to FIG.

Here, the important point in the configuration is that, as described with reference to FIG. 5, in the conventional configuration, for example, one high breakdown voltage transistor is used to drive one segment. On the other hand, in the present embodiment, the conventional configuration is such that one high breakdown voltage transistor is divided into n pieces, and the method of division is that the width and length of each transistor formed on the integrated circuit substrate are different. Focusing on the ratio, n high breakdown voltage transistors having different ratio values are formed. It should be noted that how to control the timing at the time of ON / OFF is also an important point of the present embodiment, which will be further described later.

In FIG. 2, the same elements as those described with reference to FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 2, n high breakdown voltage transistors TR1 to TRn are connected to TR1 control signal terminals 21 to TRn.
N NAND circuits 2 each receiving a signal from a control signal terminal 25 and a data signal 8 from a data signal terminal 26
In this configuration, ON / OFF control is performed by output signals 7 to 31 respectively.

Here, each of the high breakdown voltage transistors TR1 to TR
The ratio of the width (W) to the length (L) of Rn, that is, W / L will be described.

That is, not only is the W / L ratio determined based on the current capability, but also in the arrangement of the divided transistors in the layout design of the LSI, surge (external noise) protection and PAD of one terminal are required. In addition, the size of the device is made as small as possible, and a shape that does not provide a useless area is also considered.

Next, the operation of this embodiment with the above configuration will be described. The biggest feature of the operation of the present embodiment is that
Instead of turning on / off one segment, for example, with only one high-breakdown-voltage transistor 111 as in the prior art, n high-breakdown-voltage transistors TR1 to TRn are sequentially arranged in a predetermined order with a predetermined time difference. ON, and ON again
In this case, a different time difference from that of the case (1) is provided, and the turning off is performed in another order.

Specifically, each of the n transistors is turned on.
In this case, the transistor TR1 having the smallest value of W / L determined for each transistor is turned on first,
Next, the transistor TR2 having the second smallest W / L value is turned on, and sequentially turned on according to the W / L value.
The transistor TRn having the largest value is turned on. Here, as described above, the magnitude relation of the value of W / L corresponds to the magnitude relation of the current value flowing through each transistor.

When turning off the n transistors, the transistor TRn having the largest W / L value determined for each transistor is turned off first, and then the second largest W / L transistor is turned off. Value transistor TR (n-
1) is turned off, sequentially turned off according to the value of W / L, and finally the transistor TR1 is turned off.

Incidentally, the reduction of the noise level during the ON control is intended to reduce the occurrence of leakage light emission.
The purpose of reducing the noise level during control is to ensure the reliability of LSI components due to the generated noise.

Here, a noise level generated at the time of the above-described ON control and OFF control was simulated using the circuit model shown in FIG. 6 with reference to FIGS. explain.

In FIG. 4, between time t3 and time t5,
The waveform 80 (segment input waveform) of the data signal 8 described with reference to FIG. 2 is always H, and TR1 to TRn are ON / OFF controlled only by the control signals 21 to 25. t3-t
During the period 4, TRn is first turned off by the control signal 25, and then TR (n-1) to TR1 are sequentially turned off. This is shown in the left half of FIG. That is, TR
As (n-1) to TR1 are sequentially turned off, the output waveform 125 to the segment digit terminal 100 is increased.
The (segment output waveform) sequentially changes from 5V to -40V in almost the left half of FIG. This change
This is a gradual change as compared with a sudden change like the output waveform 122 shown in FIG.

The segment noise 12 generated at this time
6 is represented as a waveform that changes from -40 V to -48 V in FIG. The segment noise 126 is
It can be seen that the noise waveforms are alleviated as compared with the noise waveforms 123 and 124 shown in FIG.

At time t4, TR1 is turned on, and TR2 to TRn are sequentially turned on until t5. Also in this case, the output waveform 125 is more gradually
It shows a change of rising from 40V to 5V.

With this configuration, the digit noise 127 on the digit signal is reduced to about 8 V as compared with the case of FIG.

Therefore, the digit noise level 127
Does not exceed the filament bias level of the fluorescent display tube, it is possible to prevent leakage light emission.

According to the above-described embodiment, the noise on the digit due to the simultaneous change of the segment and the digit is reduced, and the light emission of the fluorescent display tube is prevented from leaking.
This has the effect of preventing the destruction of LSI components and further ensuring reliability.

In the above-described embodiment, the case where ON / OFF timing is sequentially shifted for each digit and segment has been described. However, the present invention is not limited to this. For example, the control target may be any one of digit and segment. Alternatively, a configuration may be adopted in which either one of the ON and OFF timings is sequentially shifted.

[0044]

As is apparent from the above description, the present invention has an advantage that the noise level can be further reduced as compared with the prior art.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a fluorescent display unit drive control device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a part of the inside of the segment digit drive circuit of the present embodiment in more detail;

FIG. 3 is a diagram for explaining ON / OFF timing of each segment separated into an X group and a Y group according to the embodiment;

FIG. 4 is an explanatory diagram of a simulation according to the present embodiment.

FIG. 5 is a schematic block diagram of a conventional segment digit drive circuit of a fluorescent display unit.

FIG. 6 is an explanatory diagram of a modeling circuit of a fluorescent display tube.

FIG. 7 is an explanatory diagram of a simulation of a noise level generated in a conventional segment / digit drive circuit of a fluorescent display unit.

[Explanation of symbols]

 1 Divider circuit 2 Rise time setting decoder 3 Fall time setting decoder 4 Rising edge synchronization circuit 5 Falling edge synchronization circuit 6 Segment digit drive circuit 11 Reference clock

Claims (2)

[Claims] 1. A fluorescent display unit having digits and / or segments; a plurality of driving elements for turning on and / or off one digit or segment of the fluorescent display unit; A control unit for performing drive control for sequentially turning on and / or sequentially turning off each of the driving elements based on a predetermined order for each of them. 2. The method according to claim 1, wherein the driving element is a transistor, and the predetermined order is such that, when the respective transistors are sequentially turned on, of the respective currents flowing through the respective transistors,
The transistor with the smaller current flows first turns on,
2. The fluorescent display unit drive control device according to claim 1, wherein, when the transistors are sequentially turned off, a transistor in which a larger current flows among the respective currents flowing through the respective transistors is turned off first.