JPH10233762A - Data transmission reception system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the logic in the configuration of an LRC control section so as to realize the configuration through duplicate configuration of LRC code latch registers only in the system where two same longitudinal redundancy check LRC codes are generated independently of whether both paths are available or only one path is available as to two packet LRC codes used to detect an error of packet data on duplicate data transmission paths. SOLUTION: As the configuration of an LRC control section 50 in a packet data transmission reception section 60, a single LRC code arithmetic section 52 and a single pre-fetch register 55 are employed and two LRC code latch registers are used. In the case that only one of duplicate data transmission paths is available, a latch timing of the two LRC code latch registers 53a, 53b and a select signal of a selector 54 are switched alternately.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a reduction in the logical scale of an LRC control unit in a packet data transmitting / receiving unit connected to a duplicated data transfer path.

[0002]

2. Description of the Related Art In transmitting and receiving packet data on a data transfer path, an LRC having a data error detection function is used to prevent data loss due to a failure in the data transfer path.
The (horizontal redundancy check) method is generally used. At the time of transmitting a packet, an LRC code generated by a predetermined operation from the packet data is added to the end of the packet and transmitted to the data transfer path. At the time of packet reception, the LRC code generated by the same method as at the time of transmission is compared with the LRC code at the end of the packet from the packet data received from the data transfer path, and when they do not match, the packet data changes on the data transfer path. Means that the LRC error has occurred. The configuration on the circuit is such that an LRC control unit is provided in a circuit (packet data transmission / reception unit) for transmitting / receiving packet data to generate an LRC code,
Perform RC error detection.

In order to realize a fault-tolerant packet data transfer system, a method of duplicating a data transfer path and a packet data transmitting / receiving unit is generally used. If both data transfer paths are available (hereinafter referred to as normal operation), as shown in FIG. 2A, 2n data blocks D _{1 to} D _2n constituting one packet are alternately transferred to the duplicated data transfer path. By alternately receiving data blocks during transmission and reception, the number of data blocks transferred on one data transfer path becomes n, so that twice the performance can be realized for one data transfer path. . When one of the data transfer paths cannot be used due to a failure, only the other one of the data transfer paths is used (hereinafter, referred to as a degeneration operation), and as shown in FIG. One packet is transmitted and received by transmitting and receiving D _{1 to} D _2n .

If data transfer paths are duplicated, it is necessary to add an LRC code to the end of the packet for each data transfer path. A packet on the data transfer path is composed of 2n data blocks D _{1 to} D _2n and LRC codes L ₁ and L ₂ . L ₁ and L ₂ are calculated by the following equations.

[0005]

L ₁ = D ₁ ＠D ₃ ＠... ＠D _2n-1 L ₂ = D ₂ ＠D ₄ ＠... ＠D _2n where ＠ is an operator of the LRC code. Equation 1 is L ₁
And the possible logical operators L ₂ is common, show that performing LRC code computation irrespective of the state of the duplexed data transfer path.

During normal operation of the dual data transfer path, as shown in FIG. 2A, LRC codes L ₁ and L ₂ are generated one by one from the data blocks transferred on each data transfer path. In the degenerate operation of the duplicated data transfer path, FIG.
As shown in (b), two LRC codes L ₁ and L ₂ are generated.

[0007]

In order to realize the above-mentioned function, the LRC code generation circuit itself in the LRC control unit has conventionally been duplicated. However, in the present invention, a single LRC code generation circuit is used. By duplicating only the register holding the LRC code, the same function is realized and the logical scale can be simplified.

[0008]

An LRC code generation circuit according to the present invention unifies an LRC code operation unit and an LRC code prefetch register at the preceding stage thereof, and
There is a selector for duplicating only the code holding register and transferring the LRC code from one of the two holding registers to the prefetch register.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments.

FIG. 2 shows a packet data transfer system and a packet format to be transferred. A plurality of adapters 70 for transferring a packet on a duplicated data transfer path have a data transfer control unit 65 and a duplicated packet data transmitting / receiving unit 60, and the packet data transmitting / receiving units 1 and 2 have the same circuit configuration. The data transmission / reception units 1 and 2 are connected to the duplicated data transfer paths 1 and 2, respectively. The data transfer control unit 65 distributes transmission data to the duplicated packet data transmitting / receiving unit 60 and integrates received data from the duplicated packet data transmitting / receiving unit 60.

FIG. 1 is a block diagram of a packet data transmitting / receiving unit 60 according to an embodiment of the present invention. At the time of transmitting the packet data, the transmission data is transmitted to the data transfer path via the selector 21, the data buffer 22, the selector 23, and the driver 24, while the LRC control unit 50 generates an LRC code from the transmission data and sends the LRC code to the end of the packet. The data is transmitted via the selector 23 and the driver 24 in an added form. At the time of receiving packet data, while receiving the received data from the data transfer path via the receiver 25, the selector 21, and the data buffer 22, the LRC control unit 50 adds the LRC code generated from the received data and the end of the received packet data. LRC codes are compared, and if they do not match, an LRC error is determined.

The LRC control unit 50 shown in FIG. 1 will be described in detail. The transmission data or the reception data is selected by the selector 51 as input data for the LRC code calculation, and the selected input data and the LR prefetched by the register 55 are selected.
The LRC code calculation unit 52 generates the next LRC code from the C code, and stores it in the register 53a or the register 53.
Latch at b. Register 53a and register 53b
Is such that, even during the degenerate operation of the duplicated data transfer path, the two LRC codes originally generated on both data transfer paths during the normal operation of the duplicated data transfer path can be generated by one packet data transmitting / receiving unit 60. Have been.
During the normal operation of the duplicated data transfer path, the LRC code output from the LRC code operation unit 52 is stored in the register 53a.
The data is latched only in synchronization with the data transfer timing clock, and is latched by the register 55 via the selector 54. At the time of the degenerate operation of the duplicated data transfer path, the packet data transmitting / receiving unit 60 connected to the transferable path has the LRC
The LRC code output from the code operation unit 52 is alternately latched by the register 53a or 53b in synchronization with the data transfer timing clock when an odd data block is input and when an even data block is input.
Then, the other register of the latched register is selected and latched by the register 55. By the above operation, the LRC code is generated cyclically from the packet data, added to the end of the packet when transmitting data, and when data is received, the LRC code at the end of the received packet and the LRC code generated from the received data are detected as LRC error The comparison is performed by the unit 56, and if they do not match, they are detected as LRC errors.

Switching between the normal operation and the degenerate operation of the duplicated data transfer path is instructed by firmware that controls the entire packet data transfer system. For example, as shown in FIG. 2A, when one of the packet data transmitting / receiving units 60 detects an LRC error when transferring packet data in a normal operation, the firmware receiving the report degenerates the duplicated data transfer path from the normal operation. Switching to operation, FIG. 2 (b)
The packet data is retransmitted as shown in FIG.

FIG. 6 shows the selection signal generating section of the selector 54.
Shown in The LRC operation permission signal is output only during data transfer, and the degeneration operation instruction signal is output according to an instruction from firmware. Two flip-flops 81 and 82
Is reset before the start of data transfer, and the select signal output from the flip-flop 82 becomes the A side. During the normal operation, only the A side remains selected, and during the degeneration operation, the A side and the B side are alternately selected at the rise of the timing clock.

The manner of LRC code generation in the LRC controller 50 in FIG. 1 will be described for the data transfer path 1 side. Figure 3 shows the normal operation of the redundant data transfer path.
The timing chart shown in FIG. 4 will be described with reference to the timing chart shown in FIG.

[0016] In Figure 3, only data transfer path 1 in the odd-numbered data block is transferred, the input number of data blocks is n pieces, also LRC code generated is only L _1. The LRC code operation unit 52 performs an LRC code operation from the input data block D _2i-1 corresponding to the output of the selector 51 and the content A _i-1 of the register 55, and outputs the output A _i to the register 53a at the rising edge of the data transfer timing clock. Latched only on To generate the next LRC code A _{i + 1} from the next data block D _{2i + 1} , the register 55 uses the LRC code A _i of the register 53a.
Need to be prefetched. Since the selector 54 selects only the register 53a, the select signal is fixed to the register 53a side (hereinafter A side). The prefetch timing is a timing shifted by a half phase from the timing clock. Finally, LRC code A _n of n-th latched becomes L ₁ in the register 53a.

In FIG. 4, since the odd-numbered and even-numbered data blocks are transferred in the data transfer path 1, the number of input data blocks is 2n, and the generated LRC
Code is L ₁ and L _2. In LRC code calculating unit 52, and outputs the odd-numbered data blocks D _2i-1 and LRC code A _i from the contents A _i-1 of the register 55, and being latched only in the register 53a at the rising edge of the data transfer timing clock At the same time, the next even-numbered data block D
_In order to generate the next LRC code B _i from _2i, it is necessary to prefetch the LRC code B _i-1 of the register 53b by the register 55, so that the select signal of the selector 54 is switched to the register 53b side (hereinafter B side). Can be
Similarly, even-numbered data blocks D
The LRC code B _i which is generated from the contents B _i-1 of _2i and register 55 simultaneously with the latch in the register 53b, switches the select signal of the selector 54 to the A side. The prefetch timing is a timing shifted by a half phase from the timing clock. Finally, LRC code A _n of n-th latched is L _1, and the the n-th LRC code B _n latched by the register 53b becomes L ₂ in the register 53a.

FIG. 5 shows a conventional packet data transmitting / receiving unit 60.
It is a block diagram of. Selector 21, data buffer 2
2, selector 23, driver 24, and receiver 25 are shown in FIG.
It has the same configuration as. However, the LRC control unit 50
The C code operation units 52a and 52b, the LRC code holding registers 53a and 53b, and the prefetch registers 55a and 55b, that is, the LRC generation circuit itself is duplicated. Since the logical operator の of Expression 1 is common to L ₁ and L ₂ , the LRC control unit 50 like the LRC control unit 50 in the circuit configuration of FIG.
The code operation unit 52 can be shared. In FIG. 5, the prefetch registers 55a and 55b are also duplicated, but as shown in FIG.
By providing the selector 54 for switching the code holding register, the prefetch register can be shared.

[0019]

As described above, according to the present invention, in the packet data transmitting / receiving unit connected to the duplicated data transfer path, the LR
By duplicating only the LRC holding register in the LRC code generation circuit without duplicating the C code generation circuit itself, the same function is realized and the logical scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 shows a packet data transfer system and a packet format.

FIG. 3 is a timing chart showing an operation of the system shown in FIG. 1;

FIG. 4 is a timing chart showing an operation of the system shown in FIG. 1;

FIG. 5 is a block diagram showing a conventional system.

FIG. 6 shows a select signal generation unit of the selector 54.

[Explanation of symbols]

 50: LRC control unit, 51: selector, 52: LRC code operation unit, 53a: LRC code holding register, 53b: LRC code holding register, 54: selector, 55: LRC code prefetch register, 60: packet data transmission / reception unit .

Claims (2)

[Claims] 1. An LRC control unit in a packet data transmitting / receiving unit connected to each of the data transfer routes and a packet data transmitting / receiving unit. The LRC control unit in the packet data transmitting / receiving unit generates an LRC code when transmitting a packet. At the end of the packet, at the time of packet reception, the LRC code generated from the received packet data is compared with the LRC code at the end of the packet to perform LRC error detection. If both data transfer paths can be used, one packet is Each of the LRC codes is distributed in such a manner that a plurality of constituent data blocks are distributed to both paths, and an LRC code is generated from the data blocks distributed to each of the data transfer paths.
A code is added to the end of the packet on each of the data transfer paths. If one of the two data transfer paths cannot be used, the packet data is transferred using only the other data transfer path. Then, the two LRC codes are generated in the LRC control unit by the same operation method as the method, and the two LRC codes are transmitted and received at the end of a packet on one available data transfer path. In the system, the LRC code generation circuit in the LRC control unit includes the LRC code generation circuit.
A data transmission / reception system characterized in that only registers holding two codes are duplicated. 2. An LRC code generation circuit comprising: a selector for selecting one of two LRC code holding registers; a register for prefetching an output of the selector; and an LRC code of the prefetch register and a next LRC code from a data block. LRC code calculator 1 for calculating codes
When only one of the two data transfer paths is unavailable because one of the two data transfer paths cannot be used, the LRC code output from the LRC code calculation unit is changed in the LRC control unit. 2. The LRC according to claim 1, wherein the LRC code holding registers are alternately sorted, the selector is alternately selected from the two LRC code holding registers, and an output of the selector is latched by the prefetch register. 3. The data transmission / reception system according to claim 1, wherein the data transmission / reception system implements a code operation method.