JPH10233720A - Diversity receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the diversity receiver from which normal reception data are obtained even when the receiver receives a strong interference signal. SOLUTION: Reception data which are received by a plurality of antennas and detected by detection circuits 101, 102, 103 are given to an interference detection circuit 200, from which 1st to 3rd interference detection signals are generated. First to third multipliers 201, 202, 203 multiply the 1st to 3rd interference detection signals with 1st to 3rd signals from 1st to 3rd signal strength detection circuits 111, 112, 113 which receive simultaneously a plurality of reception signals respectively to correct the strength of each signal. A maximum value detection circuit 120 provides an output of a selection signal that selects the reception data corresponding to the reception signal whose strength is highest among the 1st to 3rd corrected signals denoting the strength. A data selection circuit 130 selects any of the 1st to 3rd reception data based on the selection signal outputted from the maximum value detection circuit 120 and provides an output of the selected data as demodulation data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a diversity receiver in the field of wireless communication.

[0002]

2. Description of the Related Art In the field of wireless communication, particularly in the field of mobile communication, diversity reception is often applied in order to reduce the influence of fading. For a conventional diversity receiver, see, for example, the document “Effect of Selective Diversity Reception after Detection in QDPSK Mobile Radio Transmission” (Ono and Adachi, IEICE Transactions, B-II, Vol.
J73-B-II, No. 11, pp. 651-657, November 1990). Hereinafter, the related art will be described with reference to the drawings.

FIG. 3 is a configuration diagram showing a configuration of a conventional diversity receiver for performing diversity reception of three branches. In FIG. 3, reference numerals 101, 102, and 103 denote first to third detection circuits, 111, 112, 113 is a first to third signal strength detection circuit, 120 is a maximum value detection circuit, 1
Reference numeral 30 denotes a data selection circuit.

Next, the operation will be described. In FIG. 3, first to third reception signals received by different antennas (not shown) are respectively detected by corresponding first to third detection circuits 101, 102, and 103, and the detection results are obtained. Certain first to third received data are output.

At the same time, the first to third received signals are first to third signal strength detection circuits 111, 112, 11
3, and the respective signal intensities are detected. The first to third signal strengths output from the first to third signal strength detection circuits 111, 112, 113 are input to the maximum value detection circuit 120, respectively.

[0006] The maximum value detection circuit 120 receives the input first signal.
Or the third signal strength is detected, and the number of the received signal having the highest value is output. The data selection circuit 130 includes the first to third detection circuits 10
The first to third reception data output from the first, second, and third input data are input, and the reception signal having the highest signal strength is determined based on the number of the reception signal having the highest signal strength output from the maximum value detection circuit 120. The detected received data is selected and output as demodulated data.

As described above, in the conventional diversity receiver, the result of detection of a received signal having the maximum signal strength is always used as demodulated data, so that the effect of signal strength reduction due to fading can be reduced.

[0008]

As described above, the conventional diversity receiver simply selects and outputs the reception data having the maximum signal strength. Therefore, when a strong interference signal is received, the normal reception data is transmitted. There was a problem that can not be obtained. That is, in FIG. 3, for example, if the first received signal is an interference signal and the signal strength is larger than the second and third received signals, the second and third received signals are assumed to be the desired signals. Even if it is a signal, what is obtained as demodulated data is data obtained by detecting the first received signal (that is, an interference signal) having the highest signal strength, and it is impossible to obtain normal received data. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a diversity receiver capable of obtaining normal received data even when a strong interference signal is received. With the goal.

[0010]

SUMMARY OF THE INVENTION A diversity receiver according to the present invention detects a plurality of received signals and outputs received data, and a signal for detecting the signal strength of each of the plurality of received signals. Intensity detection means, interference signal detection means for determining whether the plurality of reception signals are interference signals from the plurality of reception data output from the detection means and outputting an interference detection signal, and detecting the interference signal Signal strength correcting means for correcting the signal strengths of the plurality of received signals output from the signal strength detecting means in response to the interference detection signal output from the means, and the corrected signal strength output from the signal strength correcting means. The maximum value of the signal strength
Maximum value detection means for outputting a selection signal for selecting a reception signal corresponding to the corrected signal strength having the maximum value, and a plurality of detection signals detected by the selection signal output from the maximum value detection means Data selecting means for selecting one of the received data and outputting it as demodulated data.

The interference signal detecting means includes a data comparing means for comparing the plurality of received data, a statistical processing means for statistically processing an output of the data comparing means, and an addition for adding an output of the statistical processing means. Means for determining whether or not each of the plurality of reception signals is an interference signal based on a value of an output of the adding means.

Further, the data comparison means is configured to take an exclusive OR of two different received data of the plurality of received data.

Further, the statistical processing means is constituted by a cumulative addition circuit for adding the output of the data comparing means from the current time to N (N is an integer of 1 or more) bits before.

[0014] The determining means may comprise a comparator for comparing the value of the output of the adding means with a predetermined threshold value.

Further, the signal strength correcting means is constituted by a multiplier for multiplying the interference detection signal and the reception strength.

The multiplier is constituted by an AND circuit.

Further, the signal strength correcting means is constituted by a selection circuit for outputting the reception strength or zero based on the value of the interference detection signal.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing a configuration of a 3-branch diversity receiver.
Denotes an interference detection circuit, and 201, 202, and 203 denote first to third multipliers as signal strength correcting means. The same or corresponding parts as in FIG. 3 showing the conventional apparatus are denoted by the same reference numerals, and description thereof will be omitted.

Next, the operation will be described. In FIG. 1, first to third reception signals received by different antennas (not shown) are detected by first to third detection circuits 101, 102, and 103, respectively, and a first detection result, which is a detection result, is obtained. Or third received data is output.

At the same time, the first to third received signals are first to third signal strength detection circuits 111, 112, 11
3, and the respective signal intensities are detected and output as first to third signal intensities.

First to third detection circuits 101, 10
The first to third received data output from 2, 103 are input to the interference detection circuit 200. Hereinafter, the configuration and operation of the interference detection circuit 200 will be described with reference to the drawings.

FIG. 2 is a diagram showing the configuration of the interference detection circuit 200. In the figure, reference numerals 211, 212, and 213 denote first to third exclusive OR elements as data comparing means.
Reference numerals 21, 222, and 223 denote first to third accumulators as statistical processing means, 231, 232, and 233 denote first to third adders, and 241, 242, and 243 denote first to third judging means. It is a comparator.

Next, the operation will be described. In FIG. 2, a first exclusive OR element 211 performs an exclusive OR operation of the first received data and the second received data. Similarly, the second exclusive OR element 212 performs an exclusive OR operation on the first received data and the third received data, and the third exclusive OR element 213 performs an exclusive OR operation on the second received data and the third received data. The exclusive OR operation of the received data is performed.

Here, if the first to third received signals are all desired signals, the first to third received data are all the same (here, the effects of noise, fading, etc. are considered. Make it not exist). Therefore, in this case, the first to third exclusive OR elements 211, 21
The outputs of 2, 213 are all "0".

Next, for example, consider a case where the first received signal is an interference signal. Generally, it is considered that the data of the desired signal and the data of the interference signal are uncorrelated, and the probability that the data of the two signals match is 50%. Therefore,
When the first received signal is an interference signal and the other received signal is a desired signal, a first exclusive logical operation of performing an exclusive OR operation of the first received data and the second received data From the OR element 211 and the second exclusive OR element 212 that performs an exclusive OR operation of the first received data and the third received data, “0” and “1” are randomly generated with a probability of 50%. Is output. On the other hand, since both the second received signal and the third received signal are desired signals, the third exclusive OR element 213 that performs the exclusive OR operation of the second received data and the third received data Are all "0".

The output of the first exclusive OR element 211 is
The signal is input to the first accumulative addition circuit 221, and is added with the past N (N is an integer of 1 or more) bits from the current time and output. Similarly, the output of the second exclusive OR element 212 is output by the second cumulative addition circuit 222, and the output of the third exclusive OR element 213 is output by the third cumulative addition circuit 223 from the present time to the past N The bits are added and output.

Here, the case where the received signal 1 is an interference signal will be considered again. In this case, as described above, the first exclusive-OR element 211 and the second exclusive-OR element 21
From "2", "0" and "1" are output at random with a probability of 50%, and the outputs of the third exclusive OR elements 213 all become "0". Therefore, the expected value of the output of the first cumulative addition circuit 221 and the second cumulative addition circuit 222 is N / 2, and the output of the third cumulative addition circuit 223 is “0”.

Similarly, the case where the second received signal is an interference signal and the case where the third received signal is an interference signal are summarized, and the first to third cumulative addition circuits 221 and 2
The expected values of the outputs 22 and 223 are as shown in Table 1. According to this table, the first to third accumulative adders 221 and 22
It can be seen that the output values of 2, 223 serve as evaluation criteria for determining whether the first to third received signals are interference signals.

[0029]

[Table 1]

Next, the output of the first cumulative addition circuit 221 and the output of the second cumulative addition circuit 222 are
1 is added and output. Similarly, the output of the first cumulative addition circuit 221 and the output of the third cumulative addition circuit 223 are output by the second adder 231 to the second cumulative addition circuit 22.
2 and the output of the third accumulator 223 are added and output by the third adder 233, respectively. Here, considering again the case where any one of the first to third received signals is an interference signal, the first to third adders 23
The expected values of the outputs 1, 2, 233 are as shown in Table 2 below.

[0031]

[Table 2]

That is, if the k-th (k {1, 2, 3}) received signal is an interference signal, the expected value of the output of the k-th adder is "N", and the output of the other adders is "N". The expected value of the output is “N / 2”. Using this property, the first to third
The comparators 241, 242, and 243 each determine whether the first to third received signals are interference signals.

That is, the first comparator 241 compares the output of the first adder 231 with a threshold value α having an appropriate value equal to or more than “N / 2” and less than “N”. Adder 231
Is less than the threshold value α, the first received signal is determined not to be an interference signal, and “1” is output as the first interference detection signal. On the other hand, if the output of the first adder 241 is equal to or greater than the threshold α, it is determined that the first received signal is an interference signal, and “0” is determined as the first interference detection signal.
Is output.

Similarly, the second and third comparators 242,
243 are second and third adders 232, 2
33 is compared with a threshold value α, and “1” or “0” is output as the second and third interference detection signals according to the result. The first to third interference detection signals generated by the above signal processing are output as outputs of the interference detection circuit 200.

Hereinafter, the operation will be described again with reference to FIG. In FIG. 1, first to third interference detection signals output from an interference detection circuit 200 are input to first to third multipliers 201, 202, and 203, respectively. On the other hand, the first to third multipliers 201, 202, and 203 respectively include first to third signal strength detection circuits 111,
The first to third signal intensities output from 112 and 113 are input, and multiplication with the first to third interference detection signals is performed, respectively. The results of these multiplications are output from the first to third multipliers 201, 202, 203, respectively, as first to third modified signal strengths, respectively.

As described above, the first to third interference detection signals are "0" when the first to third received signals are determined to be interference signals, respectively, and are not interference signals. If it is determined, it becomes "1". Therefore, the first to third modified signal strengths output from the first to third multipliers 201, 202, 203 respectively indicate that the first to third received signals are interference signals. Is determined to be "0", and when it is determined that the signal is not an interference signal, the first to third signals which are the outputs of the first to third signal strength detection circuits 111, 112 and 113, respectively. The signal strength is output as it is.

The first to third corrected signal intensities generated by the above-described signal processing are respectively applied to the maximum value detection circuit 12.
Input to 0. The maximum value detection circuit 120 detects a maximum value among the input first to third corrected signal intensities and selects a reception data corresponding to the reception signal having the maximum value. Is output.

As described above, when the interference detection circuit 200 determines that the k-th (k {1, 2, 3}) received signal is an interference signal, the k-th corrected signal strength Becomes “0”. Accordingly, the maximum value detection circuit 120 outputs a selection signal for selecting reception data detected from the reception signal having the highest signal strength among the reception signals determined not to be an interference signal by the interference detection circuit 200. Become. In other words, the selection signal cannot be output from the maximum value detection circuit 120 for the reception signal determined to be the interference signal by the interference detection circuit 200.

Then, according to the selection signal, one of the received data of each branch input to the data selection circuit 130 is selected and output as demodulated data. As described above, since the signal for selecting the reception data detected from the reception signal determined to be the interference signal by the interference detection circuit 200 is not output from the maximum value detection circuit 120, the present embodiment According to the embodiment, it is possible to obtain normal received data even when a strong interference signal is received.

Embodiment 2 Note that the first to third interference detection signals, which are one input of the first to third multipliers 201, 202, 203, are “0” as described above,
Since only two values of "1" are taken, when the first to third multipliers 201, 202, and 203 are configured by digital circuits, they may be configured by AND circuits.

Embodiment 3 In addition, the first to third multipliers 201, 202, and 203 select and correct the first to third signal strengths when the first to third interference detection signals are "1", respectively. Output as signal strength,
When the first to third interference detection signals are "0", the first to third selection circuits for selecting and outputting "0" as the corrected signal strength may be used. It has the same effect as.

Embodiment 4 Further, in the above-described embodiment, the case where the number of diversity branches is 3 has been described, but the number of diversity branches may be any integer of 3 or more (eg, 4, 8 or the like), and is the same as in the above-described embodiment. The same effect can be obtained by the signal processing described above.

[0043]

As described above, according to the present invention, interference detection means for determining whether or not an interference signal is present based on received data detected by detecting each received signal, and Correction means for correcting each received signal strength by detecting the maximum value of the corrected signal strength, and selecting the detected received data from the received signal indicating the maximum value, so that a strong interference signal is generated. There is an effect that a diversity receiver capable of obtaining normal received data even when received is obtained.

Further, the interference signal detecting means includes a data comparing means for comparing the plurality of received data, a statistical processing means for statistically processing an output of the data comparing means, and an addition for adding an output of the statistical processing means. Means, based on the value of the output of the adding means, the determination means for outputting the interference detection signal indicating whether or not each of the plurality of received signals is an interference signal, so that it is configured to have a simple There is an effect that an interference signal can be detected by the circuit configuration.

Further, since the data comparing means is constituted by an exclusive OR element, there is an effect that the circuit configuration is simplified.

Further, the statistical processing means is constituted by a cumulative addition circuit for adding the output of the data comparison means from the present time to N (N is an integer of 1 or more) bits before, so that the circuit configuration is simple. There is an effect that is made.

Further, since the determination means is constituted by a comparator for comparing the value of the output of the addition means with a predetermined threshold value, there is an effect that the circuit configuration is simplified.

Further, the signal strength correcting means is constituted by a multiplier for multiplying the interference detection signal and the reception strength, so that there is an effect that the circuit configuration is simplified.

Further, since the multiplier is constituted by an AND circuit, there is an effect that the circuit configuration is simplified.

Further, the signal strength correcting means is constituted by a selection circuit for outputting the reception strength or zero based on the value of the interference detection signal, so that the circuit configuration is simplified. .

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a configuration of a diversity receiver according to an embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating a configuration of an interference detection circuit 200 in FIG. 1;

FIG. 3 is a configuration diagram showing a configuration of a conventional diversity receiver.

[Explanation of symbols]

 101, 102, 103 Detection circuits 111, 112, 113 Intensity detection circuits 120 Maximum value detection circuits 130 Data selection circuits 200 Interference detection circuits 201, 202, 203 Multipliers 211, 212, 213 Exclusive OR elements 221, 222, 223 Cumulative addition circuits 231, 232, 233 Adders 241, 242, 243 Comparators.

Claims (8)

[Claims] 1. A detecting means for detecting each of a plurality of received signals and outputting received data; a signal strength detecting means for detecting a signal strength of each of the plurality of received signals; and a signal output from the detecting means. Interference detection means for determining whether the plurality of reception signals are interference signals from a plurality of reception data and outputting an interference detection signal; and the signal strength according to the interference detection signal output from the interference detection means Signal strength correcting means for correcting the signal strengths of the plurality of received signals output from the detecting means; detecting a maximum value of the corrected signal strength output from the signal strength correcting means, and taking the maximum value Maximum value detection means for outputting a selection signal for selecting a reception signal corresponding to the corrected signal strength, and the reception signal is detected by the selection signal output from the maximum value detection means. Selects one of the received data number, the diversity receiver characterized by comprising a data selection means for outputting the demodulated data. 2. The interference signal detecting means includes: a data comparing means for comparing the plurality of received data; a statistical processing means for statistically processing an output of the data comparing means; and an addition for adding an output of the statistical processing means. And means for outputting the interference detection signal indicating whether or not each of the plurality of received signals is an interference signal based on a value of an output of the adding means. 2. The diversity receiver according to claim 1, wherein: 3. The diversity receiver according to claim 2, wherein said data comparing means is configured to take an exclusive OR of two different received data of a plurality of received data. 4. The statistical processing means according to claim 1, wherein said statistical processing means is constituted by a cumulative addition circuit for adding an output of said data comparing means from a current time to N (N is an integer of 1 or more) bits before. 3. The diversity receiver according to claim 2. 5. The diversity receiver according to claim 2, wherein said judging means comprises a comparator for comparing an output value of said adding means with a predetermined threshold value. . 6. The diversity receiver according to claim 1, wherein said signal strength correcting means comprises a multiplier for multiplying said interference detection signal and said reception strength. 7. The diversity receiver according to claim 6, wherein said multiplier is configured by an AND circuit. 8. The diversity receiver according to claim 1, wherein said signal strength correction means comprises a selection circuit for outputting said reception strength or zero based on a value of said interference detection signal.