JPH1023347A - Gradation correction device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To operate optimal gradation correction to each picture in a small circuit scale even when plural pictures are displayed on a display screen. SOLUTION: A luminance signal is converted into a digital signal by an A/D converter 1 for each field, and inputted through a histogram i/f circuit 3 to a histogram 2. The histogram 2 stores the degree of each luminance as data by using a luminance value as an address. A CPU 4 prepares the cumulative histogram of luminance based on the histogram data, and fetches it through a cumulative memory i/f circuit 9 in a cumulative histogram memory 8. The CPU 4 prepares correction data by referring to the result of the cumulative histogram for each screen so that the cumulative curve can be a straight line, and stores it in lookup table memories 11a and 11b. Thus, gradation correction can be operated by this table.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gradation correcting device for correcting the gradation of each image when displaying a multi-screen image on a television receiver or an image display device.

[0002]

2. Description of the Related Art In recent years, color television receivers have been increasing in size and image quality. In order to make an image look sharper, a tone correction device that enlarges a dynamic range of a video on a CRT by correcting a gray level by passing a video (image) signal through a non-linear amplifier has been emphasized. In the field of TV, the number of screens has been increased, and TVs capable of displaying different programs on two screens have become mainstream. At that time, a tone correction device capable of performing independent tone correction on two screens has also been devised.

Here, a conventional tone correction device will be described with reference to the drawings. FIG. 7 is a block diagram showing a configuration example of a conventional tone correction device. In FIG. 1, an A / D converter 1 is a converter for A / D converting a luminance component (hereinafter, referred to as a luminance signal) of an input image signal. The digitally converted luminance signal is supplied to the synchronization processing circuit 18, the histogram interface circuit (histogram i / f circuit) 3a, the histogram i / f circuit 3b, the first selector 12a, and the second
Is input to the selector 12b. Here, the luminance signal is a signal for simultaneously displaying a plurality of programs.

Assuming that a plurality of images to be displayed simultaneously are a first image (A) and a second image (B), a histogram memory 2a records a luminance histogram of a luminance signal a1 of the first image in at least one field. Memory.
The histogram i / f circuit 3a has a histogram memory 2a.
Is an interface circuit that controls writing and reading of data. Similarly, the histogram memory 2b is a memory for recording a luminance histogram of the luminance signal a2 of the second image in at least one field. Histogram i /
The f circuit 3b is an interface circuit that controls writing and reading of the histogram memory 2b.

The CPU 4 includes histogram memories 2a, 2
An operation control unit that performs an operation for calculating a cumulative histogram from the luminance histogram data b and further calculating a lookup table. Program ROM 5
Is a ROM for storing an operation program of the CPU 4. The first register RAM 6 is a memory for storing parameters used for calculating data stored in the cumulative histogram memory 2a and the look-up table memory 11a. Similarly, the second register RAM 7 is a memory for storing parameters used for calculating data stored in the cumulative histogram memory 2b and the look-up table memory 11b.

[0006] The cumulative histogram memory 8a is a memory for storing the cumulative calculation result of the histogram distribution stored in the histogram memory 2a. The cumulative histogram memory 8b is a memory for storing the cumulative calculation result of the histogram distribution stored in the histogram memory 2b. Here, the luminance level is associated with the address of the memory, and the frequency of the luminance level is associated with the data of the memory. The cumulative memory i / f circuit 9a includes the cumulative histogram memory 8
The interface circuit controls writing and reading of a, and accumulates processing data of the histogram memory 2a under the control of the CPU 4. Similarly, cumulative memory i / f
The circuit 9b is an interface circuit that controls writing and reading of the cumulative histogram memory 8b and accumulates processing data of the histogram memory 2b under the control of the CPU 4. When calculating the cumulative histogram, the CPU 4 calculates a luminance level at which the accumulation starts and a luminance level at which the accumulation stops, and controls the accumulation memory i / f circuits 9a and 9b.

The look-up table memory (LUT memory) 11a is a memory for storing luminance correction data calculated by the CPU 4 for the luminance signal a1. Similarly, the look-up table memory 11b is a memory for storing luminance correction data calculated by the CPU 4 for the luminance signal a2. Here, the luminance level is made to correspond to the address of the LUT memory, and the correction data is made to correspond to the data.

The LUT memory i / f circuit 10a is an interface circuit for controlling writing and reading of the look-up table memory 11a. Similarly, the LUT memory i / f circuit 10b is a lookup table memory 1
1b is an interface circuit for controlling writing and reading. These LUT memory i / f circuits are:
It is controlled by the CPU 4.

The synchronization processing circuit 18 includes luminance signals a1, a2
This circuit recognizes the phase information including the vertical and horizontal display start points and controls the timing of each memory circuit and i / f circuit. The above histogram i / f circuit, cumulative memory i / f circuit, LUT memory i / f circuit, program R
The OM 5, the register RAM 6, and the RAM 7 are connected to the CPU 4 via a data bus and an address bus.

The first selector 12a has an LUT memory i
A selector which selects the output of the / f circuit 10a and the output of the A / D converter 1 and gives the selection result as an address of the lookup table 11a. At the time of a write operation of the look-up table memory 11a, the output of the LUT memory i / f circuit 10a is selected, and at the time of a read operation, a digital luminance signal output from the A / D converter 1 is selected. input.

The second selector 12b is connected to the LUT memory i /
This is a selector that selects the output of the f-circuit 10b and the output of the A / D converter 1 and gives the selection result as an address of the lookup table 11b. The look-up table memory 11b selects the output of the LUT memory i / f circuit 10b at the time of the write operation, and selects the digital luminance signal which is the output of the A / D converter 1 at the time of the read operation. input.

The third selector 16 is a selector for selecting an output signal of the lookup table memory 11a and an output signal of the lookup table memory 11b. D /
The A converter 17 is a converter that converts a digital signal output from the third selector 16 into an analog signal.

The operation of the conventional gradation correction circuit thus configured will be described. Assuming that the luminance signal input to the A / D converter 1 is a, the A / D converter 1 generates a converted luminance signal b obtained by digitally converting the luminance signal a. When there are a plurality of types of screens (for example, two screens), luminance signals a1 and a2 of different screens are converted into digital converted luminance signals b1 and b2, respectively. Histogram memory i
Each time the converted luminance signals b1 and b2 are accessed as addresses of the histogram memories 2a and 2b, the / f circuits 3a and 3b add one to the data at the address and return the data to the histogram memories 2a and 2b. Create frequency distribution data. Histogram memory 2
A restriction is made so that the frequency of each address a and 2b does not exceed a certain level. This operation is performed for one vertical scanning period (1
(Period of a field) to obtain luminance signals a1, a
2 is detected.

The contents of the histogram memories 2a and 2b are cleared every one vertical scanning period or an integral multiple thereof, and all data are initialized to zero. When two types of images exist in one vertical scanning period, a histogram memory 2a and a histogram memory 2b are assigned to each image. And the humangram memory i / f circuit 3
a is turned on only when the luminance signal b1 of the screen to which the histogram memory 2a is assigned, and the histogram memory i / f circuit 3b is turned on only when the luminance signal b2 of the screen to which the histogram 2b is assigned. That is, on / off control of the data addition of the histogram memory 2 is performed at the time of switching between a plurality of types of images.

Here, the operation of the CPU 4 with respect to the screen luminance signal b1 assigned to the histogram memory 2a,
The processing contents of the lookup table memory 11a will be described.

The CPU 4 reads the data from the histogram memory 2a, detects the minimum luminance level YMIN of the screen luminance signal b1 assigned to the histogram memory 2a and the total frequency TPX written in the histogram, and calculates the variance DST. Further, an average value APL of the luminance levels at all sample points is calculated. Using these four control parameters (YMIN, TPX, DST, APL), three values of a base value BSE (= initial setting value of the added value), an accumulated start point RST, and an accumulated end point RED are obtained.
Calculate two control parameters.

Next, data is read out again from the histogram memory 2a, and a limit value LIM and a fixed addition value OFT are calculated based on the control parameters already calculated, and the result is used as corrected histogram data c.

FIGS. 8 and 9 are explanatory diagrams showing the data processing method at each stage of creating data of a luminance histogram from an input luminance signal a, obtaining an accumulated histogram, and generating corrected histogram data from the data. FIG. 8A is a graph showing the data held in the histogram memory 2 and measuring the frequency distribution of the luminance value at each luminance level with respect to the luminance signal b1 of the sampled specific field. FIG. 8B is an explanatory diagram of a case where a frequency value at a certain luminance level exceeds a maximum value that can be measured, and a limit value is provided for the frequency value. And FIG. 8 (c)
FIG. 7 is an explanatory diagram showing an example of a setting state of a base value BSE, an accumulated start point RST, and an accumulated end point RED.

As shown in FIG. 9D, the graph obtained by cumulative addition becomes larger as indicated by a straight line L2 as the base value BSE to be added becomes larger, and the graph obtained by cumulative addition becomes smaller as the base value BSE to be added becomes smaller. It can be seen that the curve is curved as indicated by L1, and the curve is flattened at the low and high luminance levels.

The cumulative memory i / f circuit 9a shown in FIG.
Based on the cumulative start point, RST, and cumulative end point RED given by U4, the cumulative histogram data d of the histogram data c within the range is calculated, and the result is stored in the cumulative histogram memory 8a. This state is shown in FIGS. 8C and 9D.

Next, the CPU 4 reads data from the cumulative histogram memory 8a, and obtains a normalization coefficient such that the maximum value of the cumulative histogram data becomes the maximum luminance level h. Based on this normalization coefficient, normalization processing is performed on each data g of the cumulative histogram, and the result i is stored in the look-up table memory 11a. At this time, by controlling the maximum luminance level h, operations such as automatic contrast control (ACL) and automatic bright control (ABL) can be performed. This situation is shown in FIG.

A signal having a wide luminance dynamic range has a cumulative histogram that is close to linear as indicated by a straight line L2 in FIG. 9D. Therefore, a correction operation for bringing the cumulative histogram of the input image luminance signal from the state of the curve L1 to the state of the straight line L2 is performed using the look-up table memory 11a. The data j is read from the look-up table memory 11a using the luminance signal b1 on the screen assigned to the histogram memory 2a as an address. Then, the data j is output to the third selector 16 as the first corrected luminance signal k1. FIG. 9F shows a histogram of the corrected luminance signal.

The above-described data creation operation in the CPU 4 and the look-up table memory 11 is similarly performed for the other luminance signal a2. That is, the histogram memory 2
The second correction output signal k2 is also used for the luminance signal b2 assigned to the b using the cumulative histogram memory 8b, the cumulative memory i / f circuit 9b, the look-up table memory 11b, and the LUT memory i / f circuit 10b. Can be created.

Next, the third selector 16 selects the first correction output signal k1 for the screen area assigned to the histogram memory 2a, and selects the first correction output signal k1 for the screen area assigned to the histogram memory 2b. 2 is selected. Then, the D / A converter 17 converts the output signal k from the third selector 16 into an analog signal 1 and outputs it. The synchronization processing circuit 18 controls the operation timing of each circuit so that the operation of each unit is performed in the order described above.

In the above-described gradation correcting apparatus, when displaying a plurality of images on the display screen, an independent histogram can be obtained for each luminance signal, and the obtained gradation correction table (look-up) can be obtained. Uptable) can also be accurate.

[0026]

However, in the above-described conventional configuration, in order to accurately correct a plurality of images on a display screen, a circuit amount and a memory amount corresponding to the number of images are required. Had.

The present invention has been made in view of such a conventional problem, and when displaying a multi-screen image on a television receiver or an image display device, a smaller number of histogram i / f circuits and An object of the present invention is to realize a gradation correction device that corrects the gradation of each image using a histogram memory.

[0028]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the invention according to claim 1 of the present application provides a gradation correction for correcting the gradation of each image when a plurality of images are simultaneously displayed on one screen. A histogram memory for storing a luminance frequency distribution of an image at a specific cycle T for a luminance signal of each input image, and writing and reading control of data of the luminance frequency distribution with respect to the histogram memory. The histogram interface circuit and the data of the luminance frequency distribution held in the histogram memory are taken out through the histogram interface circuit to calculate the cumulative luminance frequency distribution, and the obtained cumulative luminance frequency distribution has a desired shape. Setting a control parameter, correcting the luminance frequency distribution using the control parameter, A calculation control unit that creates a correction table for correcting the level of the input luminance signal using,
A plurality of look-up table memories that hold correction tables for a plurality of images created by the arithmetic control unit for at least a specific period of time T; An image switching selector for inputting a signal and outputting a corrected luminance signal of each image using the correction table of the look-up table memory.

Further, in the invention according to claim 2 of the present application, the histogram memory interface circuit fetches a luminance signal by sequentially switching image signals for a plurality of images for each field, and displays a plurality of images displayed on the same screen. It is characterized in that the luminance frequency distribution of one image is controlled to be extracted from among the images and is provided to the histogram memory.

According to the invention described in claim 3 of the present application, when one or more images are simultaneously displayed in the same image display area,
A tone correction device for correcting the tone of each image, wherein when converting the luminance value of each image into an address signal, the address width is reduced according to each image and a predetermined offset value is added. An address signal generating unit for allocating recording areas of the memory so as not to overlap with each other, and inputting a luminance value of each image based on the address converted by the address signal generating unit address. A histogram memory for storing frequency distributions collectively; a histogram interface circuit for controlling writing and reading of luminance frequency distribution data to and from the histogram memory; and one or more luminance frequency distribution data held in the histogram memory From the histogram interface circuit to obtain the respective cumulative luminance frequency distributions. Along with the calculation, control parameters are set so that each of the obtained cumulative luminance frequency distributions has a desired shape, each luminance frequency distribution is corrected using the control parameters, and each image is corrected using the corrected luminance frequency distribution. An arithmetic control unit that creates a correction table that corrects the level of the luminance signal of at least one image, and a correction table for one or more images created by the arithmetic control unit is held for at least a specific period T, and the correction table is used A look-up table memory for outputting a corrected luminance signal of each image.

Further, in the invention according to claim 4 of the present application, the address signal generating section includes a shifter for reducing a bit width of a luminance level of an image signal, and a shifter for simultaneously displaying one or more images. And an adder for giving an offset to the output data of the shifter.

Further, in the invention described in claim 5 of the present application, the shifter and the adder turn on / off gradation correction of a plurality of images.
It is characterized in that it is controlled to be activated or deactivated by an off signal.

According to the first and second aspects, the frequency distribution of the amplitude level of the luminance of the input video signal is stored in the histogram memory. When displaying a plurality of images on the same screen, the histogram memory interface circuit controls so as to extract a frequency distribution of a region corresponding to one video signal from the plurality of images. Then, the histogram memory interface switches the image extraction area for each field. Also, when displaying a plurality of images on the display screen, the gradation correction processing for the plurality of screens can be performed without increasing the circuit scale of the histogram memory and the histogram memory interface circuit by switching the data storage in the histogram memory for each field. It can be carried out.

According to the third to fifth aspects, the frequency distribution of the amplitude level of the luminance of the input video signal is stored in the histogram memory. At this time, when converting the luminance value of each image into an address signal, the address signal generation unit reduces the address width according to each image and adds a predetermined offset value so that the recording area of the memory does not overlap. assign. At this time, the shifter reduces the bit width of the luminance level data of the video signal, and the adder gives an offset according to the display area of the screen. In this way, even when a plurality of images are displayed on the display screen, since the address width of each image is small, tone correction of the plurality of images can be performed simultaneously using one histogram memory or look-up table memory. Further, it is also possible to switch to a gradation correction device which fully uses a histogram memory or a lookup table memory for one image in response to a gradation correction off signal for a plurality of screens.

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) A gradation correcting apparatus according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of a tone correction device according to the present embodiment.
The same parts as those in the conventional example will be described with the same reference numerals. In the figure, an A / D converter 1 is a converter for A / D converting an input image signal (luminance signal). The histogram memory 2 is a histogram memory for storing a histogram of the luminance level of the luminance signal a. Generally, the luminance level of an input signal is made to correspond to an address of a memory, and 1
The frequency of each luminance level in the frame is made to correspond. This is an interface circuit that controls writing and reading of the histogram i / f circuit 3 and the histogram memory 2.
As described above, the present embodiment is configured so that a histogram of luminance is processed by a set of the histogram memory 2 and the histogram i / f circuit 3 for a plurality of images.

FIG. 2 is a block diagram specifically showing the configuration of the histogram memory i / f circuit 3. In the figure, the selector 31 sets the address of the histogram memory 2 to A
A selector for switching to the data bus side of the / D converter 1 or the CPU 4. The selector 32 is a selector for switching data input to the histogram memory 2. Adder 3
An adder 3 adds 1 to the data output from the histogram memory 2. The limiter circuit 34 is a limiter circuit provided to prevent the result of addition from overflowing from a predetermined value when 1 is added to the data output from the histogram memory 2. This is a circuit for setting the limit value LIM described with reference to FIG.

The bus selector 35 is a selector for managing data transfer with a bidirectional data bus connected to another block, and is constituted by a tri-state buffer. The selector 36 controls a screen switching pulse sent from the bidirectional data bus and a field counter 15 described later.
Is a selector for selecting whether or not to provide the output of the adder 33 to the histogram memory 2 based on the field identification signal sent from the

When data is written to the histogram memory 2 by the histogram memory i / f circuit 3 of FIG. 1, the luminance signal output from the A / D converter 1 is input to the address of the histogram memory 2 and is adjusted according to the luminance level. The distribution frequency is added as data via the adder 33. The process of reading the histogram distribution extracted in the histogram memory 2 is performed via the bus selector 35.

FIG. 4 shows a configuration of a sampling window for extracting a histogram in an image display area of an image display device or a TV receiver. FIG. 4A illustrates a case where one image A is displayed in the image display area D, and FIG. 4B illustrates a case where the image A and the image B are displayed in the image display area D.

In FIG. 1, a CPU 4 is an arithmetic control unit that calculates an accumulated histogram from the data in the histogram memory 2 and further performs calculations for calculating a look-up table. The program ROM 5 is a ROM for storing a calculation program of the CPU 4. Register RAM6
Is the first screen, for example, the sampling window D1 in FIG.
Is a RAM for storing parameters used for calculating data stored in the cumulative histogram memory 8 and the look-up table memory 11a. Register RAM
Reference numeral 7 denotes a second screen, for example, a sampling window D shown in FIG.
2 is a RAM for storing parameters used for calculating data stored in the cumulative histogram memory 8 and the look-up table memory 11b.

The cumulative histogram memory 8 is a memory for storing the cumulative calculation result of the histogram distribution stored in the histogram memory 2. Generally, a luminance level is associated with an address of a memory, and the frequency of each luminance level is associated with the data. The accumulation memory i / f circuit 9 is an interface circuit for controlling writing and reading of the accumulation histogram memory 8, and accumulates processing data of the histogram memory 2 under the control of the CPU 4. Also C
When calculating the cumulative histogram, the PU 4 calculates a luminance level at which the accumulation starts and a luminance level at which the accumulation stops.
It controls the accumulation memory i / f circuit 9.

The look-up table memory 11a stores C
This is a memory for storing correction data of the first screen calculated by the PU4. Look-up table memory 11
b is a memory for storing the correction data of the second screen calculated by the CPU 4. Generally, a luminance level is made to correspond to an address of a memory, and correction data is stored as the data. The LUT memory i / f circuit 10a is an interface circuit that controls writing and reading of the look-up table memory 11a. Similarly, the LUT memory i / f circuit 10b is an interface circuit that controls writing and reading of the look-up table memory 11b.

The first selector 12a has an LUT memory i
/ F circuit 10a and the output of the A / D converter 1 are selected, and the selection result is stored in the look-up table memory 1
This is a selector given as an address of 1a. The first selector 12a selects the output of the LUT memory i / f circuit 10a when the look-up table memory 11a performs a write operation, and selects the digital output which is the output of the A / D converter 1 when the look-up table memory 11a performs a read operation. The luminance signal is selected and the look-up table memory 11a is selected.
Give to the address.

The second selector 12b is connected to the LUT memory i
/ F circuit 10b and the output of the A / D converter 1 are selected, and the selection result is stored in the look-up table memory 1
This is a selector given as an address of 1b. The second selector 12b selects an output of the LUT memory i / f circuit 10b when the look-up table memory 11b performs a write operation, and outputs a digital signal which is an output of the A / D converter 1 when the look-up table memory 11b performs a read operation. The luminance signal is selected and the look-up table memory 11b is selected.
Give to the address.

The third selector 16 is an image switching selector for selecting either the output signal of the lookup table memory 11a or the output signal of the lookup table memory 11b. The D / A converter 17 is a converter that converts a digital luminance signal whose tone has been corrected from the third selector 16 into an analog signal.

Unlike the conventional example, a field counter 15 is provided in this embodiment. The field counter 15 is a circuit that generates a field identification signal based on the synchronization signal output from the synchronization processing circuit 18. The field identification signal is a signal that is repeatedly turned on / off for each field when two screens are simultaneously displayed in the image display area D as shown in FIG. 4B, for example. The synchronization processing circuit 18 is a circuit for recognizing phase information such as the vertical and horizontal display start points of the luminance signal and controlling the timing of each memory and other circuits, as in the conventional example.

The operation of the gradation correction circuit according to the present embodiment having the above-described configuration will be described. In the same manner as in the conventional example, first, an input luminance signal a is input to the A / D converter 1 and converted into a digital luminance signal b. If there are a plurality of types of screens in one frame or one field, for example, two screens, the digitally converted luminance signals are referred to as b1 and b2, respectively. As shown in FIG. 2, the histogram memory i / f circuit 3 uses the field identification signal output from the field counter 15 and the screen switching pulse output from the synchronization processing circuit 19 to change the current screen of the two screens. A luminance signal is selected, and the luminance signal b is supplied to the histogram memory 2.

Assuming that the selected luminance signal among the luminance signals b1 and b2 is b3, the luminance signal b3 is used as an address of the histogram memory 2, and each time the data is accessed, the adder 33 adds 1 to the data at that address. To return to the histogram memory 2. Further, a limit is imposed by the operation of the limiter circuit 34 so that the frequency of each address of the histogram memory 2 does not exceed a certain level. The bit width of the input signal of the adder 33 is, for example, 8 and the frequency data (11
When (111100) is returned from the histogram memory 2, the output of the limiter circuit 34 becomes NAND (11111100) = 1. When this 8-bit expression (00000001) is added to the original data, the output of the adder 36 becomes (11111101), and this value is stored in the histogram memory 2. On the other hand, when the frequency data (11111111) is returned from the histogram memory 2, the output of the limiter circuit 34 becomes NAND (11111111).
= 0 = (00000000). In this case, the frequency of the histogram memory 2 at that luminance level does not increase.

Generally, when all the pixels of the screen are accessed during the period (sample period) during which the luminance histogram is being extracted, the data processing is completed. By performing such an operation for one vertical scanning period, a luminance signal b3 for one screen is obtained.
Can be detected. In this case, the content of the histogram memory 2 is such that after one vertical scanning period,
Alternatively, the data is cleared every period of an integral multiple thereof, and all data is initialized to zero.

Next, the data in the histogram memory 2 is stored in the CP
U4 detects the minimum luminance level YMIN of the luminance signal of the screen allocated to the histogram memory 2 and the total frequency TPX written in the histogram, and calculates the variance DST. Further, the CPU 4 calculates an average value APL of the luminance levels at all the sample points. Depending on the value of the variance DST, gradation correction may not be performed on the input image.

The CPU 4 determines the four control parameters (Y
MIN, TPX, DST, APL) are used to calculate three control parameters: base value BSE, cumulative start point RST, and cumulative end point RED.

Next, data is read from the histogram memory 2 again, and FIG.
A limiter is set as shown in FIG. 8B, and a constant value adding process as shown in FIG. The result thus obtained is used as corrected histogram data c. Here, the larger the base value BSE to be added is, the closer the cumulative added graph is to a straight line, and the smaller the base value BSE to be added is, the more the cumulative added graph becomes a curve and flattened in the low luminance and high luminance portions. .

The accumulative memory i / f circuit 9 is connected to the CP
Based on the cumulative start point RST and the cumulative end point RED given by U4, the cumulative histogram data d of the corrected histogram data c is calculated within the range, and the result is stored in the cumulative histogram memory 8. This situation is again shown by the curve L in FIGS. 8C and 9D.
Indicated by 1.

Next, the CPU 4 reads data from the cumulative histogram memory 8 and obtains a normalization coefficient such that the maximum value of the cumulative histogram data becomes the maximum luminance level h. Then, a normalization process is performed on each data g of the cumulative histogram based on the normalization coefficient. CPU4
The luminance data stored in the histogram memory 2 is the first,
The lookup table memories 11a and 11ba and the LUT memory i /
The f circuits 10a and 10b are selected. Then, the result i of the normalization processing is stored in, for example, the selected look-up table memory 11a.

At this time, by controlling the maximum luminance level h, automatic contrast control (ACL),
An operation like an automatic bright control (ABL) can be performed. This operation is shown in FIG. In the case of a signal having a wide dynamic range, the cumulative histogram becomes like a straight line L2 in FIG. 9D. Therefore, in the luminance signal, a correction operation is performed to bring a cumulative histogram like a curve L1 in FIG. 9D close to a straight line L2.

In the look-up table 11a, the luminance signal b1 on the screen assigned to the histogram memory 2
Is used as an address to read the data j. Thus, a corrected luminance signal (corrected output signal) k1 for the image A in FIG. 4B is output. FIG. 9F shows a histogram of the corrected luminance signal. This FIG. 9 (f) and FIG.
Comparing with (a), it can be seen that the number of pixels at low and high luminance levels increases, and an image with a narrow gradation is converted to an image with a wide gradation.

Next, the third selector 16 compares the first corrected output signal k1 for the first screen area with the second corrected output signal k2 for the second screen area created in the next field cycle. Switching is performed in accordance with each screen area, and a correction output signal k is output. Then, the D / A converter 17 converts the digital correction output signal k from the third selector 16 into an analog signal and outputs the analog signal to the image display unit. The synchronization processing circuit 18 controls the operation timing of each circuit so that the operation of each unit is performed in the order described above.

As described above, if a histogram is created for each field and data is recorded in the lookup table, an image to be processed in the next field is taken in, so that optimum gradation correction can be executed. For example, when processing four screens, four sets of the LUT memory i / f10 and the look-up table memory 11 are required, but the processing can be performed using one set of the histogram i / f circuit 3 and the histogram memory 2.

Successive fields are defined as F1, F2, F3,
Assuming that F4,..., The control in this case is to update the look-up table memory 11a of the first image using the histogram i / f circuit 3 and the histogram memory 2 with the field at F1, and to store the data in this table. The gradation correction of the luminance signal in the fields F2 to F5 is performed using the above. Similarly, in the field F2, the look-up table memory 11b of the second image is updated using the histogram i / f circuit 3 and the histogram memory 2, and using the data of this table, the gradation of the luminance signal in the fields F3 to F6 is used. Make corrections. Further, in field F3, the histogram i / f circuit 3
Then, the look-up table memory 11c of the image C is updated using the histogram memory 2 and the data of this table, and the gradation correction of the luminance signals F4 to F7 is performed in the field using the data of this table.

With this control, the number of histogram memories and cumulative histogram memories corresponding to the number of screens is not required, and the optimum gradation correction can be realized with the histogram memory and cumulative histogram memory for one screen. As long as the screen is cut and the content does not change,
Since the luminance distribution of the screen does not change significantly in several frame units, it can be said that the gradation correction data created once is effective.

(Embodiment 2) Next, a gradation correcting apparatus according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing the configuration of the tone correction apparatus of the present embodiment, and the same parts as those in the conventional example and the first embodiment are described with the same reference numerals.

In this figure, an A / D converter 1 is a converter for A / D converting an input image signal (luminance signal).
The histogram memory 41 is a memory for storing a histogram of the luminance level of the digitally converted luminance signal.
The memory size is the same as that of the first embodiment.
Generally, the luminance level of the input signal is made to correspond to the address of the memory, and the frequency of the luminance level is included in the data. The histogram i / f circuit 42 is an interface circuit that controls writing and reading of the histogram memory 41.

The shifter 20 is a shifter for reducing the bit width of the luminance signal output from the A / D converter 1. Shifter 2
0 indicates the on / off state of the two-screen gradation correction output from the CPU 4.
This is a circuit for determining whether or not to shift by an off signal (AI-on / off signal). The adder 21 is an adder that adds an offset to the luminance level from the shifter 20.
The first AND circuit 22 includes a shifter 2 in the adder 21.
This is an AND circuit for instructing whether or not to add an offset value to a luminance level from 0. The first AND circuit 22 is supplied with an offset signal output from the register 23 and a screen switching signal output from the synchronization processing circuit 18.

The register 23 is a register for storing an offset value to be added in the adder 21. The second AND circuit 24 is an AND circuit that switches whether or not to add an offset to the luminance signal output from the shifter 20 according to the AI-ON / OFF signal output from the CPU 4. The second AND circuit 24 is supplied with the AI-ON / OFF signal output from the synchronization processing circuit 18 and the output signal of the first AND circuit 22. Shifter 20 and register 2 described above
3. The adder 21 constitutes an address signal generating unit that allocates the recording areas of the memory so as not to overlap by reducing the address width and adding the offset value according to each image.

The AI-ON / OFF of the shifter 20 and the ON / OFF of the second AND circuit 24 are synchronized. CPU
Reference numeral 4 denotes a calculation control unit that calculates a cumulative histogram from the data in the histogram memory 41 and performs a calculation for calculating a look-up table. Program R
OM5 is a ROM for storing the operation program of CPU4.

The register RAM 6 stores an RA for storing parameters used for calculating data to be stored in the cumulative histogram memory 8 and the look-up table memory 43 of the first screen (for example, the sampling window D1 in FIG. 4).
M. The register RAM 7 stores a cumulative histogram memory 8 for the second screen (for example, the sampling window D2 in FIG. 4).
And a RAM for storing parameters used for calculating data to be stored in the look-up table memory 43
It is. The cumulative histogram memory 8 is a memory that stores the result of the cumulative calculation of the luminance calculated from the histogram distribution stored in the histogram memory 41. Generally, a luminance level is made to correspond to an address of a memory, and the frequency of the luminance level is included in the data.

The cumulative memory i / f circuit 9 controls writing and reading of the cumulative histogram memory 8, and
4 is an interface circuit for accumulating the processing data of the histogram memory 41 under the control of 4. At this time CP
U4 calculates a luminance level at which the accumulation starts and a luminance level at which the accumulation stops when calculating the cumulative histogram,
It controls the accumulation memory i / f circuit 9. The lookup table memory 43 is a memory for storing the correction data calculated by the CPU 4. Generally, a luminance level is made to correspond to an address of a memory, and correction data is stored in the data.

The LUT memory i / f circuit 44 is an interface circuit for controlling writing and reading of the look-up table memory 43. Selector 45 is LU
One of the output of the T memory i / f circuit 44 and the output of the adder 21 is selected, and the selection result is stored in the lookup table memory 4.
3 is a selector given as address 3. At the time of the write operation of the look-up table memory 43, the output of the LUT memory i / f circuit 44 is selected. At the time of the read operation of the look-up table memory 43, the luminance signal output from the adder 21 is selected. Enter the address.

The D / A converter 17 is a converter for converting a digital signal in the look-up table memory 43 into an analog signal. The synchronization processing circuit 18 is a circuit that recognizes phase information such as the vertical and horizontal display start points of an image signal and controls the timing of each memory and each circuit.

The operation of the gradation correction circuit of the second embodiment having the above-described configuration will be described. 5 and 6 are explanatory diagrams showing the operation principle of the gradation correction circuit according to the present embodiment.
A histogram or the like is displayed in the same format as in FIGS. 8 and 9. First, the input luminance signal a is supplied to the A / D converter 1 to generate a digitally converted luminance signal b1. A plurality of types of screens (for example, two screens) exist on the same screen.
It is assumed that independent gradation correction is performed on both screens. In this case, the AI-on / off signal, which is a two-screen gradation correction signal, is turned on. Then, the luminance signal b1 is converted by the shifter 20 into a signal having a small bit width. This is Figure 8
The input luminance level shown in FIG. 6A is compressed to, for example, 、, and is converted into an input luminance level as shown in FIG.

The adder 21 in FIG. 3 adds different offset values to the output signal of the shifter 20 to the first and second images. When the luminance signal output from the adder 21 is input, the histogram i / f circuit 42 gives the luminance signal to the histogram memory 41 as an address. At this time, the offset value takes a large value so that addresses of the histogram memory 41 do not overlap between different images.

The histogram i / f circuit 42 uses the output signal of the adder 21 as an address of the histogram memory 41 in the same manner as in the case of FIG. To the histogram memory 41. In addition, the frequency of each address in the histogram memory 41 is restricted so as not to exceed a certain level. In this way, as shown in FIG. 5A, the luminance distributions of the first and second images can be simultaneously obtained on the same coordinates.

Generally, when all pixels on the screen are accessed during the period during which the luminance histogram is being extracted (sample period), the data processing is terminated. By performing such an operation for one vertical scanning period, a luminance histogram of a luminance signal for the first and second images can be detected. The contents of the histogram memory 41 are cleared at regular intervals and all data is initialized to zero. This processing cycle is selected to be one vertical scanning period or an integral multiple thereof.

Next, the data in the histogram memory 41 is stored in C
The PU 4 detects the minimum luminance level YMIN of the luminance signal of the screen allocated to the histogram memory 41 and the total frequency TPX written in the histogram, and detects the variance DS.
Calculate T. Further, the CPU 4 calculates the average value APL of the luminance levels at all sample points for the first and second images.
Is calculated.

The CPU 4 determines the four control parameters (Y
MIN, TPX, DST, APL) are used to calculate three control parameters: base value BSE, cumulative start point RST, and cumulative end point RED.

Next, the data is read out again from the histogram memory 41, a limiter process as shown in FIG. 5 (b) is performed based on the control parameters already calculated, and further a fixed process as shown in FIG. 5 (c). Is added. The result is used as corrected histogram data c. Here, as the base value BSE to be added is larger, the graph of the cumulative addition becomes closer to a straight line, and as the base value BSE to be added is smaller, the graph of the cumulative addition becomes a curve, and both ends are flattened.

The accumulation memory i / f circuit 9 has a CPU
Based on the cumulative start point RST and the cumulative end point RED given from 4, the cumulative histogram data d of the corrected histogram data c is calculated for the range, and the result is stored in the cumulative histogram memory 8.
This situation is shown in FIGS. 5C and 6D.

Next, the CPU 4 reads out the data from the cumulative histogram memory 8 and obtains a normalization coefficient such that the maximum value of the cumulative histogram data becomes the maximum luminance level h. A normalization process is performed on each data g. The relationship between the input luminance level and the output luminance level at this time is as shown in FIG. Then, the result i is stored in the lookup table memory 4
3 is stored. At this time, by controlling the maximum luminance level h, automatic contrast control (ACL),
An operation like an automatic bright control (ABL) can be performed.

For a signal having a wide dynamic range, the cumulative histogram is close to a straight line as shown in FIG. Therefore, a correction operation for making the cumulative histogram of the input image luminance signal close to a straight line is performed using a look-up table.

The look-up table memory 43
The data j is read out using the output signal of the adder 21 as an address to obtain a corrected output signal k. FIG. 6F shows a histogram of the corrected luminance signal. Then, the D / A converter 17 converts the output signal from the look-up table memory 43 into an analog signal and outputs the analog signal to the image display unit.

If there is only one screen in the same display area, or if there are a plurality of types of screens and only one of them is to be subjected to gradation correction, the two-screen gradation correction signal AI-on / off Turn off the signal. In this case, the offset value sent from the register 23 through the AND circuit 24 becomes 0, and the shifter 20 also stops the bit width reduction operation because the AI-on / off signal is off. By this operation, gradation correction can be performed on only one screen. Therefore, the histogram memory 41, the cumulative histogram memory 8, and the look-up table memory 43 can be fully used for an image of one screen. The synchronization processing circuit 18 controls the operation timing of each circuit so that the operation of each unit is performed in the order described above.

By thus reducing the bit width of the input image signal level, it is not necessary to increase the memory capacity of the histogram memory, the cumulative histogram memory, and the look-up table memory even when the number of screens increases. That is, the optimum gradation correction can be realized by the histogram memory, the cumulative histogram memory, and the look-up table memory for one screen. In addition, it is possible to switch to a gradation correction device that fully uses a histogram memory or a look-up table memory by an off signal of gradation correction for a plurality of screens.

[0083]

As described above, according to the present invention, even when a plurality of images are displayed on the display screen, the screen for storing data in the histogram memory is switched for each field, thereby reducing the amount of the histogram memory used. It is possible to realize gradation correction processing corresponding to a plurality of screens without increasing the number of the histogram memory interface circuits and without increasing the number of circuits.

By reducing the bit width of the luminance level, the amount of use of the histogram memory and the look-up table memory is not increased, and the histogram memory interface circuit and the look-up table memory i are not increased.
A gradation correction process corresponding to a plurality of screens can be realized without increasing the circuit amount of the / f circuit.

Further, it is possible to switch to a gradation correction device using a histogram memory or a look-up table memory fully by a gradation correction off signal for a plurality of screens.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a tone correction device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a histogram memory i / f circuit used in the gradation correction device of each embodiment of the present invention.

FIG. 3 is a block diagram illustrating an overall configuration of a tone correction device according to a second embodiment of the present invention.

FIG. 4 is an explanatory diagram of a sampling window for obtaining a histogram.

FIG. 5 is a characteristic diagram (part 1) for explaining the operation of each unit of the gradation correction apparatus according to the second embodiment.

FIG. 6 is a characteristic diagram (part 2) for explaining the operation of each unit of the gradation correction apparatus according to the second embodiment.

FIG. 7 is a block diagram illustrating a configuration example of a conventional tone correction device.

FIG. 8 is a characteristic diagram (part 1) for explaining the operation of each unit of the first embodiment and the conventional tone correction device.

FIG. 9 is a characteristic diagram (part 2) for explaining the operation of each unit of the first embodiment and the conventional gradation correction device.

[Explanation of symbols]

Reference Signs List 1 A / D converter 2, 41 Histogram memory 3, 42 Histogram i / f circuit 4 CPU 5 Program ROM 6, 7 Register RAM 8 Cumulative histogram memory 9 Cumulative memory i / f circuit 11a, 11b, 45 Lookup table memory 10a , 10b, 44 LUT memory i / f circuit 12a, 12b, 16, 31, 32, 36, 45 selector 15 field counter 17 D / A converter 18 synchronization processing circuit 20 shifter 21, 33 adder 22, 24 logical product circuit 23 register 34 limiter 35 bus selector

Claims (5)

[Claims] 1. A gradation correcting apparatus for correcting a gradation of each image when a plurality of images are simultaneously displayed on one screen.
A histogram memory that stores a luminance frequency distribution of an image, a histogram interface circuit that controls writing and reading of data of the luminance frequency distribution with respect to the histogram memory, and the data of the luminance frequency distribution held in the histogram memory. Calculating the cumulative luminance frequency distribution by taking out through the histogram interface circuit, setting a control parameter so that the obtained cumulative luminance frequency distribution has a desired shape, and correcting the luminance frequency distribution using the control parameters, An arithmetic control unit for creating a correction table for correcting the level of the input luminance signal using the corrected luminance frequency distribution; and a correction table for a plurality of images created by the arithmetic control unit is held for at least a specific period T. Multiple look-up table memories and each image An image switching selector that switches the plurality of look-up table memories each time a luminance signal is input, inputs a luminance signal, and outputs a corrected luminance signal of each image using the correction table of the look-up table memory. A gradation correction apparatus characterized by the above-mentioned. 2. The histogram memory interface circuit according to claim 1, wherein said plurality of images are sequentially switched for each field of an image signal to fetch a luminance signal, and a luminance of one image is selected from a plurality of images displayed on the same screen. 2. The gradation correcting device according to claim 1, wherein the frequency distribution is controlled so as to be extracted and applied to the histogram memory. 3. A gradation correction device for correcting the gradation of each image when one or more images are simultaneously displayed in the same image display area, wherein the luminance value of each image is converted into an address signal. An address signal generation unit that reduces an address width according to each image and allocates a recording area of a memory so as not to overlap by adding a predetermined offset value; and an address converted by the address signal generation unit address. A histogram memory for inputting the luminance value of each image based on the above, and collectively storing the luminance frequency distributions of a plurality of images at a specific cycle T; A histogram interface circuit, and one or more luminance frequency distribution data held in the histogram memory. The obtained cumulative luminance frequency distribution is calculated via the stogram interface circuit, and control parameters are set so that the obtained cumulative luminance frequency distribution has a desired shape. An arithmetic control unit that corrects the frequency distribution and creates a correction table for correcting the level of the luminance signal of each image using the corrected luminance frequency distribution; and a correction table for one or more images created by the arithmetic control unit. A look-up table memory that holds at least for a specific period T and outputs a corrected luminance signal of each image using the correction table. 4. An address signal generating section, comprising: a shifter for reducing a bit width of a luminance level of an image signal; and an offset for output data of the shifter according to each image when one or more images are simultaneously displayed. 4. A gradation correcting apparatus according to claim 3, comprising: 5. The gradation correction device according to claim 4, wherein the shifter and the adder are controlled to be activated or deactivated by an on / off signal for gradation correction of a plurality of images.