JPH10232659A - Scan transformation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a scan transformation circuit capable of reducing flicker while suppressing the degradation of a vertical resolution as much as possible. SOLUTION: An arithmetic circuit 14 adds picture data from line memories 11-13 to output the added data to a selector 18. Comparators 15, 16 respectively compares the luminance difference between the picture data of a certain one scanning line from the line memories 11-13 and the picture data of a scanning line being upper of the line and the luminance difference between the picture data of the scanning line and the picture data of a scanning line being lower of the line. The selector 14 selects either the synthetic picture data of the output of the arithmetic circuit 14 or the picture data of the output of the line memory 12 with the signal obtained by ORing output signals of the comparators 15, 16 in an OR circuit 17. A noninterlace/interlace transforming unit 19 transforms the picture data of the noninterlaced system of the output of the selector 18 into the picture signal of an interlaced system to output it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan conversion circuit, and more particularly to a scan conversion circuit for converting a non-interlaced image into an interlaced image.

[0002]

2. Description of the Related Art Conventionally, a non-interlaced image such as a personal computer (abbreviated as a personal computer) has been used.
When displaying on an interlaced display device, a scan conversion circuit is used for the purpose of preventing flicker that occurs when the difference in luminance between the display scanning line and the upper and lower scanning lines is large (Japanese Patent Laid-Open No. 6-83299). No., JP-A-8-14
9499).

FIG. 4 is a block diagram showing an example of a conventional scan conversion circuit having a flicker prevention function. In the figure, a line memory 1R for three red (R) signal components
1, 1R2 and 1R3, three line memories 1G1, 1G2 and 1G3 for green (G) signal components, and three line memories 1B1, 1B2 and 1B3 for blue (B) signal components each correspond to one line. Save the primary color signal data. Calculating means 3R1, 3R2 and 3R3; calculating means 3G1, 3G2 and 3G3; calculating means 3B1, 3B2
And 3B3 are the line memories 1R1, 1R1, respectively.
R2 and 1R3 and line memories 1G1, 1G2 and 1
G3 and the output data of the line memories 1B1, 1B2 and 1B3 are input, multiplied by a constant, and output.

The adding means 4R adds the output R signal component data of the calculating means 3R1, 3R2 and 3R3, the adding means 4G adds the output G signal component data of the calculating means 3G1, 3G2 and 3G3, and adds the Is arithmetic means 3B
The output B signal component data of 1, 3B2 and 3B3 are added. The NTSC converter 5C includes adding means 4R, 4G
, And 4B are output by the interlaced N
Convert to a TSC image signal.

Next, the operation of the conventional scan conversion circuit will be described. Non-interlaced image data sent from the outside is divided into a red (R) signal component, a green (G) signal component, and a blue (B) signal component, and respectively divided into line memories 1R1 to 1R3, 1G1 to 1G3, 1B1. 1
The data is input to B3, and is input and stored for each line.

Here, for example, the R signal will be described. The R signal is input to the line memories 1R1 to 1R3. When image data of a certain scanning line is stored in the line memory 1R2, the R signal is The image data of the scanning line is stored in the line memory 1R1, and the image data of the scanning line one line below is stored in the line memory 1R3.

[0007] The image data stored in the line memories 1R1 to 1R3 is read out, and the operation means 3R1 to 3R3 respectively.
Supplied to R3. The calculation means 3R1 to 3R3 perform weighting calculation. Specifically, the calculation means 3R1 and 3R
In R3, "0.25", and in calculation means 3R2, "0.
The result is supplied to the addition means 4R, and the calculation means 3R1, 3R2 and 3R3.
Add the three values from. Similar calculations are performed for the G signal and the B signal. The output means of the adding means 4R, 4G and 4B is supplied to the NTSC converter 5C, where it is converted into an interlaced image signal conforming to the NTSC system and output. This reduces the difference in luminance between the upper and lower scanning lines.

FIG. 5 is a block diagram showing another example of a conventional scan conversion circuit having a flicker prevention function (Japanese Patent Application Laid-Open No. 58-10794). In FIG. 1, an image memory 101 includes an odd line memory 102 for storing odd line image data and an even line memory 103 for storing even line image data. The odd / even switch 104 switches the output from the odd line memory 102 and the even line memory 103. The conversion correction table 105 performs a correction process on each output signal of the odd line memory 102 and the even line memory 103. The adder circuit 106 supplies a signal obtained by adding the output signals of the odd / even switch 104 and the conversion correction table 105 to the D / A converter 107.

Next, the operation of the scan conversion circuit of FIG. 5 will be described. The content read from the odd line memory 102 and the even line memory 103 of the image memory 101 by the line address
, One is selected by the odd / even switching signal OE and output to the adding circuit 106. At the same time, the image data from the odd line memory 102 and the even line memory 103 are output to the luminance conversion correction table 105. The luminance conversion correction table 105 outputs the odd / even switching signal OE and the table data which is the contents of the table address of the luminance conversion correction table 105 determined by the image data from the odd line memory 102 and the even line memory 103 to the addition circuit 106. Is done.

The adder circuit 106 includes an odd / even switch 104.
The correction value output from the luminance conversion correction table 105 is added to the odd-line or even-line image data output from, and the obtained addition result is output to the D / A converter 107. The D / A converter 107 converts the digital signal, which is the result of the addition, into a video signal, which is an analog signal, and outputs the video signal.

[0011]

However, FIG.
In the conventional scan conversion circuit shown in (1), the scan conversion is performed using a signal obtained by constantly adding the image signal of the line to be converted and the image signal of each of the upper and lower lines at a constant rate. However, there is a problem that the vertical resolution is lowered. Further, in the conventional scan conversion circuit shown in FIG. 5, since the correction data is stored in the conversion correction table 105, the address of the conversion correction table 105 is a read / write signal having a bit length twice the bit length of the luminance data. This is because if the bit length of the data is 8 bits, a ROM of 64 kbytes is required.

The present invention has been made in view of the above points,
An object of the present invention is to provide a scan conversion circuit capable of reducing flicker while minimizing deterioration of vertical resolution.

It is another object of the present invention to provide a scan conversion circuit having a small circuit scale.

[0014]

According to the present invention, in order to achieve the above object, non-interlaced image data is stored at least temporarily for each of a scanning line to be converted and one scanning line above and below it. Means, an arithmetic circuit for weighting and synthesizing a plurality of non-interlaced image data from the storage means to generate synthesized image data, and image data of the scan line to be converted from the storage means and the upper and lower scan lines. Comparing means for determining whether the luminance difference with any of the image data is equal to or more than a predetermined value; and selecting the output combined image data of the arithmetic circuit only when the comparing means determines that the luminance difference is equal to or more than the predetermined value. When it is determined that the image data is smaller than the predetermined value, the selecting means selects the image data of the scanning line to be converted from the storage means, and the image data selected by the selecting means is converted to the desired image. It is obtained by a configuration having a conversion means for converting the image signal Taresu scheme.

In the present invention, the image data of the scanning line to be converted and the image data of the upper and lower lines are not always added at a constant rate as in the prior art. Only when there is a predetermined value or more, scan conversion is performed using combined image data obtained by adding and combining the image data of the scan line to be converted and the image data of the upper and lower lines.

The arithmetic circuit according to the present invention stores the first image data of the scanning line to be converted, which is output from the storage means, into the first image data.
A first multiplying means for multiplying the image data of the two scanning lines above and below the conversion target scanning line outputted from the storage means by a first multiplying means for multiplying the first and second weighting coefficients by a value smaller than the first weighting coefficient. A second multiplying means for multiplying by a weighting coefficient of 2 and an adder for adding the multiplication results of the first and second multiplying means to generate composite image data. According to the present invention, the composite image data can be generated from the multiplication means and the adder without using a table.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a scan conversion circuit according to the present invention. In this embodiment, line memories 11, 12, and 13, an operation circuit 14, comparators 15 and 16, an OR circuit 17, a selector 1
8 and a non-interlace / interlace converter 19. The line memories 11, 12, and 13 store image data for one scanning line, respectively. At this time, the image data stored in the line memories 11 and 13 is the data of the upper and lower scanning lines of the image data stored in the line memory 12, respectively.

The arithmetic circuit 14 includes line memories 11 and 12
And 13 are added and output to the selector 18. The comparators 15 and 16 include the line memories 11, 1
The luminance difference between the image data of one scanning line from 2 and 13 is compared with the image data of the scanning line above it and the image data of the scanning line below it. The selector 18 selects and outputs one of the output composite image data of the arithmetic circuit 14 and the output image data of the line memory 12 with a signal obtained by performing an OR operation on the output signals of the comparators 15 and 16 by the OR circuit 17. The non-interlaced / interlaced converter 19 converts non-interlaced image data output from the selector 18 into an interlaced image signal and outputs it.

Next, the operation of this embodiment will be described. Non-inlace image data output from a personal computer or the like is input to line memories 11, 12, and 13, respectively. Here, the line memory 11 always stores one of the scanning lines of the image data input to the line memory 12.
Image data of the scanning line on the book is input, and the line memory 1
In 3, image data of a scanning line one line below the scanning line of the image data input to the line memory 12 is input and stored. The image data respectively stored in the line memories 11, 12 and 13 are read out and
, Where an operation is performed to reduce the difference in luminance between the upper and lower lines.

FIG. 2 is a block diagram showing an example of the arithmetic circuit 14. Here, as described in JP-A-6-83299, among the three adjacent scanning lines, the image data of the central scanning line is “0.5”, and the image data of a total of two upper and lower scanning lines is “0.5”. Is added with a weight of “0.25”. That is, the output image data of the line memory 12 is shifted rightward by one bit by the shift register 32 and halved, and then supplied to the adding circuit 34. on the other hand,
The output image data of the line memories 11 and 13 are supplied to shift registers 31 and 33, respectively, shifted right by two bits and multiplied by ４, and then supplied to an adder. The adder 34 outputs the image data as the weighted image data of the three scanning lines in total.

Referring again to FIG. 1, the image data of two adjacent scanning lines taken out of the line memories 11 and 12 are supplied to a comparator 15 where the difference in luminance is compared. Similarly, image data of two adjacent scanning lines taken out from the line memories 12 and 13 are:
The luminance difference is supplied to the comparator 16 and compared.
The comparators 15 and 16 determine that the luminance difference is large when the luminance of the two input image data has a larger luminance than the smaller luminance, and outputs a luminance difference determination signal. OR circuit 1
7 indicates that when these luminance difference determination signals are output from one or both of the comparators 15 and 16, the image data stored in the line memory 12 has a large luminance difference from the image data of the upper and lower scanning lines. The detection signal shown in FIG.

The comparators 15 and 16 have the same configuration, for example, a circuit configuration as shown in FIG.
In the figure, magnitude comparators 41 and 4
Step 2 determines whether the input signal at the input terminal A has a higher level than the input signal at the input terminal B. The input signal X input to the input terminal A of the magnitude comparator 41 and the input signal X input to the input terminal B of the magnitude comparator 42 are:
The input signal Y, which corresponds to the output signal of the line memory 11 and is input to the input terminal B of the magnitude comparator 41 and the input terminal A of the magnitude comparator 42,
It corresponds to the output signal of the line memory 12. 3 is the case of the comparator 15, and in the case of the comparator 16, the input signal X corresponds to the output signal of the line memory 11 and the input signal Y corresponds to the output signal of the line memory 13.

Here, assuming that the input signals X and Y each have 8 bits, the signal X input to each input terminal A of the magnitude comparators 41 and 42 is
, And Y (signals 51 and 54) are input as they are 8 bits. On the other hand, the magnitude comparator 4
1 and 42, the signals Y and X input to the input terminals B
As the (signals 53 and 52), values of the upper 7 bits equivalent to shifting the signals Y and X one bit to the right are input.

The magnitude comparator 41 compares the value of the signal 51 with the value of the signal 53, and if the signal 51 is larger, outputs a signal 56 of logic "1". Here, signal 5
1 is the value of the signal X, and the signal 53 is the value of the upper 7 bits of the signal Y, that is, 1/2 the value of the signal Y.
When the signal 56 of 1 ″ is output, the value of the signal X is larger than 値 times the value of the signal Y.

Similarly, the magnitude comparator 42
Compares the value of the signal 54 with the value of the signal 52, and outputs a signal 57 of logic "1" if the signal 54 is larger. Here, since the signal 54 is the value of the signal Y and the signal 52 is the value of the upper 7 bits of the signal X, that is, the value of １ ／ times the signal X, the signal 57 of logic “1” is output. Is the signal Y
Is larger than 1/2 the value of the signal X.

The OR circuit 43 outputs these signals 56 and 57
Is output. Therefore, O
When the signal of logic "1" is output from the R circuit 43, the value of the signal X is larger than 1/2 the value of the signal Y, or the value of the signal Y is larger than the value of 1/2 the signal X. When it is large, that is, it indicates that the level difference between the signal X and the signal Y is twice or more. Thus, the comparator can be configured with a small-scale circuit.

Returning to FIG. 1, the selector 1
Reference numeral 8 denotes a case where the detection signal indicating that the luminance difference is large is input from the OR circuit 17 and the composite image data from the arithmetic circuit 14 is selected, and the detection signal is not input (that is, when the luminance difference is small). Selects the output image data of the line memory 12. The output image data of the selector 18 is supplied to a non-interlace / interlace converter 19, where it is converted into an interlaced image signal and output. The non-interlace / interlace converter 19 can be realized by, for example, a frame buffer memory and an address control circuit that replaces some bits of an address at the time of writing and at the time of reading.

As described above, according to this embodiment, only the image data of a scanning line having a large difference in luminance from the upper and lower scanning lines is obtained by weighting and synthesizing the image data of three adjacent scanning lines. Since image data is output and scan-converted, flicker that is noticeable due to a large difference in brightness between the upper and lower scanning lines can be reduced by reducing the difference in brightness. In addition, by lowering the vertical resolution of the image signal after scan conversion, which is reduced by weighting synthesis, image data of a scanning line having a small difference in luminance from the upper and lower scanning lines is output as it is without weighting synthesis, and scan conversion is performed. It can be prevented from lowering as much as possible.

Further, in this embodiment, the comparators 15 and 16 can each be composed of two magnitude comparators and one OR circuit, and the arithmetic circuit 14
Can be configured by the shift registers 31 to 33 and the adder 34, so that the configuration can be made inexpensive and small.

The present invention is not limited to the above embodiment. For example, it is determined that there is a luminance difference when the luminance difference is 1/2 or more. It is also possible to set the value to

[0031]

As described above, according to the present invention,
Only when the luminance difference between the image data of the upper and lower lines is equal to or greater than a predetermined value, scan conversion is performed using combined image data obtained by adding and combining the image data of the scan line to be converted and the image data of the upper and lower lines. With this configuration, flicker can be reduced, and image data of a scanning line having a luminance difference between the upper and lower scanning lines smaller than a predetermined value is directly subjected to scan conversion, so that a decrease in vertical resolution can be suppressed as much as possible.

According to the present invention, composite image data is generated using a multiplier or an adder without using a table.
In addition, since the difference between the image data of the scanning line to be converted and the image data of the upper and lower lines is detected by using a magnitude comparator, a logic circuit, or the like, whether or not the luminance difference is equal to or greater than a predetermined value, when a table is used, R with large required capacity
No OM is required, and the circuit configuration can be made inexpensive and small in size as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of an arithmetic circuit in FIG. 1;

FIG. 3 is a circuit diagram of an example of a comparator in FIG.

FIG. 4 is a block diagram of an example of the related art.

FIG. 5 is a block diagram of another conventional example.

[Explanation of symbols]

 11 to 13 line memory 14 arithmetic circuit 15, 16 comparator 17, 43 OR circuit 18 selector 19 non-interlace / interlace converter 31, 33 2-bit shift register 32 1-bit shift register 34 adder 41, 42 magnitude comparator

Claims (3)

[Claims] 1. A storage unit for temporarily storing non-interlaced image data at least for each of a scanning line to be converted and one scanning line above and below, and a plurality of non-interlaced images from the storage unit An arithmetic circuit for generating combined image data by weighting and synthesizing the data, and a luminance difference between the image data of the scan line to be converted from the storage means and any of the image data of the scan lines above and below the predetermined value is equal to or more than a predetermined value. Comparing means for determining whether or not there is, and selecting the output composite image data of the arithmetic circuit only when the luminance difference is determined to be equal to or more than a predetermined value, and when it is determined to be less than the predetermined value, Selecting means for selecting image data of the scan line to be converted from the storage means; and converting the image data selected by the selecting means into a desired interlaced format. Scan conversion circuit; and a converting means for converting the image signal. 2. An arithmetic circuit comprising: a first multiplying unit for multiplying image data of the scan line to be converted output from the storage unit by a first weighting coefficient; Second multiplying means for multiplying the image data of a total of two scanning lines above and below the conversion target scanning line by a second weighting coefficient having a value smaller than the first weighting coefficient; 2. The scan conversion circuit according to claim 1, further comprising an adder for adding the respective multiplication results of the second multiplication means to generate the composite image data. 3. The comparing means compares the value of all bits of the input first image data with the value of the input second image data shifted right by one bit, and A first magnitude comparator that outputs a first signal of a predetermined logical value when the value is larger, a value of all bits of the input second image data, and a value of the input first image data. A second magnitude comparator for comparing a value shifted to the right by one bit and outputting a second signal of a predetermined logical value when the value of all the bits is larger; and a second magnitude comparator for comparing the first and second magnitude comparators. A logic circuit that outputs a determination signal indicating that the luminance difference is equal to or more than a predetermined value when a signal of the predetermined logic value is output from at least one of the two comparators; The image data of the scan line to be converted is input as the first image data of the above, and the respective image data of the scan lines above and below the scan line to be converted are respectively input as the second image data of both comparators. 3. The scan conversion circuit according to claim 1, wherein the input is input.