JPH1023026A - N-bit parallel signal cell transfer method and device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the configuration of a cell assembly circuit and a cell re-assembly circuit and to enhance the transfer efficiency. SOLUTION: When a received N-bit parallel signal (input signal) 1 is assembled into an ATM cell 2 of an asynchronous transfer mode adaptation layer (AAL) type 1, the input signal 1 is separated into 8-bit width, as shown in the arrow A, without the addition of excess bits, and each of the divided data is stored in a segmentation and reassembly protocol data unit (SAR-PDU) payload 5 of each cell. '1' is inserted to a convergence sublayer indicator (CSI) bit 6 in the case of a cell whose head of the payload 5 is in matching with N-bit border of the input signal 1, and '0' is inserted in the case of a cell whose head of the payload 5 does not match the border of the input signal 1 respectively. In the case of reassembling the N-bit parallel signal 1 from the ATM cell 2, the cell of the N-bit border is detected from the CSI bit 6 and the N-bit width parallel signal 1 is assembled by the cell of the N-bit border.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an asynchronous transfer mode (hereinafter referred to as ATM).
The present invention relates to a parallel signal cell transfer system for assembling, disassembling, and transferring parallel signals in a cell in the communication system described above, and in particular, to an N-bit parallel fixed bit rate (Cons
tant Bit Rate: CBR) signal is transmitted to ITU (formerly CCIT)
T) ATM type 1 ATM adaptation layer (AAL) based on recommendations
The present invention relates to a parallel signal cell transfer system for assembling, disassembling, and transferring cells.

[0002]

2. Description of the Related Art An AAL type 1 protocol type based on the above-mentioned ITU recommendation is an adaptation layer protocol which assumes a conventional CBR signal service such as voice communication or a dedicated line service.
As shown in FIG. 2, a 5-octet ATM cell header 3
And 1-bit CSI (Convergence Sublayer Indicat)
or) Sequence counter of 6 and ATM cells (Sequ
SC that is an error counter) and (Cycric Red) for error control
andancy Check) 1-octet SAR-PDU (Segmentation And Reassem) including CRC and (Parity) P
(Bly-Protocol Data Unit) header 4 and a 47-octet SAR-PDU payload 5 for a total of 53 octets.

Conventionally, the cell transfer method of the AAL type 1 CBR signal has been intended for data transfer of an 8-bit byte structure for the above-described reason. Therefore, an AAL type 1
When the ATM cell is transferred as an ATM cell, the transmitting side adds an extra bit to the N-bit parallel signal to form an ATM cell on the transmitting side so as to become byte-structured data.
In addition, when frame information is included in a signal, a surplus bit for indicating a cell containing a frame head is added in addition to a surplus bit for aligning a frame head with a payload head.

On the receiving side receiving the ATM cell, the received ATM cell is converted into byte-structured data, and the added extra bits are removed to restore the original N-bit parallel signal.

For example, when a 10-bit parallel data signal is transferred as a cell, 6-bit data is added to 10-bit data.
16 bits by adding an extra bit of bits,
Converted to 2-byte data, and 47-byte SA
The R-PDU payload is transferred using a method such as arranging one extra bit in the last byte of the R-PDU payload, and the receiving side removes these extra bits to restore a 10-bit parallel data signal.

[0006]

As described above, the conventional A
In the AL type 1 CBR cell transfer method, since redundant bits are added twice to a signal to be converted into an ATM cell, the structure of a cell assembly / reassembly circuit for a data signal becomes complicated. In cell transfer of signals, the ratio of surplus bits to transfer bits is 1
46/376, that is, about 39%, which is a disadvantage that the transfer efficiency is deteriorated.

[0007] It is an object of the present invention to overcome the above-mentioned drawbacks and to provide an 8
It is an object of the present invention to provide an N-bit parallel signal cell transfer system which simplifies the configuration of a cell assembly circuit and a cell reassembly circuit and transfers data more efficiently when transferring N-bit parallel CBR signals other than bits.

[0008]

In order to achieve the above object, an N-bit parallel signal cell transfer method according to the present invention converts an input N-bit parallel CBR signal into an ATM cell header and a SA according to an AAL type 1 cell format.
The cell is assembled into an ATM cell composed of an R-PDU header and an SAR-PDU payload, an ATM cell whose head of the SAR-PDU payload coincides with the N-bit boundary of the input signal is detected, and the head of the SAR-PDU payload and the input signal are detected. Is transferred by using the corresponding ATM cell, and the transferred ATM cell is reassembled into an N-bit parallel CBR signal and output.

Further, when cell assembly is performed according to the AAL type 1 cell format by this method, cell assembly is performed without adding a surplus bit for forming a byte structure, and CSI is used to transfer boundary information of an N-bit signal.
It is desirable to use bits.

Further, when frame information is included in an input N-bit parallel signal, AAL type 1 is used without adding a surplus bit for storing a frame in an ATM cell.
It is desirable to perform cell assembly in accordance with the cell format described above.

The N-bit parallel signal cell transfer device according to the present invention converts an input N-bit parallel signal into an ATM cell header and an S-cell according to an AAL type 1 cell format.
Cell assembling means for cell assembling into an ATM cell comprising an AR-PDU header and an SAR-PDU payload, and an ATM in which the head of the cell-assembled SAR-PDU payload coincides with the N-bit boundary of the input signal.
A signal boundary information generating means for detecting a cell to generate signal boundary information, a signal boundary information transferring means for transferring the generated signal boundary information by a corresponding ATM cell,
Reassembly means for reassembling the TM cell into an N-bit parallel signal and outputting the signal.

The above-described N-bit parallel signal cell transfer device desirably converts a cell assembly circuit and a cell reassembly circuit, that is, an N-bit parallel CBR signal into 8-bit parallel, and generates an SAP-PDU payload. A data parallel conversion unit and the input N
An M cell counter for detecting a cell in which the boundary of the bit parallel signal coincides with the beginning of the SAR-PDU payload and generating a pulse indicating the detection;
When a pulse indicating a cell matching the beginning of the DU payload is received, the CSI bit of the SAR-PDU header is set to “1”. When no pulse is received, the SAR-PD
When the CSI bit of the U header is set to “0”, the SAR-PD
A SAR-PDU header generation unit for generating a U header, an ATM cell header generation unit for generating a cell header of an ATM cell to be transmitted, a generated SAR-PDU header, and an AT
A cell assembly circuit including a multiplexing unit that multiplexes an M cell header and an SAR-PDU payload to generate an ATM cell; a demultiplexing unit that separates an input ATM cell into a SAR-PDU payload and a SAR-PDU header; An M counter for generating a pulse indicating a cell whose N-bit boundary of the signal coincides with the beginning of the SAR-PDU payload, and a SAR-PDU separated from the pulse indicating this coincidence
The cell reassembly circuit includes a synchronization detection unit that performs frame synchronization of an N-bit parallel signal using the CSI bit of the header, and a parallel conversion unit that converts data of the SAR-PDU payload into an N-bit parallel signal.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an outline of a cell assembly / reassembly of a parallel signal cell transfer system according to an embodiment of the present invention, FIG. 2 is a diagram showing an AAL type 1 cell format, and FIG. FIG. 4 is a block diagram showing an example of the configuration of a cell reassembly unit.

In FIG. 1, when assembling an N-bit parallel signal 1 to be transferred into an ATM cell 2, as shown by an arrow A, the N-bit parallel signal 1 is decomposed into an 8-bit width without adding extra bits. SAR-PDU
It is stored in the payload 5. At this time, if the head of the payload is a cell that matches the N-bit boundary of the N-bit parallel signal 1, "1" is set to the CSI bit 6, and if the cell does not match, "0" is set to the CSI bit 6. Insert each. A cell in which the head of the SAR-PDU payload 5 matches the N-bit boundary of the N-bit parallel signal 1 is SA
Since the R-PDU payload 5 is 47 × 8 bits,
Appears every first cell and from the first cell (the least common multiple of N and 8) / 8 = M cells.

When reassembling the ATM cell 2 into the N-bit parallel signal 1, the SAR-
An N-bit boundary of the parallel signal 1 is detected from the CSI bit 6 of the PDU header 4 and the SA is detected based on the N-bit boundary.
R-PDU payload 5 is converted to N-bit wide parallel signal 1
Assemble to

The cell assembly unit 30 according to one embodiment of the present invention shown in FIG. 3 includes a data parallel conversion unit 31, an M cell counter 32, a SAR-PDU header generation unit 33, an ATM header generation unit 34, and a multiplexing unit 35. .

The data parallel conversion unit 31 has N bits C
The SAR-PDU payload 5 is generated by converting the BR parallel signal 1 into an 8-bit parallel signal. The M cell counter 32 counts the number of cells starting from the first cell, that is, the cell where the beginning of the SAR-PDU payload 5 and the boundary of the N-bit CBR parallel signal 1 match, and the M-th cell (where M is ( The boundary information is sent to the SAR-PDU header generator 33 every time (the least common multiple of N and 8) / 8). The SAR-PDU header generation unit 33 outputs the SAR-P in the case of each Mth cell from the beginning, that is, the cell whose N-bit boundary matches the beginning of the payload.
The SAR-PDU is inserted by inserting “1” into the CSI bit 6 of the DU payload 5 and “0” into the CSI bit 6 in the case of a cell other than every M-th cell where the N-bit boundary does not match the beginning of the payload. Generate header 4. The multiplexing unit 35 includes the SAR-PDU header 4 and the SAR-PDU
The ATM cell 2 is generated from the data of the payload 5 and the data of the ATM header 3 generated by the ATM header generating unit 34.

A cell reassembly unit 4 according to one embodiment of the present invention.
0 has a separation unit 41, an M cell counter 42, a CSI bit detection unit 43, and a data parallel conversion unit 44, as shown in FIG.

The separating unit 41 converts the received ATM cell 2 into S
It is separated into an AR-PDU payload 5 and an SAR-PDU header 4. The CSI bit detection unit 43 uses the SAR-PD
According to the CSI bit 6 of the U header 4, the N
Detect bit boundaries. The M cell counter 42 counts the received ATM cells 2 and detects the first cell and every Mth cell as cells where the N-bit boundary of the signal coincides with the beginning of the SAR-PDU payload. The data parallel conversion unit 44 includes the M cell counter 42 and the CSI
According to the N-bit boundary information output from the bit detector 43,
The frame synchronization is performed, and the separation unit 41 separates and outputs S
AR-PDU payload data is converted to N-bit parallel C
Reassemble to BR signal.

That is, in the parallel signal cell transfer method of the present embodiment, the cell assembly unit 30 decomposes the input N-bit parallel signal other than the 8-bit parallel signal into an 8-bit width without adding extra bits. Te SA
The cell is assembled as an R-PDU payload, and the coincidence information between the beginning of the payload and the boundary of the N-bit parallel signal 1 is transferred with the CSI bit set to “1”. In accordance with the information of the N-bit boundary of the parallel signal, frame synchronization is performed and cell reassembly is performed to generate an N-bit parallel C signal.
Since the BR signal can be restored, when N is other than 8, it is not necessary to add or delete extra bits for forming a byte configuration. If the signal contains frame information,
Since it is not necessary to add information for indicating the cell containing the head of the frame, the circuit configuration can be further simplified, and the efficiency of data transfer can be further increased.

[0022]

As described above, according to the present invention, the input N-bit parallel CBR signal is cell-assembled according to the AAL type 1 cell format, and the N-bit boundary information of the input signal is inserted into the CSI bit and transferred. Thus, there is an effect that the procedure of adding a surplus bit when the structure of the input signal is not the byte structure is unnecessary, and the configuration of the cell assembly / reassembly circuit can be simplified.

In addition, since a byte structure is used and a procedure for adding a surplus bit for frame information is unnecessary,
Only the data of the input signal needs to be arranged in the SAR-PDU payload, which has the effect of improving the data transfer efficiency.

[Brief description of the drawings]

FIG. 1 is a diagram showing an outline of a cell assembly / reassembly according to an embodiment of the present invention.

FIG. 2 is a diagram showing an AAL type 1 cell format of the embodiment of FIG.

FIG. 3 is a block diagram illustrating a configuration example of a cell assembly unit according to the present invention.

FIG. 4 is a block diagram illustrating a configuration example of a cell reassembly unit according to the present invention.

[Explanation of symbols]

 1 N-bit parallel CBR signal 2 ATM cell 3 ATM cell header 4 SAR-PDU header 5 SAR-PDU payload 6 CSI bit 30 Cell assembly unit 31 Data parallel conversion unit 32 M cell counter 33 SAR-PDU header generation unit 34 ATM header generation unit 35 Multiplexing unit 40 Cell reassembly unit 41 Separation unit 42 M cell counter 43 CSI bit detection unit 44 Data parallel conversion unit

Claims (5)

[Claims] 1. An ATM communication system N-bit parallel signal cell transfer method in which an input N-bit parallel CBR signal is converted into an ATM cell and transferred, wherein the input N-bit parallel CBR signal is AAL.
According to a type 1 cell format, the cell is assembled into an ATM cell including an ATM cell header, an SAR-PDU header, and an SAR-PDU payload, and an ATM cell in which the head of the SAR-PDU payload matches the N-bit boundary of the input signal is detected. The information indicating that the boundary match has been detected is stored in the corresponding AT.
A method for transferring an N-bit parallel signal cell, comprising adding and transferring an M cell and transferring the transferred ATM cell into an N-bit parallel CBR signal. 2. When assembling an input N-bit parallel CBR signal into a cell, cell assembly is performed according to the AAL type 1 cell format without adding a surplus bit for forming a byte structure, and a boundary match is detected. Attach ATM cell information to the corresponding ATM
2. The N-bit parallel signal cell transfer method according to claim 1, wherein the transfer is performed by a CSI bit in a SAR-PDU header of the cell. 3. The cell assembly according to claim 2, wherein when frame information is included in the N-bit parallel CBR signal, cell assembly is performed according to the AAL type 1 cell format without adding a surplus bit for storing a frame in an ATM cell. N-bit parallel signal cell transfer method. 4. An N-bit parallel CBR signal is input into an ATM cell and transferred by an ATM communication system, and the transferred ATM cell is reassembled into an N-bit parallel CBR signal and output. In the bit parallel signal cell transfer device, the input N-bit parallel CBR signal is
Cell assembly means for assembling an ATM cell comprising an ATM cell header, a SAR-PDU header and a SAR-PDU payload according to a type 1 cell format, and the cell-assembled SAR-PD
A signal boundary information generating means for detecting an ATM cell whose head of the U payload coincides with the boundary of N bits of the input signal and generating signal boundary information; and transferring the generated signal boundary information by the corresponding ATM cell. An N-bit parallel unit comprising: a cell assembly unit including signal boundary information transfer means; and a cell reassembly unit including reassembly means for reassembling the transferred ATM cell into an N-bit parallel signal and outputting the same. Signal cell transfer device. 5. A data-parallel conversion unit for converting an N-bit parallel CBR signal into 8-bit parallel data to generate an SAP-PDU payload, and a boundary between the input N-bit parallel CBR signal and SAR
-An M cell counter for detecting a cell that matches the PDU payload head and generating a pulse indicating the detected cell; and when receiving a pulse indicating a cell that matches the N-bit boundary and the SAR-PDU payload head. , SAR-
When the CSI bit of the PDU header is set to "1" and the pulse is not received, the CSI bit of the SAR-PDU header is set to "0", and a SAR-PDU header generation unit for generating a SAR-PDU header; An ATM cell header generating unit for generating a cell header of a cell; and an ATM unit for multiplexing the generated SAR-PDU header, ATM cell header and SAR-PDU payload.
A cell assembly section including a multiplexing section for generating cells; a separating section for separating an input ATM cell into a SAR-PDU payload and a SAR-PDU header; an N-bit boundary of a signal and a head of the SAR-PDU payload. An M counter for generating a pulse indicating a matched cell, a synchronization detection unit for performing frame synchronization of an N-bit parallel signal by using the pulse indicating the match and the separated CSI bit of the SAR-PDU header, and a SAR-PDU payload 5. The N-bit parallel signal cell transfer device according to claim 4, further comprising: a cell reassembly unit including a parallel conversion unit that converts the data of (b) into an N-bit parallel CBR signal.