JPH1022989A - Frame synchronizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To contrive to save power by stopping the receiving operation in an unnecessary time slot as long as possible when frame synchronization is not established. SOLUTION: Decoded data from a receiving circuit 2 is first calculated by a CRC arithmetic part 5. When the result of the arithmetic is correct, it is regarded that a correct CRC arithmetic result is obtained based on a CRC bit existing at the prescribed position of each time slot so that the boundary of the time slot can be set by basing on the position of the CRC bit as a reference. At this time a frame number and a slot number obtained based on a unique code obtained by a unique code judging part 3 are loaded as a initial value to a counter within a TDMA (time-division multiplex communication) managing part 6. As a receiving position is known by the value of a counter in spite of not always detecting the synchronizing bit of received data, reception is operated only at the time of a necessary time slot and the operation of a receiving part 1 can be stopped at the time of unnecessary time slot.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a frame synchronization circuit for detecting a frame in received data and establishing synchronization in mobile communication or the like.

[0002]

2. Description of the Related Art In a digital cellular system composed of a base station and a plurality of wireless terminal devices, a TDMA (Time Division Multiplexing Communication) system is adopted in order to use frequencies effectively, and one frequency is set for a predetermined time (time). (Slots), and a plurality of communication channels are allocated to each time slot, so that one frequency is shared by several persons to improve communication efficiency.

[0003] For example, personal communication
In a system (hereinafter referred to as PACS), as shown in FIG. 3, eight time slots (TS
0 to TS7), and each time slot is composed of 120 bits of data. The communication channel is allocated to these time slots. Each time slot includes a unique code consisting of a specific bit pattern, a frame number, a slot number, a CRC bit, and the like. Is performed based on the unique code.

That is, the unique code in the time slot indicates whether the time slot is a line connection time slot, an empty slot, a busy slot, or a use prohibition slot. The terminal device firstly receives a predetermined time slot (for example, TS
0) is synchronized by detecting a pattern of a line connection unique code in which information necessary for connection with a base station existing in the time slot (TS1) is detected.
ＴＳTS7) to detect a unique code indicating an empty slot, and secure a time slot required for a call.

In order to secure time slots as described above, a conventional circuit is configured as shown in FIG. 4, and data transmitted by a base station is input to a receiving section 2 via an antenna 1 and received by the receiving section. The unit 2 decodes this and outputs it. The unique code determination unit 3 keeps monitoring the unique code pattern present in the decoded received data, and the slot number is determined according to the slot number continuously given after the detection of the pattern. It was determined whether it was a slot or not.

If the time slot number is TS0
If so, the switch 4 is turned on to operate the CRC calculation unit 5 to perform the CRC calculation in the slot. If there is an error in the operation result, the detection of the true unique code pattern is restarted. If there is no error, the counter in the TDMA management unit 6, that is, 8 frames × 8 time slots × 1
The frame synchronization is established by setting a counter value of a 13-bit counter capable of counting 20 bits = 7800 bits to determine a reference position. Then, under the establishment of the synchronization, an empty slot is searched from among the time slots TS1 to TS7 to secure a communication channel.

[0007]

However, since the unique code detecting section 3 must constantly monitor the line connection time slot TS0 which does not know at which timing it appears, the unique code detecting section 3 always operates the receiving section. Therefore, there is a problem that power consumption is always increased.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and when the frame synchronization is not established, the operation of the receiving unit is stopped in a time slot that is unnecessary as much as possible to save power. The purpose is to plan. In order to achieve this object, the frame synchronization circuit according to the present invention comprises:
Means for performing a CRC operation on each time slot in one frame of received data having a TDMA frame structure, and as a result, detecting a frame number and a time slot number existing in the next time slot by detecting a time slot boundary Means for stopping reception up to a predetermined position where a unique code exists based on these. Further, the frame synchronization circuit is characterized in that a frame number, a slot number and received data are counted using respective counters in order to clarify the current data position.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail based on an embodiment shown in the drawings. FIG. 1 is a block diagram showing a configuration of a frame synchronization circuit according to the present invention. The same components as those in the related art are denoted by the same reference numerals and description thereof will be omitted. In the figure, the unique code judging section 3 is connected to the receiving section 2 via the switch 7 and the CRC calculating section 5 is connected to the receiving section 2 via the switch 5, and the switch 7 is controlled by a detection signal from the CRC calculating section. , And switch 4 is T
Switching is performed under the control of the DMA management unit 6. Further T
The DMA management unit 6 is configured to receive not only the determination result from the unique code determination unit 4 but also the calculation result of the CRC calculation unit 5.

In the above configuration, first, in a state where synchronization is to be established, the switch 4 is on and the switch 7 is off, and the decoded data from the receiving unit 2 is processed by the CRC calculating unit 5. Will be If the calculation result is correct, the CR existing at a predetermined position of each time slot
Since the correct CRC calculation result is obtained based on the C bits, the time slot boundary can be set based on the position of the CRC bits. For example, in FIG. 3, since the CRC bit exists at the last position of the time slot, it can be determined that immediately after that is a time slot boundary. At this time, the CRC calculation unit 5 turns on the switch 7 to permit input of data to the unique code determination unit 3 and, at the same time, outputs a timing pulse to the TDMA management unit 6.

TDMA to which the timing pulse is input
The management unit 6 resets the internal counter to determine the timing of synchronization pull-in. The counter in the TDMA management unit 6 has a configuration as shown in FIG. 2, and includes a frame counter 8 and a time slot counter 9 composed of a 3-bit counter, and a data counter 10 composed of a 7-bit counter. It consists of a counter. By resetting the data counter 10, the boundaries of the time slots are set, and the position of the unique code starting from the head of the data of the next time slot can be detected by the value of the counter 10.

Further, the unique code judging section 3 reads a bit pattern at a subsequent predetermined position and compares it with the plurality of unique code patterns. However, since it is not known which time slot is obtained at this time, the extracted bit pattern is compared with all the prescribed types of unique codes. For example, the operation of the CRC operation unit is stopped, and the frame number and the slot number detected by the data processing unit are loaded into the respective 3-bit counters 8 and 9 in the TDMA management unit 6 as initial values.

Accordingly, a frame number and a slot number are set in these 3-bit counters 8 and 9, respectively, and counting is continued in synchronization with the reception timing. Therefore, the time slot number to be received can be known from these count values. In other words, even if the synchronization bit of the received data is not always detected, the reception position can be determined by the value of the counter, so the reception operation is performed only at the required time slot, and the operation of the reception unit is stopped at the unnecessary time slot Can be.

[0014]

Since the present invention is constructed as described above, a unique code consisting of a short bit pattern of several bits which may exist anywhere can be synchronized at a time by frame calculation by CRC operation. The position of a time slot that does not need to be received can be confirmed, and power can be saved by receiving only a necessary time slot.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a frame synchronization circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration of a counter in a TDMA management unit.

FIG. 3 is a diagram showing an example of a TDMA frame configuration.

FIG. 4 is a block diagram showing a configuration of a conventional frame synchronization circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Antenna 2 ... Reception part 3 ... Unique code detection part 4, 7 ... Switch 5 ... CRC calculation part 6 ... TDMA management part 8, 9, 10 ... Counter

Claims (2)

[Claims] 1. A means for performing a CRC operation process on each time slot in one frame of received data having a TDMA frame structure, and as a result, by detecting a boundary of the time slot, a frame number and a frame number existing in the next time slot are detected. A frame synchronization circuit comprising means for detecting a time slot number, and stopping reception to a predetermined position where a unique code exists based on the time slot number. 2. The frame synchronization circuit according to claim 1, wherein the frame number, the slot number, and the reception data are counted using respective counters in order to clarify the current data position. circuit.