JPH10229380A - Communication equipment in which code division multiple access system is used - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide communication equipment in which a code division multiple access system, capable of satisfying technical standards within a range where transmitting power of a transmitting signal is regulated by radio low, moreover improving the degrees of freedom of a system by enabling even-numbered multiplicity. SOLUTION: Code division multiple access system is constituted so that data signals D1 to Dn are spread and modulated by a P-N code by a transmitter 30, a transmitting signal Sc is generated and outputted by multiplying the data signals D1 to Dn by judging a majority logic by a majority logic circuit 32, the transmitting signal Sc is spread reversely and demodulated by the P-N code and the original data signals D1 to Dn are obtained. In this case, when the judged majority logic shows equivalent values and a majority signal M indicating a majority result of '1' or '0' is not outputted, the code division multiple access system is constituted, so that the transmitting signal Sc is generated and outputted, based on an equivalent value signal N set as either '1' or '0'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread signal obtained by spreading and modulating a data signal assigned to a plurality of data channels on a transmitting side with a PN code, and multiplexing the spread signal by majority logic decision to obtain a spread signal. The present invention relates to a communication apparatus using a code division multiple access system that obtains a data signal by demodulating a transmission signal output and received at a receiving side by a PN code.

[0002]

2. Description of the Related Art Code Division Multiple Access
In the iple Access (hereinafter abbreviated as CDMA) system, for example, on the transmitting side, a data signal assigned to each of a plurality of data channels is spread with a different spreading code for each data channel, and the spread signal has a predetermined frequency. A carrier is modulated, the modulated signal is multiplexed by adding the modulated signal, etc. to generate a transmission signal, and the receiving side demodulates the transmission signal by despreading the transmission signal with a spreading code used on the transmission side to obtain the original data. This is a communication method for obtaining signals.

The CDMA system differs from other data communication systems, such as the frequency division multiple access system and the time division multiple access system, due to the essential characteristics of the spread spectrum system. have.

[0004] (1) It is difficult to cause interference or interference to existing systems. (2) Resistant to interference and interference from existing systems. (3) It is easy to take measures against data transmission quality deterioration due to multipath propagation. (4) A highly confidential communication system can be constructed. (5) Broadband transmission is easy with an increase in data transmission speed. (6) The system capacity may be increased.

FIG. 16 shows an example of the configuration of a conventional communication system employing such a CDMA system. In the transmission device 10, when the data signals D1 to Dn are assigned to each of the n data channels, the data signals D1 to Dn are assigned to the PN codes PN1 as the spreading codes assigned differently for each data channel. ~ P
The spread signals are spread and modulated by N spreaders 111 to 11n by Nn, and output as spread signals K1 to Kn.

A carrier f1 of a predetermined frequency output from the carrier generator 12 with these spread signals K1 to Kn is phase-modulated (for example, 2) by n phase modulators 131 to 13n.
Phase modulation) and output as modulated signals P1 to Pn. Then, the modulation signals P1 to Pn are added by the adder 14, and a multiplexed transmission signal Sa is output.

The transmission signal Sa output in this manner is
Is given to the receiving device 20, the n despreaders 21
1 to 21n, and also to a reproduction synchronous carrier generator 22. Then, based on the transmission signal Sa being given to the reproduction synchronous carrier generator 22, a PLL (Phase Lock Loop) circuit 23 therein generates a reproduction synchronous carrier f2 synchronized with the carrier f1, and the reproduced synchronous carrier f2 is generated. f2 is spread by n spreaders 241 to 24n by the PN codes PN1 to PNn, and intermediate signals Q1 to Qn are output.

[0008] The transmission signal Sa is the intermediate signal Q
1 to Qn, despread by despreaders 211 to 21n and output as demodulated signals R1 to Rn. These demodulated signals R1 to Rn are divided into n band-pass filters (BPFs) 25.
By passing through 1 to 25n, noise components are removed and original data signals D1 to Dn are obtained. In this manner, the data signals D1 to Dn are multiplexed and
0 and the receiving device 20.

However, in such a communication system,
As described above, since the modulation signals P1 to Pn are added and multiplexed by the adder 14, the amplitude of the transmission signal Sa, that is, the transmission power, may increase in proportion to the number of multiplexed data channels. . Therefore, when the number of multiplexed data channels exceeds a predetermined number of multiplexes, there is a problem that the transmission power of the transmission signal Sa exceeds the range regulated by the Radio Law.

[0010] On the other hand, it is considered that the transmission power of each data channel is set to (1 / multiplex number) so that the transmission power of the transmission signal Sa falls within a range regulated by the Radio Law. However, in this case, when the number of multiplexes increases, the transmission power per data channel decreases, so that the SN ratio of each data channel decreases, and as a result, the transmission quality decreases. Will happen.

[0011]

Therefore, in order to solve the above-mentioned problems, as shown in FIG.
A communication system employing a majority logic circuit in the A system (JP-A-6-268631) has been considered. That is, in the transmitting device 15, n spreaders 111 to 11
The spread signals K1 to Kn generated for each of n are output to the majority logic circuit 16, and the majority logic circuit 16 makes a majority logic decision for each time slot, thereby outputting the majority signal M to the phase modulator 17 as a majority signal M. You. Then, the carrier f1 output from the carrier generator 12 by the majority signal M is phase-modulated by the phase modulator 17, and the transmission signal Sb is output.

In this case, since the transmission signal Sb is generated by phase-modulating the carrier f1 with one majority signal M as described above, the n modulated signals P1 to Pn as described above are added. Unlike the transmission signal Sa to be multiplexed, the transmission power is equal to the transmission power per channel.

That is, even if the number of multiplexed data channels increases, the transmission power of the transmission signal Sb can be kept within the range regulated by the Radio Law. Incidentally, such a majority logic circuit 1
6 also employs a configuration using the same receiving device 20 as the configuration described above,
The transmission signal Sb can be demodulated to obtain the original data signals D1 to Dn.

However, in a communication system employing such a majority logic circuit 16, since the majority logic decision is made as described above, the number of data channels is odd so that the majority logic decision result can be obtained. In other words, the number of data channels cannot be set to an even number, and there is a problem that system design is restricted.

The present invention has been made in view of the above circumstances, and has as its object to satisfy the technical standards by setting the transmission power of a transmission signal within a range specified by the Radio Law.
In addition, it is an object of the present invention to provide a communication device using a code division multiple access system that can improve the degree of freedom of the system.

[0016]

According to the first aspect of the present invention, when a data signal is allocated to a plurality of data channels, the transmitting section transmits the data signal to a plurality of data channels by a spreading means.
A spread signal is output by spreading modulation with the N code, and the spread signal is determined by majority logic by majority logic means, and the result of majority logic determination is output corresponding to the binary signal,
The modulating means modulates the carrier with the binarized signal and outputs a transmission signal. On the other hand, in the receiving unit, when the transmission signal output from the transmission unit is received, the transmission signal is demodulated by the demodulation unit using the PN code to obtain a data signal. In this way, the data signal can be multiplexed and communicated between the transmitting unit and the receiving unit.

Now, consider the case where the number of data channels is even. When the number of channels is even, the majority logic decision in majority logic means may have the same value, in which case, a predetermined signal among the above-described binarized signals is output by the same value detection means, The carrier is modulated with the signal by the modulation means, and the transmission signal is output. Then, in the receiving unit, the transmission signal is demodulated using the PN code in the same manner as described above to obtain a data signal.

The reason why the original data signal can be obtained by using a predetermined signal among the binarized signals when the result of the majority logic decision is the same is as follows. is there. That is, if the PN code used for the above spreading and despreading has a code sequence composed of, for example, “1” and “0”,
This is because they generally have the following properties.

(1) Balance, more specifically, 1 of a code sequence
The number of occurrences of “1” and the number of occurrences of “0” in the cycle are 1
The nature that only differs. (2) Continuousness, more specifically, the property that the number of appearances of “runs of ones” and the number of appearances of “runs of zeros” in one cycle of a code sequence are substantially equal.

That is, since the PN code has such a property, even when the majority logic decision becomes the same value and the majority logic decision result is not output, a predetermined signal is output, thereby allowing the original signal to be output. Can be obtained.

As described above, according to the communication apparatus using such a code division connection system, the multiplexing is performed by majority logic decision to satisfy the technical standard with the transmission power within the range specified by the Radio Law. And the number of data channels is not limited to an odd number,
That is, even if the number of data channels is even, data communication can be performed, and the degree of freedom of the system can be improved.

According to the second and third aspects of the present invention, in the same manner as the first aspect of the present invention, when a data signal is allocated to a plurality of data channels, the data signal is transmitted to the PN code by the spreading means. The spread signals are output in a spread-spectrum manner, and the spread signals are subjected to majority logic determination by majority logic means, and the majority logic determination result is output corresponding to two of the multi-valued signals and output by the modulation means. The carrier is modulated by the multi-level signal and the transmission signal is output. On the other hand, in the receiving unit, when the transmission signal output from the transmission side is received, the data signal is obtained by demodulation using the PN code by the demodulation means. In this way, the data signal can be multiplexed and communicated between the transmitting unit and the receiving unit.

At this time, a case is considered in which the number of data channels is even. In the case of the invention of claim 2,
If the number of channels is even and the majority logic decision by the majority logic means is the same, a predetermined signal of the binarized signal is output. A predetermined signal that is different from the one used for the majority logic decision result among the converted signals is output, and the modulation means modulates the carrier with the predetermined signal to output a transmission signal. That is, even if the number of channels is even and the majority logic decision is the same, the transmission side outputs a transmission signal modulated by a predetermined signal. Then, in the receiving section, the transmission signal is demodulated using the PN code based on the two multi-valued signals assigned to the majority logic decision by the demodulation means of the third aspect of the invention, and the original data signal is obtained.

As described above, according to the communication apparatus using such a code division connection system, the transmission power is specified by the Radio Law by multiplexing by majority decision logic judgment as in the first aspect of the invention. Within this range, technical standards can be satisfied, and even if the number of data channels is even, data communication can be performed, and the degree of freedom of the system can be improved.

According to the fourth aspect of the present invention, the receiving unit includes a PLL.
When a circuit is used, the transmission signal is not interrupted even if the majority logic decision is the same, so that the operation of the PLL circuit can be stabilized.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment according to the present invention will be described below with reference to FIG. First,
The transmitting device 30 of the communication system is configured as follows. N diffusers 311 to 31n as diffusion means
Are binary data signals D1 to Dn of “1” and “0” respectively assigned to a plurality of data channels.
And PN codes PN1 to PNn of a predetermined number of chips as a binary spreading code of “1” and “0” assigned differently for each of the data channels. Signals D1 to Dn are converted to PN code PN
The spread signals K1 to Kn are generated by spread modulation with 1 to PNn, and the spread signals K1 to Kn are output to a majority logic circuit 32 as majority logic means.

The majority logic circuit 32 is connected to the spreader 311
The spread signals K1 to Kn given from 31n to PN
The majority logic decision is made for each time slot corresponding to one chip of the code. Specifically, the number of “1” s in the time slot unit of the spread signals K1 to Kn provided from each data channel is “0”. When majority logic is determined to be greater than the number, majority signal M is output as "1",
When the majority logic is determined that the number of “1” is smaller than the number of “0”, the majority signal M is output to the conversion circuit 33 as the equivalence detecting means as “0”. When the majority logic circuit 32 determines that the number of “1” and the number of “0” of the spread signals K1 to Kn are equal, that is, they are the same value, the majority logic circuit 32 outputs the same value detection signal T to the conversion circuit 33. It has become.

The conversion circuit 33 includes the majority logic circuit 32
, A majority signal M and an equivalence detection signal T are given from the control signal. When the majority signal M is given, the majority signal M is output in that state. That is, when the majority signal M is given as "1", the " 1 "majority signal M
When the majority signal M is given as “0”, the majority signal M of “0” is output to the two-phase modulator 34 as the modulation means. Further, when the equivalent detection signal T is given, the conversion circuit 33 sets “1” equal to the majority signal M.
Alternatively, the equivalent signal N set to either “0” is output to the two-phase modulator 34.

The two-phase modulator 34 is connected to the conversion circuit 33
, A majority signal M and an equivalent signal N are given from the carrier wave f1 of a predetermined frequency outputted from the carrier wave generator 35.
Is phase-modulated by the majority signal M and the equivalent signal N to generate and output a transmission signal Sc of a wide band frequency. In this way, the transmitting device 30 is configured to multiplex the data signals D1 to Dn, modulate the phase, and output the multiplexed data signals.

On the other hand, the receiving device 40 that receives the transmission signal Sc output from the transmitting device 30 is configured as follows. The reproduction synchronous carrier generator 41 is supplied with the transmission signal Sc, and based on the transmission signal Sc, the above-described transmission signal Sc by the PLL circuit 42 therein.
Is generated and output to n spreaders 431 to 43n.

The spreaders 431 to 43n are connected to the transmitting device 3
PN codes PN1 to PNn used at 0 and the reproduced synchronous carrier f2 are given. The reproduced synchronous carrier f2 is spread by the PN codes PN1 to PNn to produce an intermediate signal Q.
1 to Qn are generated and output to n despreaders 441 to 44n.

The despreaders 441 to 44n receive the transmission signal Sc and the intermediate signals Q1 to Qn. The despreaders 441 to 44n despread the transmission signal Sc with the intermediate signals Q1 to Qn to convert the demodulated signals R1 to Rn. Generate a bandpass filter (BP
F) Output to 451 to 45n. The band-pass filters 451 to 45n remove the noise components by passing the given demodulated signals R1 to Rn through a predetermined pass frequency band to remove the original data signals D1 to Dn.
Is to be obtained. Thus, the receiving device 4
0 demodulates the transmission signal Sc output from the transmission device 30 to obtain the original data signals D1 to Dn. still,
The demodulation means of the present invention uses these reproduced synchronous carrier generators 4.
1, a PLL circuit 42, a spreader 43, a despreader 44, and bandpass filters 451 to 45n.

Next, the operation of the above configuration will be described.
When the data signals D1 to Dn are assigned to the respective data channels, the data signals D1 to Dn are
Spread signals K1 to Kn are output after being spread modulated by the PN codes PN1 to PNn at 11 to 31n. The spread signals K1 to Kn are determined by majority logic in the majority logic circuit 32 in units of time slots, and the number of “1” and the number of “0” of the spread signals K1 to Kn are different and the majority logic is determined. At times, the majority signal M is output as "1" or "0" according to the majority logic decision result.
Further, when the number of channels is even and the number of “1” and the number of “0” of the spread signals K1 to Kn are equal, that is, when they have the same value, the same value detection signal T is output.

When the majority signal M is output from the majority logic circuit 32, the majority signal M is output to the two-phase modulator 34 via the conversion circuit 33, and the carrier f1 output from the carrier generator 35 is output. Is phase-modulated by the majority signal M to generate and output a transmission signal Sc. On the other hand, when the equivalence detection signal T is output from the majority logic circuit 32, the equivalence signal N of “1” or “0” is output from the conversion circuit 33 to the two-phase modulator 34, and the carrier f1 is The transmission signal Sc is generated and output after being phase-modulated by the equivalent signal N.

As described above, in the transmitting device 30, when the majority logic decision is made, the majority signal M is set to "1".
Or, the carrier f1 is phase-modulated by "0" and the transmission signal S
c is output, and when the number of channels is even and equal, the carrier f1 is phase-modulated by the equivalent signal N set to either "1" or "0", and the transmission signal Sc is output.

Now, when the transmission signal Sc output from the transmission device 30 is received by the reception device 40,
The transmission signal Sc is supplied to the despreaders 441 to 44n and to the reproduction synchronous carrier generator 41. The reproduced synchronous carrier f synchronized with the transmission signal Sc by the PLL circuit 42 of the reproduced synchronous carrier generator 41.
2 is generated, and the reproduced synchronous carrier f2 is transmitted to the spreader 431.
Are spread by the PN codes PN1 to PNn, and intermediate signals Q1 to Qn are generated and output.

Next, the transmission signal Sc supplied to the despreaders 441 to 44n is despread by the intermediate signals Q1 to Qn to generate demodulated signals R1 to Rn, and the demodulated signal R
1 to Rn are passed through band pass filters 451 to 45n to a predetermined pass frequency band to remove noise components and obtain original data signals D1 to Dn. In this manner, the data signals D1 to Dn are transmitted to the majority logic circuit 32.
By performing majority logic determination, the transmission device 30 and the reception device 40 can multiplex and communicate with each other.

As described above, in the transmitting device 30, when the majority logic decision is the same and the majority logic circuit 32 does not output the majority signal M, it is not the majority signal M but either "1" or "0". The carrier signal f1 is phase-modulated by the set equivalent signal N to generate a transmission signal Sc, and the reception device 40 demodulates the transmission signal Sc to obtain the original data signals D1 to Dn. However, this is because the PN code as the spreading code has the properties described in "Means for Solving the Problem" described above.

As described above, according to the first embodiment, in the transmitting device 30, the data signals D1 to Dn are spread by the PN code, and the majority logic circuit 32 determines the majority logic to multiplex the data signals D1 to Dn. A transmission signal Sc is generated and output, and the receiving device 40 demultiplexes the transmission signal Sc by a PN code and demodulates the signal to obtain original data signals D1 to Dn.
In the communication system of the A system, when the majority logic decision is the same and the majority signal M is not output, the majority signal M is output based on the equivalent signal N set to either “1” or “0” of the majority signal M. Therefore, even if the number of data channels is even and the majority logic decision is the same, data communication can be performed satisfactorily.

That is, the transmission signal S is multiplexed by the majority logic decision using the majority decision logic circuit 32.
The technical standard can be satisfied by setting the transmission power of c within the range specified by the Radio Law, and the number of data channels is not limited to an odd number. Communication can be performed, and the degree of freedom of the system can be improved.

Also, even if the majority logic decision is the same,
Since the transmission signal Sc is output, the operation of the PLL circuit 42 of the reproduction synchronous carrier generator 41 can be stabilized in the receiving device 40.

Next, a second embodiment of the present invention will be described with reference to FIG. The first
The same parts as those in the embodiment are denoted by the same reference numerals, and the description thereof will be omitted.
Hereinafter, different parts will be described.

In the second embodiment, in the transmission device 50, the conversion circuit 51 is configured to output the converted signal I and the converted signal Q when the majority signal M and the equivalent detection signal T are given. Specifically, the conversion circuit 51
When the majority signal M is given as “1”, the conversion signal I
Is set to “1” and the conversion signal Q is set to “0”, the conversion signal IQ is output as “10”, and when the majority signal M is given as “0”, the conversion signal I is set to “0” and the conversion signal By setting Q to “1”, the conversion signal IQ
Is output to the four-phase modulator 52 as “01”. Further, the conversion circuit 51 receives the equivalence detection signal T,
By setting the conversion signal I to “0” and the conversion signal Q to “0”, the conversion signal IQ is output to the four-phase modulator 52 as “00”.

The four-phase modulator 52 converts the converted signal IQ
The carrier f1 having a predetermined frequency output from the carrier generator 35 is phase-modulated with the converted signal IQ to generate and output a transmission signal Sd having a wide band frequency. At this time, the phase of the transmission signal Sd is shifted by π / 4 with respect to the phase of the carrier f1. This is because, as described later, the transmission signal Sd generated by modulating the carrier f1 with the converted signal IQ “10” and “01” is demodulated, and the carrier f1 is converted with the converted signal IQ “00”.
This is for the purpose of preventing the transmission signal Sd generated by modulating.

On the other hand, in the receiving device 60, π
The / 4 shift reproduction synchronous carrier generator 61 is supplied with the transmission signal Sd, generates a reproduction synchronous carrier f2 synchronized with the transmission signal Sd by the PLL circuit 62 based on the transmission signal Sd, and generates n reproduced synchronization carriers f2. Diffusers 431-
43n.

In this case, the phase of the reproduction synchronous carrier f2 is
The phase of the transmission signal Sd generated by being modulated by “10” and “01” of the converted signal IQ by being shifted by π / 4 is equal to the phase of the transmission signal Sd, that is, as described above,
The transmission signal Sd generated by being modulated by “10” and “01” of the converted signal IQ is demodulated and “0” of the converted signal IQ.
The transmission signal Sd modulated by "0" is not demodulated. Thus, the receiving device 60
Are configured to obtain the data signals D1 to Dn by demodulating only the transmission signal Sd generated by modulating the converted signal IQ with “10” and “01”.

Next, the operation of the above configuration will be described.
When the data signals D1 to Dn are assigned to the respective data channels, the data signals D1 to Dn are
Spread signals K1 to Kn are output after being spread modulated by the PN codes PN1 to PNn at 11 to 31n. The spread signals K1 to Kn are determined by majority logic in the majority logic circuit 32 in units of time slots, and the number of “1” and the number of “0” of the spread signals K1 to Kn are different and the majority logic is determined. At times, the majority signal M is output as "1" or "0" according to the majority logic decision result.
Further, when the number of channels is even and the number of “1” and the number of “0” of the spread signals K1 to Kn are equal, that is, when they have the same value, the same value detection signal T is output.

When the majority signal M is output as "1" from the majority logic circuit 32, the conversion circuit 51
Output the conversion signal IQ as "10", and the majority signal M
Is output as "0", the conversion signal IQ is output from the conversion circuit 51 to the four-phase modulator 52 at "10". On the other hand, when the equivalence detection signal T is output from the majority logic circuit 32, the conversion signal IQ is “00” from the conversion circuit 51 and is output to the four-phase modulator 52.
Then, the carrier f1 output from the carrier generator 35 is phase-modulated with the converted signal IQ, and a transmission signal Sd is generated and output.

As described above, in the transmitting device 50, when the majority logic decision is made, the conversion signal IQ is set to “1”.
The carrier wave f1 is phase-modulated by "0" or "01" to output the transmission signal Sd. When the number of channels is even and equal, the carrier wave f1 is phase-modulated by "00" of the converted signal IQ and the transmission signal is transmitted. Sd is output.

Now, when the transmission signal Sd output from the transmission device 50 is received by the reception device 60,
The transmission signal Sd is provided to the despreaders 441 to 44n and to the π / 4 reproduced synchronous carrier generator 61. The PLL of the π / 4 reproduction synchronous carrier generator 61
A reproduced synchronous carrier f2 synchronized with the transmission signal Sd is generated by the circuit 62, and the reproduced synchronous carrier f2 is spread by PN codes PN1 to PNn in spreaders 431 to 43n to generate and output intermediate signals Q1 to Qn. You.

Next, the transmission signal Sd given to the despreaders 441 to 44n is despread by the intermediate signals Q1 to Qn to generate demodulated signals R1 to Rn.
1 to Rn are passed through band pass filters 451 to 45n to a predetermined pass frequency band to remove noise components and obtain original data signals D1 to Dn. In this manner, the data signals D1 to Dn are transmitted to the majority logic circuit 32.
By performing majority logic determination in the above, it is possible to multiplex and communicate between the transmitting device 50 and the receiving device 60.

At this time, as described above, the phase of the reproduction synchronous carrier f2 is changed to “10” and “0” of the modulation signal IQ.
By making the phase equal to the phase of the transmission signal Sd modulated and generated by “1”, “10” and “0”
Only the transmission signal Sd modulated and generated at "1" is demodulated, and the transmission signal Sd modulated and generated at "00" of the modulation signal IQ is not demodulated.
The original data signals D1 to Dn are obtained. In this case, the transmission signal Sd generated by modulating the modulated signal IQ with “00” is transmitted between the transmitting device 50 and the receiving device 60.
And serves as a signal for maintaining synchronization between the two.

As described above, according to the second embodiment, when the majority decision is not equivalent and the majority signal M is not output in the transmitting device 50, the conversion signal I corresponding to the majority signal M is output.
A transmission signal Sd phase-modulated based on the conversion signal IQ “00” different from Q “10” and “01” is generated and output, and the receiving device 60 converts the conversion signal corresponding to the majority signal M. Since only the transmission signal Sd phase-modulated based on IQ “10” and “01” is demodulated to obtain the original data signals D1 to Dn,
Even if the number of data channels is even and the majority logic decision is the same, data communication can be performed.

That is, the transmission signal S is multiplexed by the majority logic decision using the majority
The transmission power of d can be within the range specified by the Radio Law to satisfy the technical standards. Further, even if the number of data channels is even, data communication can be performed, and the degree of freedom of the system can be improved. become able to.

In order to confirm that even if the number of data channels is set to an even number in the first embodiment and the second embodiment described above, the inventors do not interfere with data communication. An experiment like the one obtained the confirmation. Hereinafter, the experimental systems and the experimental results will be described with reference to FIGS. Hereinafter, the experiment corresponding to the first embodiment is referred to as “equivalent signal limiting method”, and the experiment corresponding to the second embodiment is referred to as “π / 4 shift PS”.
Equivalent carrier suppression method by K demodulation ".

First, the configuration of the experimental system of this experiment is shown in FIG.
Is shown in As is clear from FIG. 3, the experimental system of this experiment is basically the same as the configuration described in the second embodiment, and the number of data channels is set to a maximum of 15 (n = 15). And we have two schemes,
That is, the equivalent signal limiting system and the equivalent carrier suppression system based on π / 4 shift PSK demodulation are used in the conversion circuit 5 of the transmitting apparatus 50.
The experiment was performed by one experimental system shown in FIG.

Now, the majority logic circuit 32 employed in the experimental system will be described in detail. Majority logic circuit 3
2, comprises a gate switch 32a, an adding circuit 32b, a threshold 4-bit switch 32c, and a 4-bit comparator 32d, as shown in FIG.

The gate switch 32a receives the data signal D1
To D15 are spread by PN codes PN1 to PN15 to generate spread signals K1 to K15, respectively.
This switch selects whether or not to output the data channel 2b, that is, the number of data channels is selected from 1 to 15 by the gate switch 32a.

The adder circuit 32b is composed of a 15-bit input and a 4-bit output, and outputs the number of data signals "1" as a binary 4-bit signal A in accordance with a 15-bit input state corresponding to each data channel. It has become.
Specifically, the adder circuit 32b determines that the number of data signals “1” to be assigned is 0 to 15 if the channel is 15-channel multiplexing. For example, if no data signal “1” is assigned, the 4-bit signal A is output as “0000” indicating that there are 0 data signals “1”, and if the data signal “1” is allocated to all 15 channels, the 4-bit signal A is It is output to the 4-bit comparator 32d as "1111" indicating that there is.

Threshold 4-bit switch 32c
Sets a threshold level according to the number of multiplexed channels, and outputs the threshold level as a 4-bit signal B to a 4-bit comparator 32d.
At this time, if the number of channels is an odd number, the threshold level is set with a 4-bit signal B of [(multiplex number-1) / 2].
111 ". If the number of channels is even,
(Multiplex / 2) 4-bit signal B, for example, 1
In the case of 0 multiplexing, the 4-bit signal B is "0101".

The 4-bit comparator 32d outputs a 4-bit signal A output from the adder circuit 32b and a 4-bit signal B output from the threshold 4-bit switch 32c.
And outputs the comparison result. Specifically, when the 4-bit signal A is smaller than the 4-bit signal B, the 4-bit comparator 32d determines that the number of data signals "1" is smaller than the number of data signals "0" in majority logic judgment. Signal M is "0"
At this time, the equivalent value detection signal T is output as “0” indicating that it is not the same value. When the 4-bit signal A is larger than the 4-bit signal B, the number of data signals “1” is reduced to “0” in the majority logic decision.
Therefore, the majority signal M is output as "1", and also at this time, the equivalent detection signal T is output as "0" indicating that it is not the same value.

On the other hand, when the 4-bit signal A is equal to the 4-bit signal B, it means that the number of data signals "1" and the number of data signals "0" are equal in the majority logic decision. The signal T is output as "1", and the majority signal M is output as "0" indicating that the majority logic decision was not made. That is, the majority logic circuit 32 outputs the comparison result of the 4-bit comparator 32d to the conversion circuit 51 in three patterns “00”, “10”, and “01” by combining the majority signal M and the equivalent detection signal T. Things.

As described above, the conversion circuit 51 has two methods, namely, an equivalent signal limiting method and a π / 4 shift PSK.
The output of the converted signal IQ is different between the demodulation and the equivalent carrier suppression system. FIG.
(A) shows a case of an equivalent signal limiting system, and (b) shows a case of an equivalent carrier suppression system by π / 4 shift PSK demodulation. In the equivalent signal limiting method of (a), the output when the value becomes the same is
The setting is made so as to be equal to the case where the majority decision result is “0”.

That is, in the equivalent signal limiting method,
For input of “00”, “10” and “01”, “0”
The output is "1", "10", or "01". In other words, the majority logic signal M becomes "0" and the equivalence detection signal T becomes "0" when the majority logic signal is determined, and the majority logic signal M becomes "0" and the equivalence detection signal T without the majority logic decision. The output of the conversion circuit 51 becomes equal to “1”, and if the majority logic decision is not made, the majority signal M is processed as “0”. In this way, the conversion signal IQ output when the majority is determined by the majority logic determination is set to one of the conversion signals IQ output when the majority logic determination is performed. It operates in the same manner as in the first embodiment.

On the other hand, in the equivalent carrier suppression method by π / 4 shift PSK demodulation, “00”, “1”
For input of “0” and “01”, different “0”
Outputs are "1", "10", and "00". In this way, the converted signal IQ output when the majority is determined to have the same value is different from the converted signal IQ output when the majority logic is determined. It works in the same way as. still,
Here, "11" is not adopted as the output.

As described above, the four-phase phase modulator 52 modulates the phase of the carrier f1 output from the carrier generator 35 with the conversion signal IQ supplied from the conversion circuit 51. Here, how the four-phase modulator 52 operates in the equivalent signal limiting system and the equivalent carrier suppression system based on π / 4 shift PSK demodulation will be described.

First, in the equivalent signal limiting method, as described above, the two values of “01” and “10” are four as the converted signal IQ.
Since the signals are input to the phase phase modulator 52, the four-phase phase modulator 52 acts to phase-modulate the carrier wave f1 in binary. On the other hand, π / 4 shift PS
In the equivalent carrier suppression method by K demodulation, as described above, three converted signals IQ of “01”, “10”, and “00” are used.
Since the value is input to the four-phase modulator 52,
The four-phase modulator 52 is different from the equivalent signal limiting system,
This acts to phase-modulate the carrier wave f1 in three values.

At this time, in both of the equivalent signal limiting system and the equivalent carrier suppression system based on π / 4 shift PSK demodulation, as shown in FIG. Sd is shifted by π / 4 with respect to the carrier wave f1. That is, in the equivalent signal limiting method, “01” of the converted signal IQ is 3 with respect to the carrier f1.
π / 4 shifted, and “10” is 7π with respect to the carrier f1.
/ 4 shift. Also, π / 4 shift PS
In the equivalent carrier suppression method by K demodulation, “00” of the converted signal IQ is shifted by π / 4 with respect to the carrier f1, and “0”
“1” is shifted by 3π / 4 with respect to the carrier f1, and “1”
“0” will be shifted by 7π / 4 with respect to the carrier f1.

This is to prevent the transmission signal Sd generated by modulating the carrier f1 with the converted signal IQ “00” in the equivalent carrier suppression system based on π / 4 shift PSK demodulation from being demodulated. It is for this reason that the apparatus 60 uses the π / 4 shift regenerative synchronous carrier generator 61 to generate the regenerative synchronous carrier f2. That is, the π / 4 shift reproduction synchronous carrier generator 6
1 is synchronized with the phases of 3π / 4 and 7π / 4, the transmission signal Sd modulated by the converted signal IQ “01” and “10” is demodulated, and the converted signal IQ The transmission signal Sd modulated by “00” can be prevented from being demodulated.

As is apparent from the above description, the experimental system having the above-described configuration allows the equivalent signal limiting system and the equivalent carrier suppression system based on the π / 4 shift PSK demodulation only by changing the conversion circuit 51. Can be performed by one experimental system. In implementation, the equivalent carrier suppression method can also be performed by a two-phase modulation method.

Next, the main specifications of this experiment are shown below.

[Table 1]

As described above, the PN code in this experiment is the longest connection tap [2, 3,
[4,8], having a code length of 255 chips. FIG. 7 shows a code sequence of the PN code. Note that the code sequence shown in FIG. 7 corresponds to PN1,
2 is one chip shifted from PN1, PN3 is PN
PN1 to PN1
PNn is shifted one chip sequentially.

Next, the experimental results of such an experiment will be described with reference to FIGS. First, the relationship between the carrier power and the error rate due to the change in the number n of multiplexed data channels will be described with reference to FIGS.

First, the multiplex number n in the equivalent signal limiting system
8 and 9 which show the relationship between the carrier power and the error rate due to the change in the multiplex number, even if the multiplex number n is an even number, communication is performed with the same error rate as when the multiplex number n is an odd number in the equivalent signal limiting method. You can see what you can do. Also, it can be seen that there is a general tendency that the error rate increases as the multiplex number n increases with the same carrier power.

FIG. 10 and FIG. 11 show the relationship between the carrier power and the error rate due to the change in the number of multiplexes n in the equivalent carrier suppression system based on π / 4 shift PSK demodulation.
It can be seen that, even in the equivalent carrier suppression system based on the 4-shift PSK demodulation, even when the multiplex number n is an even number, communication can be performed with the same error rate as when the multiplex number n is an odd number, as in the equivalent signal limiting system.

Now, the present inventors performed computer simulations on how the correlation level changes depending on the number n of multiplexes for each of the equivalent signal limiting system and the equivalent carrier suppression system based on π / 4 shift PSK demodulation. went. Hereinafter, the procedure and results of the simulation will be described with reference to FIGS.

FIG. 12 and FIG. 13 show the procedure of the simulation. First, as preparation for simulation, a PN code (PN code) shown in the above-mentioned main specifications is generated by a PN code generator (step S).
1) The file of the PN code was output (step S2).

In the simulation, first, a PN code file was input (step T1), and PN1 to PN15 were generated by sequentially shifting the PN code by one chip (step T2). Then, the multiplexing number n of the data channel was initially set to two multiplexing (step T3), and measurement was performed (steps T4 and T5). Next, the correlation level obtained by the measurement was output (step T6), the multiplex number n was increased by 1 (step T7), and measurement was performed up to 15 multiplexes (step T8).

FIG. 14 and FIG. 15 show simulation results obtained by this simulation. First, from FIG. 14 showing a simulation result in the equivalent signal limiting method, the same signal limiting method shows the same tendency in both the even multiplexing and the odd multiplexing, and the correlation value converges as the multiplexing number increases. I understand.

Further, from FIG. 15 showing a simulation result in the equivalent carrier suppression method using the π / 4 shift PSK demodulation, the case of the odd number multiplexing and the even number multiplexing are different in the equivalent carrier suppression method using the π / 4 shift PSK demodulation. It turns out that it shows a tendency.

As described above, according to the present experiment, the data channel of both the equivalent signal limiting method according to claim 1 and the equivalent carrier suppression method by π / 4 shift PSK demodulation according to claim 2 are used. Multiplex number n
It can be seen that even if is an even number, data communication can be performed as in the case of an odd number, that is, the degree of freedom of the system can be improved.

The present invention is not limited to the above embodiment, but can be modified or expanded as follows. When demodulating the data signals D1 to Dn, the transmission signal is despread by the PN codes PN1 to PNn, and the signal obtained by despreading is demodulated by the reproduction synchronous carrier f2 to obtain the original data signal D1 to Dn. Dn may be obtained.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a view corresponding to FIG. 1 showing a second embodiment of the present invention.

FIG. 3 is a diagram corresponding to FIG. 1 showing an experimental system.

FIG. 4 is a block diagram showing a configuration of a majority logic circuit;

FIG. 5 is a diagram showing correspondence between input and output signals of a conversion circuit;

FIG. 6 is a diagram showing a relationship between a converted signal and a phase.

FIG. 7 is a diagram showing one code sequence of a PN code;

FIG. 8 is a diagram showing a relationship between carrier power and error rate in odd-number multiplexing of the equivalent signal limiting method.

FIG. 9 is a diagram corresponding to FIG. 8 in the even number multiplexing of the equivalent signal limiting method.

FIG. 10 is a diagram corresponding to FIG. 8 in the odd-number multiplexing of the equivalent carrier suppression system by π / 4 shift PSK demodulation;

FIG. 11 is a diagram corresponding to FIG. 8 in the even multiplexing of the equivalent carrier suppression system by π / 4 shift PSK demodulation;

FIG. 12 is a flowchart showing a simulation preparation procedure;

FIG. 13 is a flowchart showing a simulation procedure;

FIG. 14 is a diagram showing the relationship between the number of multiplexes and the correlation level in the equivalent signal limiting system.

FIG. 15 is a diagram corresponding to FIG. 14 in the equivalent carrier suppression system by π / 4 shift PSK demodulation;

FIG. 16 is a diagram corresponding to FIG. 1 showing a conventional example.

FIG. 17 is a diagram corresponding to FIG. 1, showing another conventional example.

[Explanation of symbols]

In the drawing, 311 to 31n are spreaders (spreading means), 32 is a majority logic circuit (majority logic means), 33 is a conversion circuit (equivalence detection means), 34 is a two-phase modulator (modulation means), and 41 is reproduction. Synchronous carrier generator (demodulation means), 42
Is a PLL circuit (demodulation means), 431 to 43n are spreaders (demodulation means), 441 to 44n are despreaders (demodulation means), 451 to 45n are band-pass filters (demodulation means), and 51 is a conversion circuit (equivalence detection). Means, 52 are four-phase phase modulators (modulation means).

Claims (4)

[Claims] 1. A spreading means for spreading and modulating a data signal with a different PN code corresponding to each of a plurality of data channels and outputting a spread signal for each data channel to a transmitting unit, and an output signal from the spreading means. Majority logic means for performing a majority logic decision on a plurality of spread signals in units of time slots and outputting the majority logic decision result in association with a binarized signal; and the binary signal output from the majority logic means. And a modulating means for modulating a predetermined carrier wave to output a transmission signal, and receiving a transmission signal output from the transmission unit at a receiving unit, demodulating the signal using the PN code to obtain the data signal. In a communication device using a code division multiple access system having a configuration provided with a demodulation means, the transmitting section has the same value as a majority logic decision in the majority logic means, and When the decision logic decision result is not output, the decision means comprises an equivalence detection means for detecting the binary decision signal and outputting a predetermined signal among the binarized signals, wherein the modulation means determines the majority logic decision result from the majority decision logic means. A communication apparatus using a code division multiple access system, wherein modulation is performed by a binary signal output from the equivalence detection means when no is output. 2. A spreading means for spreading and modulating a data signal with a different PN code corresponding to each of a plurality of data channels and outputting a spread signal for each of the data channels to a transmitting unit, and a signal output from the spreading means. Majority logic means for determining a plurality of spread signals in a time slot unit and outputting the result of the majority logic decision in correspondence with two of the multi-valued signals, and output from the majority logic means. Modulating means for modulating a predetermined carrier with the multi-level signal and outputting a transmission signal, and a receiving unit,
In a communication apparatus using a code division multiple access system having a configuration including a demodulation unit that receives the transmission signal output from the transmission unit and demodulates using the PN code to obtain the data signal, the transmission unit includes: A predetermined signal different from that used for the majority logic decision result among the multi-valued signals, when the majority logic decision means does not output the majority logic decision result as being equivalent to the majority logic decision. The modulation means is configured to perform modulation by a multi-level signal output from the equivalence detection means when the majority logic means does not output a majority logic decision result. A communication device using a code division multiple access system characterized by the following. 3. The demodulation means receives the transmission signal and obtains the data signal based on the two multi-valued signals assigned to the majority logic decision when demodulating using the PN code. 3. The communication device according to claim 2, wherein the communication device is configured. 4. The code division multiple access system according to claim 1, wherein the receiving unit is provided with a PLL circuit for generating a reproduced synchronous carrier synchronized with the transmission signal. Communication device.