JPH1022809A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a malfunction due to an output simultaneous operation, without deteriorating the circuit characteristics and not attended with decrease in number of signal terminals due to the addition of power and GND terminals by controlling an output impedance of a plurality of circuits, based on the result of detection of an output simultaneous operation detection means. SOLUTION: A circuit 1 is provided with an output impedance control circuit 2 for a rising state of the circuit 1 and an output impedance control circuit 3 for a falling state of the circuit 1. An output simultaneous operation detection circuit 4 detects an output simultaneous operation of circuits 1,5-8. The output of the circuit 4 connects to the output impedance control circuit 2, 3 of the circuit 1 and the circuits 5-8. Then the circuit 4 actually detects a state of production of the output simultaneous operation and increases the output impedance for noise reduction. Thus, when no output simultaneous operation is generated, the integrated circuit realizes a characteristic without any change from that in the usual circuit state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a circuit for reducing noise during simultaneous output operation in which output signals of a plurality of circuits simultaneously transition in the same direction.

[0002]

2. Description of the Related Art In recent years, the number of input / output signals has been dramatically increased due to high integration of semiconductor integrated circuits. As a result, the output signal simultaneously changes in the same direction, that is, the number of simultaneous output operations has been increasing, but countermeasures such as those described below have been taken against malfunctions caused by noise caused by this simultaneous output operation. Has been taken.

First, as a first prior art, a power supply terminal or a GND terminal is further added (the number of terminals is increased). Malfunctions due to simultaneous output operation can be caused by the simultaneous output operation from the power supply potential to the output terminal or from the output terminal to GND.
A voltage drop or a potential change due to a transient current flowing to the potential causes a malfunction of an input circuit in the same integrated circuit or a malfunction of an input circuit of another integrated circuit connected to the next stage.

For example, assuming that the sum of the inductance and the series resistance of the GND terminal is L and R, respectively, and the sum of the DC current flowing through the GND terminal at a certain time in a transient state is i, the potential fluctuation ΔV is It is represented by equation (1).

[0005]

(Equation 1)

Therefore, by adding the GND terminal, the inductance L and the resistance R are reduced, and the potential variation ΔV is reduced.

A second prior art is disclosed in, for example,
Japanese Patent Application Laid-Open No. 130920/130 discloses an output signal which is equivalently regarded as an output simultaneous operation by shifting the timing of an input signal input to an output circuit which operates simultaneously with an output in advance, as schematically shown in FIG. Have been proposed to reduce the number of lines. That is, the publication discloses that a capacitor (capacitance value is C1 <C
2 <C3), the input timing of the next-stage circuit is made different, the simultaneous output to the next-stage circuit is avoided, and the transient current flowing through the power supply line is controlled.

As a third prior art, for example, Japanese Unexamined Patent Publication No. 1-119051 discloses a circuit in which circuit constants and terminals used in output circuits which operate simultaneously are changed in advance as shown in FIG. In addition, a method has been proposed in which not only the timing of the simultaneous output operation but also the mutual conductance gm is changed to suppress noise generated by the simultaneous output operation. In this case, by utilizing the property that the gm of the MOS transistor greatly depends on how to open the contacts in the source / drain regions, the contact opening method shown in FIGS. A configuration applied to a gate array system in which the subsequent process is an upper layer process is described.

[0009]

The above-mentioned prior art has the following problems.

First, in the first prior art, since a power supply terminal and a GND terminal are added, the number of terminals that can be used as signal terminals is reduced (conversely, the number of terminals increases unless the number of signal terminals is reduced). There is a problem. That is, the power supply terminal is used for simultaneous output operation from low level to high level, and GN is used for simultaneous operation from high level to low level.
Since each of the D terminals must be added, a large number of power supply terminals and GND terminals are added as a countermeasure for simultaneous output operation, and there is a problem that the number of signal terminals is significantly reduced.

In the second prior art, since the timing of the input signal is changed in advance, it is difficult to adjust the time for the change, and the changed timing makes it difficult to design the integrated circuit connected to the next stage. However, there is a problem that it becomes more difficult.

Further, in the third prior art, since the generation of noise is suppressed by lowering the performance of the circuit, there is a possibility that the highest performance of the circuit itself cannot be applied (or realized). Was.

[0013] Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to reduce the number of signal terminals by adding power supply terminals and GND terminals without lowering circuit characteristics. Another object of the present invention is to provide a semiconductor integrated circuit in which a malfunction due to simultaneous output operation is prevented.

[0014]

In order to achieve the above-mentioned object, a semiconductor integrated circuit according to the present invention comprises a plurality of circuits which output signals simultaneously transition from a high level to a low level or from a low level to a high level. In operation, the output simultaneous operation detecting means for detecting that an input signal of the plurality of circuits has transitioned from a high level to a low level or from a low level to a high level, based on a detection result of the output simultaneous operation detecting means, Output impedance control means for controlling the output impedance of the plurality of circuits.

Further, in the present invention, the output impedance control means in the semiconductor integrated circuit includes an N-channel MO connected in series between a higher power supply and a lower power supply.
A plurality of parallel-connected N-channel MOS transistors and a plurality of P-channel MOS transistors are connected in series between respective drain terminals of the S-transistor and the P-channel MOS transistor.
The gate terminals of the S transistor group and the P channel MOS transistor group are connected to respective outputs of the output simultaneous operation detecting means.

Further, the present invention is characterized in that the output simultaneous operation detecting means detects the simultaneous output operation of the plurality of circuits in synchronization with a clock signal in a synchronous circuit.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of the first exemplary embodiment of the present invention. In the figure, circuits 1, 5,
Reference numerals 6, 7, and 8 denote circuit groups that operate simultaneously with output. The circuit 1 also includes an output impedance control circuit 2 when the circuit 1 rises and an output impedance control circuit 3 when the circuit 1 falls, and a gate is provided between the power supply terminal and the output impedance control circuit 2. Is connected to a P-channel MOS transistor MP0 having a signal IN0 as an input, and an N-channel MOS transistor MN0 having a gate inputted with a signal IN0 is connected between the output impedance control circuit 3 and a ground terminal. Circuit 2
And 3 are connected to the output terminal OUT0. In the figure, reference numeral 4 denotes an output simultaneous operation detection circuit for detecting the simultaneous output operation of the circuits 1, 5, 6, 7, and 8, and its output is connected to the output impedance control circuits 2 and 3 of each circuit. Note that the configuration of the circuits 5, 6, 7, and 8 is the same as that of the circuit 1, and therefore only the configuration of the circuit 1 is shown in FIG.

FIG. 2 shows an output impedance control circuit 2,
3 shows a specific circuit configuration of the synchronous output circuit 3 and the output simultaneous operation detection circuit 4 using a clock signal in a synchronous circuit. Note that IN0 to INn in FIG. 2 indicate input signals of an output circuit group that operates simultaneously with output.

The operation of the embodiment of the present invention will be described with reference to FIG.

First, a description will be given of a case where the output signals from the input signals IN0 to INn to the output circuit group are simultaneously output from the high level to the low level.

FIG. 3 is a timing chart in this case. Immediately before the output simultaneous operation occurs, that is, one cycle before the clock signal 17, since IN0 to INn are all at a high level, the nodes (nodes) 35 and 36 are at a high level, and the node B is also at a high level ( Time a) in FIG.

Therefore, N channel MOS transistor 2
4 is ON, the output impedance at the time of falling is represented by the ON resistance of the N-channel MOS transistor as follows. That is, the on-resistance of the N-channel MOS transistor 22 is set to Ron22 and the N-channel
Assuming that the on-resistance of the S transistor 24 is Ron24 and the on-resistance of the N-channel MOS transistor 26 is Ron26, the on-resistance Rfall at the fall is Ron2.
Ron 22 is connected in series to the parallel connection of Ron 4 and Ron 26 and is represented by the following equation (2).

[0023]

(Equation 2)

In FIG. 3, the portion indicated as Rfall corresponds to the above state.

Here, it is assumed that IN0 to INn have transitioned from a high level to a low level in synchronization with the clock signal 17.

First, by the edge of the clock signal 17,
The data of the node 36 in the immediately preceding state, that is, the high level is taken into the flip-flop 33 and output to the node 38. In this case, the node 38 becomes the low level (time b in FIG. 3).
And the portions indicated by arrows from nodes 36 to 38).

Thereafter, the data of IN0 to INn is ORed.
When reaching the gate 31 and the AND gate 32, the node 35
Becomes low level, the level of the node B also becomes low level (time c in FIG. 3), and the N-channel MOS transistor 2
4 is turned off, and the on-resistance Rfall ′ at the fall is
It is expressed by the following equation (3).

Rfall ′ = Ron22 + Ron26 (3)

In FIG. 3, the portion indicated by Rfall 'corresponds to the above state. Therefore, the on-resistance at the falling time, that is, the output impedance becomes larger than one cycle before (Rfall ′> Rfall), and the transiently generated noise is suppressed.

On the other hand, if the simultaneous output operation does not occur, that is, if all of IN0 to INn are not low, O
Since the output node 35 of the R gate 31 is always at the high level (after time d in FIG. 6), the node B is always at the high level, and the N-channel MOS transistor 24 is turned on. One cycle before the occurrence, that is, the same value as Rfall is maintained.

Next, a case will be described in which IN0 to INn perform a simultaneous output operation from a low level to a high level.
The timing chart in this case is basically as shown in FIG.
Are omitted because they are equivalent to those shown in FIG.

Immediately before the simultaneous output operation occurs, that is, one cycle before the clock signal 17, IN0 to IN0
Since n is all low, nodes 15 and 16 are low, and therefore node A is also low. As a result, the P-channel MOS transistor 23 is turned on, and the output impedance at the time of rising is represented by the on-resistance of the P-channel MOS transistor as follows. That is, the on-resistance of the P-channel MOS transistor 21 is set to Ron21,
Assuming that the on-resistance of No. 3 is Ron23 and the on-resistance of the P-channel MOS transistor 25 is Ron25, the on-resistance Rrise at the time of rising is expressed by the following equation (4).

[0033]

(Equation 3)

Here, it is assumed that IN0 to INn transition from a low level to a high level in synchronization with the clock signal 17. First, at the edge of the clock signal 17, the data at the node 16 in the immediately preceding state, that is, the low level is taken into the flip-flop 13 and output to the node 18, where the node 18 is at the low level. Then, from IN0 to I
When the data of Nn reaches the gates 11 and 12, the node 15 goes high, the level of the node A also goes high, the P-channel MOS transistor 23 is turned off, and the on-resistance Rrise 'at the time of rising is expressed by the following equation. (5).

Rise ′ = Ron21 + Ron25 (5)

Accordingly, the on-resistance at the rise, that is, the output impedance becomes larger than one cycle before (R
rise ′> Rise), the noise generated transiently is suppressed.

On the other hand, if the simultaneous output operation does not occur, that is, if all of IN0 to INn are not at the high level, the node A is always at the low level because the node 15 is always at the high level, and the P-channel MOS transistor 23 is turned on. , The output impedance at the time of rising is maintained one cycle before the simultaneous output operation occurs, that is, the same value as Rrise.

FIG. 4 shows a second embodiment of the present invention. In the present embodiment, two types of output simultaneous operation detection circuits 41 and 42 and an output impedance control circuit are prepared, and the output impedance is changed in two ways according to the number of simultaneous output operations. Pch transistors MP1 and MP2 are connected in parallel with Pch transistor MP4, and N
N-channel transistor M in parallel with channel transistor MN4
N1 and MN2 are connected. Although this embodiment shows two cases, the output impedance can be changed in accordance with the number of simultaneous output operations by increasing the number of output simultaneous operation detection circuits and the number of output impedance control circuits. .

[0039]

As described above, in the prior art, a countermeasure against malfunction due to noise caused by simultaneous output operation was realized by adding a power supply terminal and a GND terminal. For example, noise can be reduced without adding a power supply terminal or a GND terminal. Conventionally, measures to reduce the performance of the circuit have been applied in advance in order to suppress the occurrence of noise. However, according to the present invention, a state in which simultaneous output operation occurs is detected, and the state is detected. Only in the case of the above, since the value of the output impedance for reducing the noise is increased, when the simultaneous output operation does not occur, there is an advantage that the characteristics which are not different from the ordinary circuit can be realized. .

Further, according to the present invention, it is possible to change the value of the output impedance to several types in accordance with the number of simultaneous output operations, and the present invention has expandability to various operation states.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of a first embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the first exemplary embodiment of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional technique.

FIG. 6 is a diagram showing a configuration of another conventional technique.

[Explanation of symbols]

 1, 5, 6, 7, 8 output circuit 2, 3 output impedance control circuit 4 output simultaneous operation detection circuit 11 AND gate 12 OR gate 13 flip-flop 14 AND gate 15, 16 node 21, 23, 25 P-channel MOS transistor 22 , 24, 26 N-channel MOS transistors 41, 42 Simultaneous output detection circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04L 25/02

Claims (3)

[Claims] An output signal of a plurality of circuits in a semiconductor integrated circuit transitions from a high level to a low level or from a low level to a high level. In the simultaneous output operation, the input signals of the plurality of circuits are changed from a high level to a low level. To, or to detect that the transition from low level to high level, output simultaneous operation detection means, and to control the output impedance of the plurality of circuits based on the detection result of the output simultaneous operation detection means, output impedance control means, A semiconductor integrated circuit comprising: A plurality of output impedance control means connected in parallel between a drain terminal of an N-channel MOS transistor and a P-channel MOS transistor connected in series between a higher power supply and a lower power supply; N-channel MOS transistor group and P-channel M
2. An OS transistor group is connected in series, and gate terminals of the N-channel MOS transistor group and the P-channel MOS transistor group are respectively connected to an output of the output simultaneous operation detecting means. A semiconductor integrated circuit as described in the above. 3. The semiconductor integrated circuit according to claim 1, wherein said simultaneous output operation detecting means detects the simultaneous output operation of said plurality of circuits in synchronization with a clock signal in a synchronous circuit.