JPH10227824A - Schedule processor for wire assembly and assembly side unit used therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a schedule processing for a wire assembly in real time by serial communication. SOLUTION: An assembly side unit 30 connected to a wire assembly WA is connected to a master unit 20 for controlling the assembly side unit 30 by a serial communication line 14. The individual units 20 and 30 and the serial signal line 14 are connected to common memories 45 and 46 respectively installed on the units 20 and 30. The common memories 45 and 46 are updated so that data received and transmitted through the serial signal communication line 14 become the same. With such an arrangement, the updating of the common memories 45 and 46 enables the contents of the data to coincide between the transmitting side unit and the receiving side unit thereby letting the units 20 and 30 accomplish various processing in parallel with the reception and transmission of the data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a process apparatus for a wire assembly and an assembly unit used for the apparatus.

[0002]

2. Description of the Related Art Generally, a wire harness and a subassembly (hereinafter, collectively referred to as a "wire assembly") constituting the wire harness are an electric wiring system forming a plurality of electric circuits, and include a large number of electric wires forming signal lines. And a connector connected to the electric wire. As one aspect of such a wire assembly process,
For example, JP-A-6-258371 discloses that a master unit and a connector unit are connected by a serial signal line and a connector unit is connected to a connector of a wire assembly to be processed in order to reduce a search time in a continuity test. In addition, an apparatus is disclosed in which an inspection command is issued from a master unit to a connector unit by serial communication, and based on an inspection signal of a wire assembly detected from the connector unit, whether conduction is good or not is disclosed.

[0003]

In the above-described apparatus, communication control between the master unit and the connector unit is exclusively performed by the CPU provided in each unit. For this communication process, for example, 30μ per byte
S processing time is required. Therefore, as in the continuity test,
When reading and processing data of several thousand terminals (hundreds of bytes) for a signal from one terminal, the inspection of only one terminal results in a delay of several milliseconds, and when the total number of terminals is relatively small (for example, 1000) ), A delay of a few seconds.
Moreover, in recent years, the number of terminals of the wire assembly has tended to increase, and usually, the number of terminals reaches several thousand (hundreds of bytes). Therefore, in many cases, the CPU
The wire assembly could not be processed in real time.

However, the necessity of processing a wire assembly in real time has been increasing rapidly in recent years for the purpose of performing inspection in parallel with the work and eliminating an independent inspection process, and an improvement thereof has been demanded. The present invention has been made in view of the above problems, and has as its object to provide a wire assembly process processing apparatus capable of performing wire assembly process processing in real time by serial communication, and an assembly-side unit used for the same. .

[0005]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides an assembly-side unit having a communication function and being connectable to a wire assembly via a connector of the wire assembly. And a serial communication unit communicably connected to the master unit and the assembly side unit, and based on an instruction signal output from the master unit, a signal line of the wire assembly set to the instruction signal By performing the reception and transmission of the signal from the assembly side unit, while performing a predetermined process, a wire assembly process processing device capable of transmitting a processing result signal indicating the result of the executed processing to the master unit, Each of the above master unit and assembly side unit Vignetting, it is a process apparatus of the wire assembly, characterized in that the serial signal line receiving and transmitting data via is provided a shared memory to be updated to the same.

[0006] In the invention including this specific matter, serial communication is performed between the master unit and the assembly-side unit, and various process processes such as a continuity test are performed through data transmission and reception. At this time, the shared memory is updated by the data transmission / reception performed for performing the process processing, and the contents of the data match between the transmitting unit and the receiving unit. As a result, each unit
Various processes can be performed in parallel with data transmission and reception. As the serial communication means, it is possible to use an optical cable or a radio as well as an electric signal line.

Another aspect of the present invention is an assembly-side unit employed in the above-described wire assembly process processing apparatus, wherein each of the wire assemblies to be processed increases or decreases in accordance with the number of circuits of the wire assembly. Possible I /
An assembly-side unit having a building block configuration having an O port portion. In the invention including this specific matter, the number of I / O ports can be increased or decreased according to the type of the wire assembly to be processed, so that the installation state can be optimized.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
A preferred embodiment of the present invention will be described. FIG. 1 is a block diagram of a process apparatus according to an embodiment of the present invention. With reference to FIG.
The master unit 20 and the assembly-side unit 30 are provided, and are connected by, for example, a twisted pair cable, an optical communication cable, or a wireless serial signal line 14.
The master unit 20 and the assembly unit 30 are communicably connected to each other to form a time-division serial transmission system.

[0009] The wire assembly WA to be processed
Is an electric wiring system in which a predetermined circuit is constituted by a plurality of signal lines W bundled in a harness and a connector C connected to each signal line W. A terminal fitting T to which the wire W is connected is included. In the illustrated example, the electronic unit U is connected to a specific signal line W and is included in the circuit.
The electronic unit has a built-in controller U1 including a CPU.
Various programs are stored. Controller U1
Include a self-diagnosis program and a specification determination program that can be started by a predetermined signal.

[0010] The master unit 20 is embodied by a personal computer.
An operation unit 22 such as a keyboard connected to the PU 21 and the CPU 21, a display unit 23, and a local memory 24 are provided. The local memory 24 stores processing data (wire numbers, pins, types of electronic units connected to the wire assembly WA, etc.) of the wire assembly WA for each product number of the wire assembly WA to be processed. ) And information including a plurality of processing programs.

On the other hand, the assembly side unit 30 also has a CP.
U32 is included, and a local memory 33 and a plurality of I / O blocks 34 are connected to the CPU 32. The local memory 33 stores programs, data, and the like for controlling the CPU 32.

The I / O block 34 has a so-called building block structure. Specifically, a plurality of I / O ports are formed as a unit on a board, and a case also serving as an outer housing (or a case of the outer housing) is provided. One I / O block (I / O module) 34 is configured by attaching a case part that also serves as a part. These I /
The O-blocks 34 can be electrically connected simply by overlapping and screwing them together (or by connecting the cables after screwing).
The number of / O blocks 34 can be increased or decreased as necessary. Although not shown in the drawing, when connecting each connector C of the wire assembly WA to the I / O block 34, the wire assembly WA is usually wired on a work table called a wiring board. Each connector C is electrically connected to the I / O block 34 via a wiring device disposed on the wiring board.

In the illustrated embodiment, the CPUs 21 and 32 of each of the units 20 and 30 are connected by a communication line 17 so as to enable direct communication. In the above configuration, the master unit 20 and the assembly-side unit 30 are connected via a shared memory system 40 so as to be able to perform serial communication. The shared memory system 40 includes a shared memory board 41 mounted on the master unit 20 as an expansion board, and a shared memory board 42 mounted on the assembly-side unit 30 as an expansion board. Each shared memory board 41,
42, a serial communication control unit 43 for serial communication;
44, and shared memories 45 and 46. Each serial communication control unit 43 and 44
5 and 46, and each CPU 21, 3
2 receives and transmits data communicated via the corresponding shared memories 45 and 46, respectively. Therefore, the master unit 20 and the assembly side unit 3
0 indicates that time-division multiplexed serial signals can be received and transmitted via the serial communication control units 43 and 44 of the shared memory system 40, and the received and transmitted data is transmitted to the shared memory 45, Recorded at 46, C
The data content is updated without being controlled by the PUs 21 and 32.

Next, the basic operation of the above-described process apparatus 10 will be described with reference to FIG. FIG. 2 is a flowchart showing the basic operations of the master unit 20 and the assembly-side unit 30 in the process apparatus 10 of FIG. Referring to the left side of FIG. 2, first, the master unit 20 operates the power switch to turn on the power, thereby performing step A1.
, The entire initialization including the memory 24 and input / output is performed.

Next, at step A2, the display unit 23
, A processing menu is displayed, prompting the operator to select which processing is to be performed. The operator selects necessary processing by operating the operation unit 23. Next, in step A3, the display unit 23 displays the wire assembly W
A part number selection menu of A is displayed, and a part number selection operation is performed. This part number selection operation is realized by selecting a part number to be processed by the operation unit 22. The display in step A3 may be performed simultaneously with the display of the product number in step A2.

Next, when the specification of the part number and the work is completed, in step A4, the CPU 21 determines whether or not the processing data of the specified processing program related to the specified part number is stored in the memory 21. If not stored, the process proceeds to the input step in step A41. In this input step, the operator performs teaching work, data input from a data medium (for example, a floppy disk), or input from a keyboard, as necessary.

If data has been input to the memory 24, the CPU executes a processing program in step A5, and writes necessary data to the shared memory 45 in step A6. Then, in step A7,
It is determined whether or not the processing result from the assembly-side unit 30 has been read into the shared memory 45. If the processing result has been read, the process proceeds to step A8. In step A8,
It is determined whether or not all the processes have been completed. If the processes have not been completed, the process returns to step A6. If the processes have been completed, the process proceeds to step A9.

In the determination process of step A9, the quality of the wire assembly WA is determined based on the processing result from the assembly-side unit 30. Thereafter, in step A10, a pass / fail indication based on the determination result is displayed, and the process is terminated. Next, referring to FIG. 3, in the assembly-side unit 30, the entire initialization is performed in step B1 immediately after the power is turned on, corresponding to the above-described process.

In step B2, data is read from the shared memory 46 of the shared memory system 40 in order to execute the processing program of the master unit 20.
The read data is output to an external output, that is, the wire assembly WA in step B3. Next, in step B4, a signal from the wire assembly WA is received. In this process, for example, each terminal fitting T
, And a state change is transmitted to the master unit 20 assuming that the pin state has changed in the event of a voltage drop. Of course, on the contrary, the voltage rise may be regarded as a change.

At step B5, the CPU of the assembly-side unit 30 determines whether or not there is something to be determined and processed at the time when the data from the wire assembly WA is obtained. Necessary judgment and processing are performed, and if not, the process proceeds to step B7. Then, in step B7, the processing result is written into the shared memory 46 again. After writing the data, the process returns to step B2 to repeat the processing.

A processing program executed by each of the units 20 and 30 includes a plurality of programs for executing each processing performed on the wire assembly WA during a manufacturing process or an inspection of the wire assembly WA to be manufactured. When connecting the wire assembly signal wire W to the connector C, the assembly support program for indicating the pole to which the terminal fitting T of the signal wire W is to be connected, the conduction of the assembled wire assembly WA, A continuity inspection program for performing an inspection, and various signal evaluation processes such as a noise resistance evaluation of the wire assembly WA and a measurement of a signal transmission time are included.

A feature of the illustrated embodiment is that each unit 20, 30 transmits and receives a serial signal (steps A6, A8, B2, B7) via the shared memory 45, 46. Data is exchanged at all times,
The point is that the data contents are updated so as to be the same. FIG. 3 is a flowchart showing communication data processing in the embodiment of FIG. 1, wherein (A) shows transmission processing and (B) shows reception processing.

Referring to FIG. 3A, when executing the programs of FIGS. 2 and 3, each unit 2
0 and 30 frequently transmit and receive data signals, but the CPU 21 (32) on the transmitting side loads the data to be received from the local memory 24 (33) (step M1) and the corresponding shared memory. All that is necessary is to input the data to 45 (46) (step M2). As a result, the sending side CP
The U21 (32) can perform other processing in parallel with data reception without performing reception control.

On the other hand, FIG.
In (20), since the data content of the shared memory 46 (45) is automatically updated without being controlled by the CPU 32 (21), the CPU 32 (21) exclusively loads data from the shared memory 46 (45). (Step M3)
It is only necessary to output to the outside (the display unit when the receiving side is the master unit 20 and the wire assembly WA when the receiving side is the assembly side unit 30) (step M4). As a result, the CPU 32 (21) can perform other processing in parallel with data reception without performing reception control.

As described above, in the above embodiment, the same data is shared between the unit on the transmitting side and the unit on the receiving side by the shared memory system 40, so that each unit 20, 30 Various processes can be performed in parallel with the transmission and reception of the data. Therefore, the wire assembly W to be processed in real time
There is a remarkable effect that the step A can be performed.

In particular, when the assembly-side unit 30 has a building block configuration, by optimizing the installation state, useless wiring and space are eliminated.
There is an advantage that the equipment can be used efficiently. The above-described embodiment is merely an example of a preferred specific example of the present invention, and the present invention is not limited to the above-described embodiment. It goes without saying that various design changes are possible within the scope of the claims of the present invention.

[0027]

As described above, according to the present invention,
By sharing the same data between the transmitting unit and the receiving unit by using the shared memory, each unit can perform various processes in parallel with the reception and transmission of the data. Thus, there is a remarkable effect that it is possible to perform the process of the wire assembly to be processed.

In particular, when the assembly-side unit has a building block configuration, there is an advantage that by optimizing the installation state, useless wiring and space are eliminated, and the equipment can be used efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram of a process processing apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart showing basic operations of a master unit and an assembly-side unit in the process apparatus of FIG. 1 in association with each other.

3 is a flowchart showing communication data processing in the embodiment of FIG. 1, wherein (A) shows a transmission processing and (B) shows a reception processing.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Process processing apparatus 14 Serial signal line 20 Master unit 21 CPU 30 Assembly side unit 32 CPU 40 Shared memory system 45 Shared memory 46 Shared memory

Claims (2)

[Claims] An assembly unit having a communication function, a master unit for controlling the assembly unit, and a communication unit between the master unit and the assembly unit, the connection unit being configured to be connectable to the wire assembly via a connector of the wire assembly. And a serial communication unit connected to the master unit. Based on an instruction signal output from the master unit, a signal line of the wire assembly set in the instruction signal performs transmission and reception of a signal from the assembly side unit, thereby Process,
A wire assembly process processing device capable of transmitting a processing result signal indicating a result of the executed processing to a master unit, wherein the processing unit is provided in each of the master unit and the assembly-side unit, and receives and transmits via the serial signal line. A shared memory in which the same data is updated in the same manner. 2. An assembly side unit employed in the wire assembly processing apparatus according to claim 1, wherein the I / O can be increased / decreased in accordance with the number of circuits of the wire assembly for each wire assembly to be processed. An assembly-side unit having a building block configuration having an O port portion.