JPH1022742A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device with a dispersion correction circuit by which variation in the circuit characteristics due to dispersion in the manufacture process is surely corrected without changing a mask. SOLUTION: A dispersion detection circuit 11 detects variation in an operating characteristics of a transistor(TR) due to process dispersion. An A/D converter 12 applies A/D conversion to an output signal of the dispersion detection circuit 11. A selection circuit 17 selects an internal circuit 18 to cancel the dispersion in the operating characteristics of the TR among a pulrality of internal circuits 18 whose operating characteristics differ and activates the selected circuit 18, based on an output signal from the A/D converter 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a correction function for correcting a variation in circuit operation due to a variation in a process.

2. Description of the Related Art In recent years, semiconductor integrated circuit devices have become more highly integrated and multifunctional, and as a result, internal circuits have become more complicated and larger in scale. Such a semiconductor integrated circuit device has a variation correction circuit for maintaining the characteristic change within a standard because the process variation greatly affects the circuit characteristics. Then, it is necessary to optimally correct the circuit characteristics by the variation correction circuit to improve the yield.

[0003]

2. Description of the Related Art FIG. 5 shows an example of a variation correction circuit mounted on a conventional semiconductor integrated circuit. The sources of the N-channel MOS transistors Tr1 and Tr2 constituting the operational amplifier 1 are connected to the ground GND via the N-channel MOS transistor Tr3.

[0004] A bias voltage VB is supplied from the bias voltage generation circuit 2 to the gate of the transistor Tr3. In the bias voltage generation circuit 2, a resistor R1 and an N-channel MOS transistor Tr4 are connected in series between a power supply Vcc and a ground GND, and the gate of the transistor Tr4 is connected to its drain.

Therefore, the transistor Tr4 operates as a diode, and a voltage corresponding to the threshold value of the transistor Tr4 is output as the bias voltage VB. When the bias voltage VB is supplied to the gate of the transistor Tr3, the transistor Tr3 is turned on. The bias current I flows, and the operational amplifier 1 is activated.

The input signals IN and / IN are input to the gates of the transistors Tr1 and Tr2, and the drain potential of the transistor Tr2 goes high or low based on the input signals IN and / IN.

The drain of the transistor Tr2 is connected to the gate of a P-channel MOS transistor Tr5 constituting the output section of the operational amplifier 1, the source of the transistor Tr5 is connected to the power supply Vcc, and the drain is connected to the output terminal To. With the N-channel MOS transistor T
Connected to ground GND via r6.

The bias voltage VB is supplied to the gate of the transistor Tr6. When the power supply Vcc is supplied to the bias voltage generation circuit 2 and the bias voltage VB is output, the transistor Tr6 is always turned on. Further, the size of the transistor Tr6 is set sufficiently smaller than the size of the transistor Tr5, and the transistor Tr6 operates as a high resistance to the transistor Tr5.

Therefore, when the transistor Tr5 is turned on based on the input signals IN and / IN, the output signal OUT output from the output terminal To becomes H level, and when the transistor Tr5 is turned off, the output signal OUT becomes It becomes L level.

In the operational amplifier 1 configured as described above, when the threshold value of the transistor Tr4 fluctuates due to process variations, the bias voltage VB fluctuates. Then, since the bias current I flowing through the transistor Tr3 varies, the circuit characteristics of the operational amplifier 1 vary.

Therefore, a variation correction circuit 3 is provided in advance to suppress a variation in circuit characteristics of the operational amplifier 1 due to a variation in the bias voltage VB. In the variation correction circuit 3, N-channel MOS transistors Tr7 to Tr9 each having a different size from the transistor Tr3 are laid out in advance adjacent to the transistor Tr3.

[0012] After grasping the tendency of the variation of the bias voltage VB due to the process variation from the manufactured sample, the mask is changed to change the bias voltage VB from the transistor Tr3 and the transistors Tr7 to Tr9. Are selected so that the fluctuation of the bias current I can be suppressed by canceling the bias current.

[0013]

In the operational amplifier configured as described above, the size of the transistor constituting the variation correction circuit 3 is selected by changing the mask. That is, a semiconductor integrated circuit device equipped with such an operational amplifier 1 is formed on a large number of chips formed on a wafer.

Then, the variation correction circuit 3 for all chips is changed by changing the mask in accordance with the tendency of process variation.
In the above, a similar transistor change is performed. However, the bias voltage VB due to the process variation
May vary between the chips at the outer peripheral portion and the chips at the central portion of the wafer. Then, even if the same correction is performed in the variation correction circuit 3 in each chip by changing the mask as described above, the circuit characteristics of each chip cannot be made uniform.

[0015] Therefore, in the correction of the variation due to the mask, the circuit characteristics of each chip cannot be made sufficiently uniform, so that the circuit characteristics of all the chips on the wafer may not be within the standard. As a result, since the yield cannot be sufficiently improved, there is a problem that the manufacturing cost increases.

Further, there is a problem that the process variation due to the continuous aging of the operation state of the manufacturing apparatus cannot be dealt with only by changing the mask. An object of the present invention is to provide a semiconductor integrated circuit device provided with a variation correction circuit capable of reliably correcting a change in circuit characteristics due to a variation in a manufacturing process without changing a mask.

[0017]

FIG. 1 is a diagram for explaining the principle of claim 1 of the present invention. That is, the variation detection circuit 1
1 detects a change in the operating characteristics of the transistor due to a process variation. The A / D converter 12 A / D converts the output signal of the variation detection circuit 11. The selection circuit 17 is based on the output signal of the A / D converter 12,
From among the plurality of internal circuits having different operating characteristics, an internal circuit for canceling the variation in the operating characteristics of the transistor is selected and operated.

According to a second aspect, the variation detection circuit includes:
A resistor and a diode-connected transistor are connected in series between the high-potential-side power supply and the low-potential-side power supply, and a threshold value of the transistor is detected from a connection point between the resistor and the transistor.

According to a third aspect, the variation detection circuit includes:
It comprises a ring oscillator and an F / V converter for converting the output signal frequency of the ring oscillator into a voltage value. 5. The semiconductor device according to claim 4, wherein the selection circuit includes a decoder for decoding a digital output signal of the A / D converter and a plurality of transistors of different sizes for setting a bias current of an operational amplifier based on the output signal of the decoder. And a switch circuit for selecting and operating one of the switches.

(Function) In the first aspect, the output signal of the variation detection circuit is A / D converted by the A / D converter, and the A / D conversion is performed.
Based on the output signal of the D converter, a circuit having an operation characteristic for canceling process variations is selected by a selection circuit.

According to the second aspect, the variation detecting circuit provides
A change in the threshold value of the transistor due to a process variation is detected. According to the third aspect, the variation detection circuit detects a signal obtained by converting the output signal frequency of the ring oscillator into a voltage value, and detects a variation in the threshold value of the transistor due to a variation in the process.

According to the present invention, the digital output signal of the A / D converter is decoded by the decoder, and the variation in the process is selected from among a plurality of transistors for setting the bias current of the operational amplifier by the switch circuit based on the decoded signal. Is selected such that the fluctuation of the threshold value of the transistor due to the above is canceled.

[0023]

FIG. 2 shows an operational amplifier having a variation correction circuit according to an embodiment of the present invention. The same components as those in the conventional example will be described with the same reference numerals.

An N-channel MOS transistor T connected in series is connected between the sources of the transistors Tr1 and Tr2 constituting the differential circuit of the operational amplifier 1 and the ground GND.
r11 and Tr15, N-channel MOS transistors Tr12 and Tr16 connected in series, N-channel MOS transistors Tr13 and Tr17 connected in series, and N-channel MOS transistors Tr14 and Tr18 connected in series Is done.

The transistors Tr15 to Tr18 are formed of transistors having different sizes, similarly to the transistors Tr3 and Tr7 to Tr9 of the conventional example. The transistors Tr15 to Tr18 are set so as to decrease in size in the order of the transistors Tr15 to Tr18. The bias voltage VB output from the bias voltage generation circuit 3 is input to the gates of the transistors Tr15 to Tr18.

The variation voltage detection circuit 11 is constructed similarly to the bias voltage generation circuit 3 by using a resistor R2 and an N-channel MOS transistor Tr19, and outputs a detection voltage VS equal to the bias voltage VB to the A / D converter 12. I do.

The A / D converter 12 detects the detection voltage V
S is converted into 2-bit digital signals D0 and D1 and output to flip-flop circuits 13a and 13b. An appropriate value of the detection voltage VS is 0.7V. In addition, A /
If the D converter 12 is configured as a flash type, for example, A /
The reference voltages input to the four comparators constituting the D converter 12 are, for example, 0.55 V, 0.65 V, 0.7
5 V and 0.85 V are set.

Therefore, when the detection voltage VS is 0.55 V to 0.
When it is in the range of 65V, the digital signals D0 and D1 become "00" and the detection voltage VS becomes 0.65V to 0.75V.
V, the digital signals D0 and D1 are “0”.
1 ", and when the detection voltage VS is in the range of 0.75 V to 0.85 V, the digital signals D0 and D1 become" 10 ".
When the detection voltage VS exceeds 0.85 V, the digital signals D0 and D1 become "11".

The flip-flop circuit 13a latches the digital signal D0 and outputs it to the decoder 14, and the flip-flop circuit 13b latches the digital signal D1 and outputs it to the decoder 14.

The flip-flop circuits 13a and 13b
The output signal is reset by a reset signal RS input when the power is turned on. The decoder 14 decodes the digital signals D0 and D1 latched by the flip-flop circuits 13a and 13b, and outputs decoded signals DE1 to DE4. The decode signals DE1 to DE1
Any one of DE4 becomes H level.

When the digital signals D0 and D1 become "00", only the decode signal DE1 becomes H level, and when the digital signals D0 and D1 become "01", the decode signal D1 becomes "00".
When only E2 becomes H level and the digital signals D0 and D1 become "10", only the decode signal DE3 becomes H level and when the digital signals D0 and D1 become "11",
Only the decode signal DE4 becomes H level.

The decode signals DE1 to DE4 are input to the gates of the transistors Tr11 to Tr14, respectively. Therefore, the transistors Tr11 to Tr14 operate as switches, and one of them is turned on.

Next, the operation of the variation correction circuit configured as described above will be described. When the detection voltage VS has an appropriate value, that is, when the bias voltage VB has an appropriate value, the digital signals D0 and D1 become "01", only the decode signal DE2 becomes H level, and the transistor T
r12 is turned on. Then, the operational amplifier 1 operates with the bias current set by the transistor Tr16.

The bias voltage V
When B rises, the detection voltage VS also rises. Due to the rise of the detection voltage VS, the digital signals D0 and D1 become "1".
When it becomes "0", the transistor Tr13 is turned on. Then, the operational amplifier 1 operates with the bias current set by the transistor Tr17. That is, when the bias voltage VB rises by 1 LSB of the A / D converter 12, the transistor Tr16 for setting the bias current of the operational amplifier 1 is switched to the transistor Tr17 to reduce the size, and the bias current VB increases with the rise of the bias voltage VB. The increase is suppressed.

When the bias voltage VB further rises, the digital signals D0 and D1 are increased due to the rise of the detection voltage VS.
Becomes "11", and the transistor Tr14 is turned on.
Then, since the operational amplifier 1 operates with the bias current set by the transistor Tr18, the increase in the bias current due to the increase in the bias voltage VB is suppressed.

On the other hand, when the bias voltage VB falls below an appropriate value due to process variations, the digital signals D0,
D1 becomes "00", only the decode signal DE1 becomes H level, and the transistor Tr11 is turned on. Then, the operational amplifier 1 operates with the bias current set by the transistor Tr15.

Therefore, a decrease in the bias current due to a decrease in the bias voltage VB is suppressed by increasing the size of the transistor for setting the bias current. With the variation correction circuit as described above, the following operational effects can be obtained. (A) The variation of the bias voltage VB due to the process variation is automatically converted into digital signals D0 and D1 by the variation detection circuit 11 and the A / D converter 12, and the bias signal is biased based on the digital signals D0 and D1. A transistor for setting the current is selected, and the transistor is selected to offset the bias current variation due to the bias voltage VB variation. Therefore, it is possible to automatically correct the bias current due to process variations. (B) Process variations can be automatically corrected without changing the mask. (C) Since the variation in the process can be corrected by the variation correction circuit provided for each chip, the variation in the process can be corrected for each chip. Therefore, since the operation speed of the internal circuit of each chip is reliably maintained within the standard, the chip yield can be improved. (D) Variations in the process due to continuous aging of the operation state of the manufacturing apparatus can be automatically corrected.

In the above embodiment, the variation correction circuit for suppressing the variation of the bias current of the operational amplifier 1 has been described. However, a variation correction circuit as described below may be configured. (1) A variation is corrected by selecting and operating one of a large number of circuits composed of a group of transistors of different sizes based on the output signal of the decoder of the embodiment. Can also. (2) Based on the output signal of the decoder according to the above embodiment, one of a large number of operational amplifiers composed of transistors of different sizes is selected and operated, whereby the operational speed of the operational amplifier due to process variations is reduced. It is also possible to adopt a configuration for correcting the fluctuation. (3) Based on the output signal of the decoder of the above embodiment, by selecting and operating one of a large number of comparators composed of transistors of different sizes, the operating speed of the comparator due to process variation is reduced. It is also possible to adopt a configuration for correcting the fluctuation. (4) Based on the output signal of the decoder of the above embodiment, a number of transistors formed of transistors of different sizes
By selecting and operating one of the / D converters, it is also possible to adopt a configuration in which a change in the operation speed of the A / D converter due to a process variation is corrected. (5) Based on the output signal of the decoder of the above embodiment, a large number of Ds composed of transistors of different sizes
By selecting and operating one of the / A converters, it is also possible to adopt a configuration in which a change in the operation speed of the D / A converter due to process variations is corrected. (6) The variation correction circuit shown in FIG. 3 is a circuit that corrects a variation in the threshold value of the P-channel MOS transistor due to a process variation. In a variation voltage detection circuit 11a including a P-channel MOS transistor Tr20 and a resistor, the source of the transistor Tr20 is connected to the power supply Vcc, and the gate and the drain are connected to the ground GND via the resistor R3.

Therefore, the threshold voltage of the transistor Tr20 changes from the drain of the transistor Tr20 to the detection voltage V.
Output as s. The threshold value of the detection voltage Vs is:
The signals are converted into digital signals D0 to Dn by the A / D converter 12a and output as variation information.

Based on such variation information, it is possible to configure a variation correction circuit that automatically corrects the variation in the threshold value of the P-channel MOS transistor due to the process variation as in the above-described embodiment. (7) The variation correction circuit shown in FIG. 4 is a circuit that corrects a variation in the oscillation frequency of the ring oscillator due to a variation in the process. In the ring oscillator 15, odd-numbered stages of inverter circuits are connected in a ring shape, and the output signal frequency fluctuates because the threshold values of the P-channel MOS transistor and the N-channel MOS transistor constituting each inverter circuit fluctuate due to process variations. I do.

The output signal of the ring oscillator 15 is F
/ V converter 16 and the output signal frequency of ring oscillator 15 is converted to a voltage. The F / V converter 1
The output signal of No. 6 is output to the A / D converter 12b, and the A / D converter 12b converts the output signal of the F / V converter 16 into digital signals D0 to Dn and outputs the digital signals as variation information.

Based on such variation information, any one of a large number of transistors formed in different sizes in a chip is selected and operated, or a large number of inverters formed of transistors of different sizes are operated. By selecting and operating a circuit, a variation correction circuit that automatically corrects a change in the threshold value of the transistor can be configured.

The technical ideas other than the claims which can be grasped from the above embodiment will be described below together with their effects. (1) In claim 4, the selection circuit is configured to control the A / D
A decoder for decoding the digital output signal of the converter;
Based on the output signal of the decoder, one internal circuit that operates so as to cancel the process variation is selected from among a plurality of internal circuits composed of transistor groups of different sizes. The operation of the selected internal circuit cancels out process variations. (2) In claim 4, the selection circuit is configured to control the A / D
A decoder for decoding the digital output signal of the converter;
Based on the output signal of the decoder, one operational amplifier that operates so as to cancel the process variation is selected from a plurality of operational amplifiers configured by transistors of different sizes. The operation of the selected operational amplifier cancels out process variations. (3) In claim 4, the selection circuit is configured to control the A / D
A decoder for decoding the digital output signal of the converter;
Based on the output signal of the decoder, one comparator that operates so as to cancel the process variation is selected from a plurality of comparators composed of transistors of different sizes. The operation of the selected comparator cancels out process variations.

[0044]

As described above in detail, the present invention provides a semiconductor integrated circuit device having a variation correction circuit capable of reliably correcting a change in circuit characteristics due to a variation in a manufacturing process without changing a mask. be able to.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing one embodiment.

FIG. 3 is a circuit diagram showing a variation of the variation detection circuit.

FIG. 4 is a circuit diagram illustrating a variation of the variation detection circuit.

FIG. 5 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 11 Variation detection circuit 12 A / D converter 17 Selection circuit 18 Internal circuit

Claims (4)

[Claims] 1. A variation detection circuit for detecting a change in operation characteristics of a transistor due to a variation in a process, and an A / D converter for A / D converting an output signal of the variation detection circuit.
A D converter; and a selection circuit for selecting and operating an internal circuit that cancels a variation in the operating characteristics of the transistor from a plurality of internal circuits having different operating characteristics based on an output signal of the A / D converter. A semiconductor integrated circuit device comprising: 2. The variation detection circuit according to claim 1, wherein a resistor and a diode-connected transistor are connected in series between a high-potential-side power supply and a low-potential-side power supply, and the transistor is connected from a connection point between the resistor and the transistor. 2. The semiconductor integrated circuit device according to claim 1, wherein a threshold value is output. 3. The semiconductor integrated circuit according to claim 1, wherein said variation detection circuit comprises a ring oscillator, and an F / V converter for converting an output signal frequency of said ring oscillator into a voltage value. apparatus. 4. The selection circuit includes: a decoder for decoding a digital output signal of the A / D converter; and a plurality of transistors of different sizes for setting a bias current of an operational amplifier based on an output signal of the decoder. 2. The semiconductor integrated circuit device according to claim 1, further comprising: a switch circuit for selecting and operating one of the two.