JPH10224708A - Device for displaying plural pictures - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display plural pictures on one screen by successively executing processing for successively selecting one video signal from plural digitally compressed video signals, reducing a frame to be independently processed in each video signal and storing the reduced frame in a prescribed address of a frame memory. SOLUTION: When the display of plural pictures is instructed from an input device 5, a screen is divided into nine areas and a program guide for programs being broadcasted at present in eight previously specified channels is displayed on the center of the screen. The program guide display part is generated by an on-screen guide generation circuit 4. The pictures of programs being broadcast at present in the eight channels are displayed on the remaining peripheral parts other than the center part of the nine divided screens. The selection order of eight channels is obtained by a processing procedure for checking whether each of all previously specified channels is included in a selected transponder or not and then selecting a succeeding transponder.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-image display device for displaying a plurality of video signals transmitted after being subjected to digital image compression processing.

[0002]

2. Description of the Related Art Broadcasting in which a video signal is digitally compressed according to a system such as MPEG and transmitted using satellite broadcasting has been put to practical use. In this broadcast, since a video signal is digitally compressed, a plurality of channels can be multiplexed on one frequency and transmitted. In other words, it is possible to broadcast and use programs of a much larger number of channels as compared with the conventional terrestrial television broadcasting. Therefore, it is an important function for the television receiver to easily select a program desired by the user from a large number of programs.

[0003] For example, Japanese Patent Application Laid-Open No. 7-67061 discloses that in order to simultaneously display a plurality of broadcast images of a channel which has been pre-selected and registered on a screen, the pre-registered channels are cyclically arranged at predetermined intervals. There has been proposed an idea of automatically selecting a channel, writing a video signal of each channel to an image memory, and displaying a plurality of images on a screen.

[0004]

However, the above prior art cannot be applied to the case where each video signal is digitally compressed by the MPEG system.

Accordingly, the present invention proposes an image display device which obtains a video signal processed and transmitted by the MPEG system and displays a plurality of images.

[0006]

According to the present invention, there is provided a tuner control device for sequentially selecting a plurality of predetermined channels, and an independent decoding process from an MPEG bit stream output from the tuner control device. Only possible I frames are MPEG-decoded and written at predetermined positions in an image memory, and are read out so as to form one screen. Therefore, a plurality of digitally compressed video signals sequentially selected can be divided and displayed on the same screen.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a general digital satellite broadcast receiving apparatus. In such digital satellite broadcasting, for example, DSS in the United States and Perfect TV in Japan, a plurality of programs and data are time-division multiplexed into one bit stream using a digital compression algorithm based on the MPEG system. Transmitted. MPEG is a digital compression method standardized by ISO / IEC, and two types of standardization have been completed (MPEG1 and MPEG2). MPEG1 and MP
Details of the compression algorithm of EG2 are given in ISO / IEC 1172 and 13818, respectively.

In such digital satellite broadcasting,
A channel shall mean the transmission of one program,
It does not mean one transponder of the satellite, ie one frequency. In digital satellite broadcasting, one transponder transmits a plurality of channels, and each channel has a channel number. Therefore, one frequency corresponds to a plurality of channel numbers. Therefore, in order to select a program, it is necessary to first select a frequency on which the program is multiplexed, and then extract data of a desired program from the obtained bit stream.

In FIG. 1, reference numeral 1 denotes a reception signal input terminal, to which a signal transmitted by a satellite, a cable or the like is input. Reference numeral 2 denotes a tuner for demodulating a signal modulated by a modulation method suitable for the transmission process to generate a baseband digital signal, and reference numeral 3 denotes an input of the output of the tuner 2 for conversion into a signal corresponding to a display format. Video processing circuit.

Reference numeral 4 denotes an on-screen guide generating circuit for generating a program guide display screen for displaying the program guide on-screen. Reference numeral 5 denotes an input device which is operated by a user to issue an operation command. You. Operation unit 5
Are provided with left, right, up and down cursor movement buttons, menu buttons, select buttons, and the like.

Reference numeral 6 denotes a CPU for controlling the program content display screen based on the information from the operation unit 5 and for controlling the tuner 2 to select a desired program by a user. A multiplexer for receiving an output signal from the control unit 3 and an output signal of the on-screen guide generation circuit 4 and controlling to select and output one of them according to a control signal from the CPU 6;
8 is a CRT display. 9 is a memory,
In addition to storing the set values relating to the program selection set by the user, a program for the CPU 6 is stored, and for example, a writable ROM can be used.

The on-screen guide generation circuit 4 generates on-screen guide information in accordance with program information (extracted by the video processing circuit 3) sent from a satellite. The program information includes information such as the start / end time of the program, the title, the contents, and, in the case of a pay program, the fee.

The video processing circuit 3 also performs MPEG decoding. FIG. 2 is a block diagram of a portion related to the MPEG decoding process. The selected MPEG bit stream from the tuner is provided at input 20.
Each frame of I, P and B is time-division multiplexed in this MPEG bit stream. This MPEG bit stream is for adjusting the time axis of the originally variable length MPEG video stream in the bit buffer 21 and outputting it as a fixed length baseband signal.

The output of the bit buffer 21 is supplied to an adder 24 via an inverse quantization circuit 22 and an inverse DCT circuit 23. An I frame in an MPEG bit stream is
Since the decoding can be performed without reference from another frame, the first switch 25 is connected to the fourth terminal 25d and is output as it is. Since the I frame is referred to by the P and B frames, it is buffered in the first frame memory 26 or the second frame memory 27. The connection of the first switch 25 is controlled in units of macroblocks by the CPU 6 which receives an MPEG bit stream before decoding and determines an input frame or the like.

[0015] The P frame is a previously decoded I
Alternatively, since the decoding is performed with reference to the P frame, the first switch 25 is connected to the first terminal 25a or the third terminal 25c.
And the output of the first frame memory 26 is
Supplied to However, if the correlation with the reference frame is low, the first switch 25 may select the fourth terminal 25d because intra processing is performed in macroblock units. P frames are buffered because they are referenced from B or another P frame.

The B frame is decoded by interpolation with reference to already decoded past and future frames. Therefore, the first switch 25 is connected to the second terminal 25b. However, the structure of the B frame can be the same as that of the I or P frame in macroblock units, so that the connection of the first switch 25 changes accordingly. Since the B frame is not referenced from other frames, it is output immediately after decoding,
It is buffered in the third frame memory 29 for timing adjustment.

The second switch 30 is for switching the buffer for storing the reference frame, and is switched alternately in frame or field units. The third switch 31 is a switch for selecting and switching a frame to be output.
In the case of a B frame, the first terminal 31a is connected to I or P
In the case of a frame, the second terminal 31b or the third terminal 31c
Connected to. The connection of the second and third switches is controlled by the CPU 6 on a frame (field) basis.

Next, the operation will be described mainly with reference to FIG. 3 focusing on the tuner control at the time of displaying a plurality of images. When an instruction to display a plurality of images is issued from the input device 5 in FIG. 1, the display of a plurality of images shown in FIG. 4 is performed. In this multi-image display, the screen is divided into nine parts, and a list display (program guide display) of currently broadcasted programs of eight pre-specified channels is performed at the center of the screen. This program guide display portion is generated by the on-screen guide generation circuit 4. The eight channels specified in advance are, for example, channels preferred by the user.

On the remaining peripheral portion of the nine-divided screen, images A to H of programs currently being broadcast on eight channels are displayed. As will be described later, these images are obtained by sequentially processing and displaying video signals of eight channels, and are not complete moving images. However, since the images are updated at certain intervals, The contents can be determined.

The sequential selection of eight channels is performed according to the flowchart of FIG. The point here lies in the processing procedure of checking whether or not all channels specified in advance are included in the selected transponder, and then selecting the next transponder.

First, when the display of a plurality of images is designated by the input device 5, the on-screen guide generation circuit 4
The program guide 41 shown in the center of FIG. 4 is created and displayed based on the eight designated channel data. Then, a channel number in the currently selected transponder (normally, about five channels are included in one transponder) is obtained (step 101). The channels specified in advance are stored in the memory 9 in the data structure shown in FIG. 5 for one selected channel. The data number 51 is a number from 1 to 8, and is a number uniquely assigned to the designated channel data. Further, the data numbers 51 correspond to the display positions A to H in FIG. 4, respectively. Channel number 5
2 stores the designated channel number as it is. The flag 53 is used for the processing in FIG. 3, and is cleared when a display of a plurality of images is instructed.

Next, a variable n for designating the data number of the designated channel is initialized to 1 (step 10).
2). Then, the state of the flag of the designated channel data of data number n is checked (hereinafter, the flag of data number n is referred to as flag (n)) (step 103). As will be described later, the flag is set to 1 when the selection output from the tuner 2 is instructed, so that a state of 0 (zero) indicates that the flag has not yet been processed. If the flag (n) is not 0, step 108
Proceed to.

If the flag (n) is zero, it is checked whether the channel number of the data number n (represented as channel (n)) matches the channel in the currently selected transponder (step 104). . If they do not match, the process proceeds to step 108. In step 108, n
Is incremented by one, and then the process proceeds to step 109, where n> 8
Find out if. If n> 8, the process returns to the step 103, and the processes after the step 103 are performed for a new n.

In step 104, channel (n)
Is determined to match the channel in the currently selected transponder, the flag (n) is set (step 105), and an instruction is issued from the tuner 2 to output the bit stream of the channel (n). ,
In the video processing circuit 3, the bit buffer 21 is reset, an I frame is extracted from the video stream output from the tuner 2, and downsampled and written to a position corresponding to the data number n in the frame memory. This write operation will be described later. Then, in step 107, channel (n)
Wait until the writing for is completed.

When the waiting at step 107 is completed, that is, when the writing for the channel (n) is completed, the process proceeds to step 108, and the process is continued for a new n. If n> 8, it means that the check on the currently selected transponder has been completed. And
A flag is set for the channel for which the selection processing in the tuner 2 has been completed. Therefore, in order to search for an unprocessed channel, n is initialized to 1 again (step 1).
10) Check whether the flag (n) is zero (step 111). If it is not zero, the process proceeds to step 113, and n is updated.
Return to

If the result of the determination in step 111 is that the flag (n) is equal to zero, then step 11
Proceeding to 2, the transponder to which this channel (n) belongs is selected by the tuner 2, and the channel included in the selected transponder is acquired. And step 1
Proceeding to 05, the processing is continued. That is, since an unprocessed channel has been found, a transponder to which this channel is transmitted is selected, a flag corresponding to the channel is set, and a channel (n) is transmitted from the tuner 2.
And performs a predetermined process in the video processing circuit 3. Thereafter, the process proceeds to step 108, and the processing is continued for the unprocessed channel among the designated channels. n>
At 8, the process for the current transponder has been completed, and a new transponder is selected in steps 111 and 112.

If n> 8 in step 114,
Since it indicates that there is no more unprocessed designated channel, the process proceeds to step 115 to clear all designated channel flags. Then, the process returns to step 101 to repeat the processing. In other words, in the multiple image display process, a process of sequentially selecting a designated channel, extracting an I frame, and updating the display screen is repeated. Since the processing is performed with priority given to the channels in the same transponder, the required time for processing the entire channel can be shortened as compared with the case where the channel selection is controlled only according to the information of the designated channel.

FIG. 6 is a block diagram for explaining the operation of the video processing circuit 3 when displaying a plurality of images. The same components as those in FIG. 2 are denoted by the same reference numerals and description thereof is omitted. In the multiple display process, as described above, the decoding process is performed only on the I frame, and the P and B frames are ignored. Accordingly, the first switch 25 is always connected to the fourth terminal 25.
d is selected. The first frame memory 26 stores I
The second frame memory 27 is used for decoding a frame, and is used as a buffer for synthesizing a plurality of screens.

The decoded I frame is read from the first frame memory 26, and the screen size is reduced by the downsampling circuit 33. In this embodiment, 9
Since screen division display is performed, downsampling is performed to one third in both horizontal and vertical directions. The reduced image signal is CP
In accordance with an instruction from U6, the image is written in the address range of the second frame memory corresponding to the data number of the channel to which the image belongs. Then, by reading the stored contents from the second frame memory 27 at a predetermined timing, images A to H in FIG. 4 are formed. still,
The operation of each frame memory is performed by the memory controller 32 according to an instruction from the CPU 6.

The output of the second frame memory 27 is output from the third switch 31 fixed to the third terminal, and is synthesized with the output of the on-screen guide generation circuit 4, that is, the guide screen 41 in FIG. When the cursor movement button of the input device 5 is operated, the cursor on the guidance screen 41 moves up and down. Then, when the cursor is moved to a desired channel portion and the select button is operated, the corresponding program is selected, the processing in FIG. 3 is completed, and the selected program is displayed on the full screen. Characters A to H corresponding to the guide screen are overlapped in the portion where the video of each channel is displayed, and the user can display the contents of the currently broadcast program in a compressed size. You can make a selection while confirming with,
It is convenient for the user.

It is also possible to overlap and display the actual channel numbers instead of the letters A to H. Only the video of the channel where the cursor is located on the guide screen 41 can be displayed with the surroundings surrounded by a highlight frame. In this case, since the display position on the screen in the designated channel is predetermined, the on-screen guide generation circuit 4 creates a frame portion of the display position corresponding to the program where the cursor is located on the guide screen 41, and Processing circuit 3 can be realized by combining with an empty output.

In the above embodiment, the designated channel is a channel in which the user's favorite channel is registered in advance. As a method of registering a channel desired by the user, a method of displaying a channel registration screen and inputting a desired channel number by the user can be applied. In addition, as a format for displaying a plurality of images, in addition to the format shown in FIG.
Division, 16 division, etc. are also conceivable, and other division methods are also conceivable.

The call of the multiple display screen is in accordance with the user's instruction via the input device 5, but is automatically performed when the power of the television receiver or the set-top box using the multiple image display device is turned on. It is also possible to set so that a plurality of images are displayed. In this case, when the power is turned on, the processing is performed according to the flowchart of FIG.

When the power is turned on, first, it is checked by checking a predetermined address in the memory 9 whether or not the user has set so that a plurality of images are displayed when the power is turned on (step 71). If the display of a plurality of images has been set, the display of the plurality of images is executed in step 72, and the process returns to the main routine of the program. If the display of a plurality of images is not set, in step 73, it is determined whether the channel previously selected when the power was turned off (stored as a last channel at a predetermined address in the memory 9 at the time of the power-off processing) is a pay broadcast. If the check is made and the broadcast is not a pay broadcast, the process proceeds to step 74, where the last channel is displayed.

If the last channel is a pay broadcast, it is checked whether or not a display channel has been designated (step 75. A channel to be selected preferentially in advance can be designated. If it is specified, the channel is displayed (step 76). If no designation is made, the process proceeds to step 77, where a grid-like program guide is displayed.
After the completion of steps 74, 76 and 77, the program returns to the main routine of the program. As described above, the user can specify the initial screen when the power is turned on, so that the operability of the apparatus is further improved.

[0036]

As described above, according to the present invention, MP
Focusing on frames that can be independently processed from multiple video signals that are digitally compressed and transmitted by the EG method, etc., and combining the results of decoding, enables multiple images to be displayed at once. And its usefulness is high.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital satellite broadcast receiver.

FIG. 2 is a block diagram illustrating details of a video processing circuit.

FIG. 3 is a flowchart illustrating an operation of tuning control of a tuner.

FIG. 4 is an explanatory diagram of a multiple display screen.

FIG. 5 is an explanatory diagram showing designated channel data.

FIG. 6 is a block diagram illustrating details of a video processing circuit in multiple display processing.

FIG. 7 is a flowchart showing processing at the time of power-on.

[Explanation of symbols]

 6 CPU 21 Bit buffer 22 Inverse quantization circuit 23 Inverse DCT circuit 24 Interpolation circuit 25 First switch 26 First frame memory 27 Second frame memory 29 Third frame memory 30 Second switch 31 Third switch 32 Memory controller 33 Downsampling circuit

Claims (4)

[Claims] 1. A video signal which is sequentially selected from a plurality of digitally compressed video signals, and a frame which can be independently processed in the selected video signal is reduced to a predetermined address of a frame memory. A multi-image display device that displays a plurality of videos in one video by sequentially performing a process of storing the images. 2. Extraction means for extracting data of a target video signal from a plurality of media in which a plurality of digitally compressed video signals are multiplexed and transmitted, and receiving an output from the extraction means, Signal processing means for down-sampling independently decodable frames of video signal data and storing the down-sampled frames at a predetermined address of a frame memory; and control means for controlling the extraction means and the signal processing means, wherein A multiple image display device comprising a control means for sequentially extracting a predetermined number of video signals by the extracting means, reading out the video data stored in the frame memory and displaying one video. 3. An extraction by the extraction means, wherein all of the video signals transmitted by a medium selected from the plurality of media and which match a predetermined number of video signals specified in advance are extracted. 3. The multi-image display apparatus according to claim 2, wherein the same process is repeated thereafter for a medium to which an unextracted one of the predetermined number of video signals belongs. 4. A tuner for receiving a digital broadcast in which digitally compressed video signals of a plurality of channels are multiplexed and transmitted to one transponder and outputting one video signal data, and a video from the tuner. A video processing circuit having at least one image memory for decoding signal data; an on-screen guide generation circuit for generating a guide screen for a user; and synthesizing and outputting the video processing circuit and the on-screen guide generation circuit output A synthesizing circuit; a control circuit for controlling operations of the tuner, the video processing circuit, the on-screen guide generating circuit and the synthesizing circuit; and a memory for storing a program of the control circuit and at least a predetermined number of designated channels. Transmitting the video signals of the predetermined number of designated channels by the tuner; The processing to be selected is characterized in that after processing all of the channels in one transponder that match the predetermined number of designated channels, processing for the next transponder is performed. Video data
By reducing the image size of the unit image that can be independently decoded and writing the image size in the image memory, the image of the video signal of a plurality of channels is written in the image memory and read out to form one screen. A multi-image display device, wherein a guide screen from the on-screen guide generation circuit and an output of a video processing circuit including a plurality of images are combined and displayed.