JPH10224371A - Data communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an equipment in which a function is easily added or revised. SOLUTION: A sequence control section 4 is connected to a buffer circuit 1, a header conversion section 2, a DA interpreter section 31, a header conversion memory 32, and a DA/SA check section 22 by a common bus 5. The sequence control section 4 extracts a value received by the buffer circuit 1 and included in an ATM cell via the common bus 5 and controls a sequence to rewrite values of VPI, VCI, MID depending on whether a cell is a head cell, an intermediate cell or a final cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication apparatus for changing the value of received data and transmitting the data, and more particularly to an ATM (As
The present invention relates to a data communication device that performs an exchange operation in a connectionless communication server (CLNAP: connectionless network access protocol) of the asynchronous transfer mode (asynchronous transfer mode) method.

[0002]

2. Description of the Related Art As a communication service on an ATM, a connectionless service has been considered in order to easily establish a connection between terminals and simultaneously establish a connection with an unspecified number or plurality of terminals. In this connectionless service, a connectionless server analyzes an address and selects a communication partner.

FIG. 2 is an explanatory diagram of a general connectionless network. First, a message is sent from a source terminal to a server. The originating server is
Based on the source and destination specified on the message,
It creates a PI, VCI, etc., and sends a message to the destination server. In this way, the server at the other end operates to transfer the message to the terminal at the destination.

FIG. 3 is an explanatory diagram of a format of communication data. As shown in the figure, the message includes an address indicating a delivery destination (DA: Destination Address) and an address indicating a transmission source (SA: Source Address), and one message is divided into a plurality of ATM cells. This division is internationally standardized.

[0005] Each of the divided cells has a field (ST: segment type) indicating the position of a message, and can identify a head (BOM), a middle (COM), and an end (EOM). Further, a connection is established between the terminal and the server by a logical path identifier (VPI) and a logical channel identifier (VCI) included in the header of the ATM cell. When a plurality of messages are transmitted from the terminal, a multiple identifier (MID) is included as a means for distinguishing the messages. In FIG. 3, SN is a sequence number in the message.

In a conventional server, upon receiving a cell in which BOM is displayed in ST, DA, S included in the head cell are received.
A, VP, and VC are extracted, and a DA / SA check is performed. If DA / SA is the correct value, translate DA and D
If there is a new VPI and VCI corresponding to A, the values are transferred to the header conversion table. The new VPI and VCI are set in the table together with the appropriate VID and the old VPI, VCI and MID. When ST is COM, VPI, VCI, MI
By replacing D, it is sent to the delivery destination.

[0007]

In a conventional data communication apparatus, the above-described processes such as DA / SA check, DA translation, and header conversion are performed by hardware using fixed blocks. Since the configuration is such that certain processing is performed, there is a problem that when a function change or a procedure is added as a data communication device, this cannot be easily performed.

[0008] In view of the above, there has been a demand for an apparatus which can easily change or add a function in a data communication apparatus.

[0009]

The present invention employs the following structure to solve the above-mentioned problems. <Structure of Claim 1> A buffer circuit for storing received data, a data converter for converting a destination address of the received data into an arbitrary value and transmitting the converted data, and converted data for holding a converted value for the destination address of the arbitrary data The holding unit is connected to the buffer circuit, the data conversion unit, and the conversion data holding unit via a common bus, and obtains, from the conversion data holding unit, a conversion value for the reception data read by the buffer circuit, and provides this value to the data conversion unit. A data communication device comprising: a sequence control unit that controls a sequence.

<Description of Claim 1> The line type in which the buffer circuit and the data conversion unit are provided is, for example, an ATM line, but other various line types such as 10BASE5 and FDDI are applicable. The conversion data holding unit is
It is hardware such as a memory that holds a value to be converted according to the destination address of the received data. The sequence control unit controls a sequence of extracting a destination address from the data accumulated in the buffer circuit, obtaining a value corresponding to the destination address from the conversion data holding unit, and registering the value in the data conversion unit.

Therefore, even when the sequence is changed / added, it is only necessary to change the procedure of the sequence control unit. In addition, the sequence control unit and the conversion data holding unit
Since they are connected by the common bus, addition / reduction of the conversion data holding unit can be easily performed. Further, since the buffer circuit and the data conversion unit are also connected to the common bus, if the control procedure of the sequence control unit is compatible, it is possible to simultaneously connect various line types. Also, by adding the sequence control unit procedure,
It is also possible to perform processing of a plurality of protocols in parallel.

In a data communication apparatus for performing connectionless communication in an asynchronous transfer mode, a buffer circuit for storing ATM cells and a transmission destination address of the ATM cell are converted into an arbitrary value and transmitted. A header conversion circuit, a conversion data holding unit for holding a conversion value corresponding to a destination address of the ATM cell, and an ATM cell connected to the buffer circuit, the header conversion circuit, and the conversion data holding unit via a common bus and received by the buffer circuit; A sequence control unit for controlling a sequence for taking out a value corresponding to the destination address from a destination address included in the header conversion circuit via a common bus and providing the value to a header conversion circuit. Communication device.

<Explanation of Claim 2> The invention of claim 2 is an apparatus for performing connectionless communication in ATM as a data communication apparatus. In this data communication device, the sequence control unit controls the sequence for performing the header conversion of the ATM cell, so that the function of the device can be easily changed or added by changing the procedure of the sequence control unit. For example, by adding a procedure of the sequence control unit, the line type can be changed not only to ATM but also to FD.
A configuration for controlling various lines such as DI and 10BASE5 can be easily realized. Also, regarding the protocol,
It is also possible to easily add a function of performing processing of a protocol other than CLNAP in parallel.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. <Configuration> FIG. 1 is a configuration diagram showing a specific example of the data communication apparatus of the present invention. 1 includes a buffer circuit 1, a header conversion circuit (data conversion unit) 2, a converted data holding unit 3, a sequence control unit 4, and a common bus 5.

The buffer circuit 1 receives an ATM cell,
A data storage unit that stores the ATM cells. The header conversion circuit 2 is a circuit having a function of converting the header of the ATM cell received by the buffer circuit 1 based on the given VPI, VCI, and MID values and transmitting the converted data.

The conversion data holding unit 3 has a function of holding a value for performing header conversion of an ATM cell, and includes a DA translation unit 31, a header conversion memory 32, and a DA / SA check unit 33. The DA translator 31 converts DA into VPI,
This is a routing table for converting to a VCI, and is composed of a content addressable memory (CAM) or the like. The header conversion memory 32 is a memory including a RAM and the like. The DA / SA check unit 33 has a check table provided in advance and has a function of checking DA and SA.

The sequence control unit 4 includes buffer circuits 1 to
Connected to the conversion data holding unit 3 by a common bus 5,
A procedure for searching for a value included in the received ATM cell is registered in advance. That is, the value contained in the ATM cell received by the buffer circuit 1 is extracted via the common bus 5, and if the value is the head (BOM), a new VPI, VCI, MID is generated based on the data in the conversion data holding unit 3. Get
A control unit that controls a sequence such as registration in the header conversion circuit 2, and a PLD (Programmable logic device).
e) etc. It should be noted that such a process can be controlled by a sequencer without using a microprocessor, and thus is constituted by such an LSI.

<Operation> FIG. 4 is a flowchart of a sequence control process performed by the sequence control unit 4. The sequence control unit 4 periodically checks whether or not the buffer circuit 1 is receiving a cell (step S1), and if a cell is received, extracts the ST (step S2). As a result, it is checked whether this cell is one of BOM, COM and EOM (step S3). Cell is BO
If M, DA, SA, VPI,
The VCI is taken out and sent to the DA / SA check unit 33,
The DA / SA check unit 33 checks this (steps S4 and S5). That is, the DA / SA check unit 33
Checks that SA is the correct value, so V
It is checked whether a combination of P, VC, and SA has been registered. If SA and DA are in the same group, it is checked whether a combination of SA and DA is registered to permit transfer.

If the result of the check in step S5 is O
If it is K, a new VPI and VCI corresponding to the DA are obtained from the DA translation unit 31 (step S6), and an appropriate MID that can be distinguished from other cells is obtained (step S7). Is registered in the header conversion memory 32 (step S8). The registered value is also sent to the header conversion circuit 2 (step S9). As a result, the header conversion circuit 2 converts the received VPI, VCI, and MID from
The cell is replaced with the values of the transmission VPI, VCI, and MID, and the cell is transmitted (step S10).

In step S3, if the ST of the cell indicates COM, the header conversion memory 3
2, the VP registered in step S8
I, VCI, and MIP are directly read (step S11), and this value is passed to the header conversion circuit 2. Further, in step S3, if the ST of the cell indicates EOM,
After reading the value of the header conversion memory 32, the value is deleted (step S12). Then, the read value is sent to the header conversion circuit 2 (step S13), and the header conversion circuit 2 replaces the value of the cell header and transmits it (step S14). This ends the sequence control for one message.

After registering the value in the header conversion memory 32,
If any error is detected in a cell in the middle, the corresponding table in the header conversion memory 32 is deleted.

In the data communication apparatus configured as described above, when the procedure is changed / added, it is only necessary to change the procedure registered in the sequence control unit 4. As such an example, for example, instead of deleting the VPI, VCI, and MID registered in the header conversion memory 32 each time, a certain number of sets of VPI, VCI, and MID can be registered, and when the number reaches a certain number. Can be easily changed or added, such as erasing the oldest one first or fetching the VPI, VCI, and MID directly from the DA to the header conversion memory 32.

The DA translation unit 31, the header conversion memory 32, and the DA / SA check unit 33 only search for numerical values, and since only the number of bits is different, hardware is added to the configuration. Can be used. Further, since the components are connected via the common bus 5, the capacity of the table can be easily added / reduced.

Further, when the line speed is low or the processing speed of the server has room, a plurality of lines can be connected. FIG. 5 is an explanatory diagram of the configuration in this case. In the figure, each of lines 1 to n has a configuration including the buffer circuit 1 and the header conversion circuit 2 shown in FIG.
Here, each of the lines 1 to n does not depend on the line type.
For example, one line is 10BASE5, another line is FDD
A configuration such as I is also possible.

Further, by adding the sequence control unit 4 or adding a control procedure to be registered, it is possible to perform processing of a protocol other than CLNAP in parallel.
In other words, since the functions are connected by the common bus 5, functions can be freely added.

In the above specific example, the case where the data communication device is CLNAP using the ATM communication system has been described. However, the present invention is not limited to this, and other than the above, such as 10BASE5, FDDI and IP, etc.
The present invention can be similarly applied to any data communication device that transmits the data after changing the value of the received data.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a specific example of a data communication device of the present invention.

FIG. 2 is an explanatory diagram of a general connectionless network.

FIG. 3 is an explanatory diagram of a format of communication data.

FIG. 4 is a flowchart of a sequence control process in the data communication device of the present invention.

FIG. 5 is an explanatory diagram of a configuration when a plurality of lines are connected in the data communication device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Buffer circuit 2 Header conversion circuit 3 Conversion data holding part 4 Sequence control part 5 Common bus 31 DA translation part 32 Header conversion memory 33 DA / SA check part

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Katsura Noritake 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation

Claims (2)

[Claims] 1. A buffer circuit for accumulating received data, a data conversion unit for converting a destination address of the received data into an arbitrary value and transmitting the converted value, and a conversion data holding unit for holding a converted value for the destination address of the arbitrary data Unit, the buffer circuit, a data conversion unit and a conversion data holding unit are connected to a common bus, a conversion value for the reception data read by the buffer circuit is obtained from the conversion data holding unit, and this value is used as the data conversion unit And a sequence control unit for controlling a sequence given to the data communication device. 2. A data communication device for performing connectionless communication in an asynchronous transfer mode, comprising: a buffer circuit for storing ATM cells; a header conversion circuit for converting a destination address of an ATM cell into an arbitrary value for transmission; A conversion data holding unit for holding a conversion value corresponding to a transmission destination address of the ATM cell; a common bus connected to the buffer circuit, the header conversion circuit, and the conversion data holding unit, which are included in the ATM cells received by the buffer circuit; A data communication device comprising: a sequence control unit for controlling a sequence for extracting a value corresponding to the destination address from the destination address via the common bus and supplying the value to the header conversion circuit. .