JPH10224206A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that improves a noise margin of a path transistor(TR) logic circuit and a drop in an operating speed. SOLUTION: A buffer circuit 2 is provided to an input side of a path transistor(TR) logic circuit 1, and a buffer circuit 3 is provided to an output side of the path transistor(TR) logic circuit 1. Each of the buffer circuits 2, 3 is made up of a CMOS logic circuit. The path TR logic circuit 1 is provided with plural NMOS TRs 4, 5, 6,... and is made by connecting the NMOS TRs in series. A threshold of the NMOS TRs is set lower than that of the TRs of the buffer circuits 2, 3. Then an increase portion in a threshold voltage of the NMOS TRs 4, 5, 6,... due to a substrate effect is cancelled each other, and a noise margin and an operating speed are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit composed of MOS transistors, and more particularly, to a semiconductor integrated circuit including a MOS transistor.
The present invention relates to a semiconductor integrated circuit in which a MOS logic circuit and a pass transistor logic circuit are mixed, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a CMOS logic circuit, when data of the logic circuit changes, that is, when a PMOS transistor and an NMOS transistor are switched, a direct current (hereinafter referred to as a through current) flows. Based power accounts for the majority of its power consumption.

On the other hand, a pass transistor logic circuit, which has attracted attention in recent years, has a structure in which each transmission path is switched according to an input signal, and signals on these transmission paths are selectively transmitted. Does not exist, and the power consumption can be significantly reduced as compared with the CMOS logic circuit.

However, in the case of a pass transistor logic circuit, since a plurality of transistors are connected in series, the pass transistor logic circuit is easily affected by the body effect. In other words, the body effect means that when the voltage between the source and the substrate of the transistor increases, the effective threshold value increases with this, and the level of the signal output from the transistor decreases. When each transistor is connected in series like a transistor logic circuit, some of them are separated from the substrate, and the voltage between the source and the substrate increases, so that the level of the output signal is significantly reduced by the substrate effect. Suru ("CMOS V" issued by Maruzen Co., Ltd.
Principle of LSI Circuit Design ”on page 33).

For example, in the case of a pass transistor logic circuit as shown in FIG. 12, when a high level signal is applied to the source tg101 of the NMOS transistor 101, the high level signal applied to the gate tg101 is transmitted to the drain td101. Output from The level of this output signal decreases by the effective threshold voltage Vtnx of transistor 101. Such a decrease in the level of the output signal similarly occurs in the next-stage transistor, and the voltage between the source and the substrate of the transistor increases in the subsequent stage. And the level of the output signal is greatly reduced.

In order to compensate for such a decrease in the output signal level, for example, an inverter, a latch, a sense amplifier, etc. composed of a CMOS logic circuit may be added to the pass transistor logic circuit (refer to "Low-power LSI" published by Nikkei BP). Technical White Paper ”, Nikkei Microdevices, pp. 98-104).

As a method for minimizing the body effect, a method of lowering the threshold value of a transistor in a pass transistor logic circuit to 0 V has been proposed (“A 3.8 ns CMOS 16 × 16-b Multiplier Using Compleme”).
tary Pass-Transistor-Logic '' K.Yano and others IEEE Journal
Of Solid-State Circuits.Vol125.No2.April1990P388-
395).

[0008]

However, in the above-mentioned conventional method, the lowering of the level of the output signal of the pass transistor logic circuit is only compensated for by a CMOS logic circuit provided externally, and the above-mentioned problem is caused by the substrate effect. It does not solve the reduction in noise margin inside the pass transistor logic circuit.

For example, assume that the signal applied to the gate tg101 of the transistor 101 in FIG. 12 is as shown in FIG. The voltage of the signal in FIG. 13A is the effective threshold voltage Vtnx of the transistor 101 (the transistor 10
1 (the threshold voltage Vt + the threshold voltage increase Vα caused by the body effect), the transistor 101 is turned on, and the signal shown in FIG. 13B is transmitted to the next transistor 102. Is done.

Here, assuming that the power supply voltage of the pass transistor logic circuit is Vdd and the noise level is Vih, the noise margin of the output signal of the transistor 101 is obtained by subtracting the effective threshold Vtnx and the noise level Vih from the power supply voltage Vdd. And is expressed by the following equation (1).

Vdd−Vtnx−Vih = Vdd− (Vt + Vα) −Vih (1) As is apparent from the equation (1), the noise margin decreases as the threshold voltage increase Vα due to the substrate effect increases. I do.

Such a decrease in the noise margin inside the pass transistor logic circuit is not improved by a conventional inverter, latch, sense amplifier, etc. connected outside the pass transistor logic circuit.

Further, the conventional countermeasure does not solve another problem in the pass transistor logic circuit caused by the body effect, that is, a reduction in operation speed.

The decrease in the operation speed is caused by each delay time generated between the transistors of the pass transistor logic circuit, and is expressed as the sum of these delay times.

For example, the rising time t of the signal shown in FIG.
Assuming that the time from 1 to the rising time t2 of the signal in FIG. 13B is the delay time between the transistors 101 and 102, this delay time is determined by the voltage of the signal in FIG. It is the sum of the time tnx required to reach Vtnx and the signal propagation time td between the transistors 101 and 102. The former time tnx is a time th until the voltage of the signal in FIG. 13A reaches the threshold voltage Vt of the transistor 101, and the voltage of this signal further increases the threshold voltage Vt.
From the time t until the voltage reaches the effective threshold voltage Vtnx. Therefore, this delay time is represented by the following equation (2).

Tnx + td = (th + tα) + td (2) Since such a delay time is generated for each of the plurality of pass transistor logic circuits, when the respective delay times are integrated, the delay time is input to the last transistor. The signal shown in FIG.
As shown in FIG. 3C, the operation is very delayed, and this delay significantly reduces the operation speed.

Regardless of which of the preceding times th, tα, td becomes longer, the delay time becomes longer. For example, even if the time tα becomes longer, the delay time becomes longer. This time t
α is the time required for the signal voltage in FIG. 13A to reach the effective threshold voltage Vtnx from the threshold voltage Vt,
The larger the increase Vα of the threshold voltage due to the substrate effect,
This time tα becomes longer.

That is, in the pass transistor logic circuit, the time tα becomes longer due to the body effect, so that the delay time between the transistors becomes longer, and the operation speed of this logic circuit decreases.

Further, in order to solve such a problem, there has been proposed a method of applying the above-described 0V threshold voltage transistor to a pass transistor portion. As a result, the substrate effect can be minimized, and the problems of the noise margin and the delay time of the circuit can be solved. However, by setting the threshold value of the pass transistor portion to 0 V,
An off-leak current of the transistor occurs, and as a result, the low current consumption operation performance, which is one of the features of the pass transistor logic circuit, deteriorates.

Accordingly, the present invention is to solve such a problem of the prior art, and it is intended to improve the noise margin and the operating speed of the pass transistor logic circuit while preventing the power consumption from increasing. It is an object to provide a circuit and a method for manufacturing the circuit.

[0021]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention relates to a semiconductor integrated circuit comprising MOS transistors, in which a CMOS logic circuit and a pass transistor circuit coexist. The threshold value is set lower than the threshold value of the transistor of the CMOS logic circuit within a range where the off-leak current of the transistor does not matter.

According to the present invention, the threshold value of the transistor of the pass transistor logic circuit is lower than the threshold value of the transistor of the CMOS logic circuit. In this case, if the pass transistor logic circuit is formed of, for example, an NMOS transistor, the high-level output of this transistor is prevented from lowering (in the case of a PMOS transistor, the low-level output is prevented from rising), so that the noise margin is increased. Also,
Since the output of the transistor of the pass transistor logic circuit quickly reaches the threshold value of its input, the delay time generated between each transistor can be reduced as compared with the conventional circuit, and the operation of the logic circuit can be performed faster. Become.

Further, a buffer circuit or a gate circuit composed of a CMOS logic circuit may be connected to the input / output side of the pass transistor logic circuit. In this case, the input / output level of the pass transistor logic circuit can be supplemented by the CMOS logic circuit.

Further, at this time, the threshold value of the NMOS transistor of the CMOS buffer circuit is also reduced to a threshold value equivalent to that of the pass transistor logic circuit. Circuit operation becomes possible.

If the buffer circuit or the gate circuit is provided with a means for interrupting the signal path of the pass transistor logic circuit when the pass transistor logic circuit is not operating, the non-conductive transistor in the pass transistor logic circuit can be used. In the case where a leakage current at the time of turning off occurs, the leakage current flowing through the circuit can be suppressed.

In order to manufacture this semiconductor integrated circuit, the threshold value of the transistor of the pass transistor logic circuit is set by not performing ion implantation for controlling the threshold value. The threshold may be set by ion implantation for threshold control.

[0027]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the semiconductor integrated circuit of the present invention. In this semiconductor circuit, a buffer circuit 2 is provided on the input side of the pass transistor logic circuit 1, and a buffer circuit 3 is also provided on the output side. Each of the buffer circuits 2 and 3 is composed of a CMOS logic circuit.

The pass transistor logic circuit 1 includes a plurality of N
MOS transistors 4, 5, 6,...
An OS transistor is connected. The threshold value Vtw of these NMOS transistors is set lower than the threshold value Vt of each transistor of each of the buffer circuits 2 and 3 which are CMOS logic circuits.

In a conventional semiconductor integrated circuit,
The threshold value of the transistor of the pass transistor logic circuit is matched with that of the transistor of the CMOS logic circuit.

Now, through the buffer circuit 2, the NMOS
When a high-level signal is applied to the source ts4 of the transistor 4, the high-level signal applied to the gate tg4 is transmitted to the drain td4 and output therefrom.

Assuming that the signal applied to the gate tg4 of the transistor 4 is as shown in FIG. 2A, this signal is generated by the effective threshold value Vtnxw of the transistor 4 (the threshold value Vtw of the transistor 4 + the substrate effect). When the threshold voltage increases (Vα), the transistor 4 is turned on, and the signal shown in FIG. 2B is transmitted to the transistor 5 in the next stage.

Here, assuming that the power supply voltage of the pass transistor logic circuit 1 is Vdd and the noise level is Vih, the noise margin of the output signal of the transistor 4 is the power supply voltage Vd.
This is a value obtained by subtracting the effective threshold value Vtnxw and the noise level Vih from dd, and is represented by the following equation (3).

Vdd−Vtnxw−Vih = Vdd− (Vtw + Vα) −Vih (3) It is apparent from comparing this equation (3) with the equation (1) representing the noise margin of the transistor inside the conventional pass transistor logic circuit. Thus, the difference between the two is in the threshold value Vtw of the transistor in this embodiment and the threshold value Vt of the conventional transistor. Since Vtw <Vt, the noise margin of the transistor in this embodiment is This means that the noise margin of the transistor is improved by Vt-Vtw.

Assuming that the time from the rise time t1 of the signal in FIG. 2A to the rise time t2 of the signal in FIG. 2B is the delay time between the transistors 4 and 5, this delay time is , The voltage of the signal shown in FIG.
Is reached, and the signal propagation time td between the transistors 4 and 5 is the sum of the time tnxw and the signal propagation time td. During the former time tnxw, the signal voltage of FIG.
And the time tα until the voltage of this signal further increases from the threshold voltage Vtw to the effective threshold voltage Vtnxw. This delay time is shown in the following equation (4).

Tnxw + td = (thw + tα) + td (4) As is clear from comparison between the equation (4) and the equation (2) representing the delay time between the conventional transistors, the difference between the two is as follows.
In this embodiment, the time thw until the signal of FIG. 2A reaches the threshold voltage Vtw of the transistor and the conventional signal of FIG.
time t until the time t is reached, and Vtw <
Since Vt, and therefore, thw <th, the delay time between the transistors in this embodiment is shorter than the conventional delay time between the transistors by th-thw.

The reduction of the delay time is performed every time the delay time occurs, and the signal input to the last transistor is
The result is as shown in FIG. As is clear from comparison between the signal of FIG. 2C and the conventional signal of FIG. 13C, the operation speed of this embodiment is sufficiently improved as compared with the conventional example.

That is, in the pass transistor logic circuit 1 of this embodiment, the threshold voltage Vtw of the transistor is made lower than the threshold voltage Vt of the conventional transistor, and the increase in the threshold voltage due to the body effect is obtained. Vα is canceled out, thereby improving the noise margin and the operation speed.

By the way, if the threshold value of the CMOS logic circuit is lowered similarly to the pass transistor logic circuit, the through current at the time of a signal change will increase. On the contrary,
In the present invention, the threshold value of each transistor of each of the buffer circuits 2 and 3 composed of a CMOS logic circuit is set to a normal value larger than that of each of the transistors of the pass transistor logic circuit 1. A few
It is difficult for a leak current to flow.

FIG. 7 shows each of the buffer circuits 2, 3 shown in FIG.
This circuit configuration is the circuit 2 of both,
3 are common. In this circuit, when a degraded high-level signal is input from the pass transistor logic circuit,
The level of the signal is recovered by the PMOS transistor 25, and the signal is output to the next stage through the buffer circuits 23 and 24.

However, each of the buffer circuits 2 and 3 does not need to have a configuration as shown in FIG. 7, but may be a normal CMOS logic circuit. There is no problem even if the buffer circuits 2 and 3 have different circuit configurations.

FIG. 3 shows a configuration of a buffer circuit that is effective when the threshold value of the pass transistor logic circuit is low and a leakage current at the time of off flows. Here, a signal is input through the input transistor 11, and this signal is input to the first transistor.
This signal is output after being inverted twice by the second buffer circuits 12 and 13 and restored.

The inverted output of the first buffer circuit 12 is the inverted input of the inverter 14, and the output of the inverter 14 is input to the first buffer circuit 12. As a result, the level of the signal output from the first buffer circuit 12 is held, and accordingly, the level of the output signal of the second buffer circuit 13 is also held.

The input transistor 11 and the output transistor 15 are switched according to the CTRL level. When transmitting a signal, the input transistor 11 and the output transistor 15 are turned on, and the first and second buffer circuits 12 and 13 turn on the input transistor 11 and the output transistor 15. When the level of the signal is held, the input transistor 11 and the output transistor 15 are turned off, and the buffer circuits 2 and 3 are disconnected from the pass transistor logic circuit 1.

If the buffer circuits 2 and 3 having such a configuration are connected to the input / output side of the pass transistor logic circuit 1, when the data of the pass transistor logic circuit 1 does not change, that is, when the pass transistor logic circuit is not operating, this pass transistor Since the logic circuit 1 is disconnected from the signal transmission path, the leakage current of the logic circuit 1 can be completely cut off.

In some cases, a power supply or a ground potential is directly connected to a leak portion of the pass transistor logic circuit 1. In this case, the leakage current can be cut off by inserting an NMOS transistor corresponding to the transistor 15 of FIG. 3 between the power supply potential or the ground potential and the first-stage pass transistor.

Further, it is possible to use a depletion type transistor as each transistor of the pass transistor logic circuit 1. In the case of this depletion type transistor, the signal path is switched between a low resistance and a high resistance, thereby transmitting and blocking a signal.

Further, in the pass transistor logic circuit 1, the first stage NMOS transistor 4 is switched to the last stage NM
If there is an OS transistor n, the threshold values of the transistors 4 and n of the first and last stages are set to be equal to those of the transistors of the CMOS logic circuit, and the threshold values of the second stage and one stage before the last stage are set. Each of the transistors 5 to (n-
The threshold value of 1) may be lower than the threshold value of the transistor of the CMOS logic circuit. As a result, the through current flowing through the first and last transistors 4 and n at the time of a signal change is reduced, and accordingly, the through current of the pass transistor logic circuit 1 is also reduced.

In the semiconductor device of the present invention, as described above, the threshold value of the transistor of the pass transistor logic circuit is lower than that of the transistor of the CMOS logic circuit, which is different from the conventional device. different.

Also, the above-mentioned document “A 3.8ns CMOS 16x16-b
..], The threshold value of the transistor is set to 0 V. In this case, as described above, the off-leak current of the transistor becomes a problem. On the other hand, in the present invention, the circuit performance can be improved without deteriorating the power consumption by setting the threshold value of the transistor low enough to prevent the off-leak current from flowing.

For this purpose, for example, a method of applying a native transistor (NativeTransister) as a transistor of a pass transistor logic circuit can be considered.

First, a cross-sectional structure of a general NMOS transistor is shown in FIG. Here, the thin P of the ion node
On the field 16, N-type ions are implanted into the source / drain regions 17, and further, a p-region 19 below the gate 18 is used to control the threshold value of the transistor.
P-type ions are implanted.

On the other hand, in the native transistor, as shown in FIG. 5, no P-type ions are implanted below the gate 18. As a result, the region under the gate 18 of this transistor is a thin region of the P-type ion node, so that a transistor having a low threshold value can be realized.

Further, when the off-state leakage current does not flow in the transistor whose threshold value has been lowered, the first NMOS transistor of the buffer circuit of the succeeding stage is also formed of a transistor having a low threshold value. The input inversion level of the circuit can be reduced, and as a result, operation at a lower voltage is possible.

[0055]

FIG. 6 shows a semiconductor device used to confirm the effects of the present invention by HSPICE evaluation. Here, the buffer circuits 21-1 to 21-9 and the pass transistor logic circuits 22-1 to 22-8 are connected alternately.

Each of the buffer circuits 21-1 to 21-9 has a configuration as shown in FIG.
3, 24 and a transistor 25, and the input can be held.

In this circuit, the sources of all the pass transistors are set to either the power supply potential or the ground potential in order to simplify the pass transistor logic circuit. Is connected to a pass transistor logic circuit at the preceding stage, and a signal propagated through these circuits is input.

In the HSPICE evaluation, the threshold values of the transistors of the pass transistor logic circuits 22-1 to 22-8 are set to those of the transistors of the CMOS logic circuit (the threshold value of the Pch transistor is 0.6 V, Nch
The case where the threshold value of the transistor is set to be equal to 0.6 V) and the case where the threshold value of the transistor of each of the pass transistor logic circuits 22-1 to 22-8 is C
0.2 lower than that of the MOS logic circuit transistor
V was set.

The results are shown in FIGS. 8, 9, 10 and 11.
Shown in In the graph of FIG. 8, the power consumption of this embodiment is compared with that of the conventional example, and the power consumption of this embodiment is slightly lower than that of the conventional example. This suggests that the leak current has not increased.

In the graph of FIG. 9, the rise delay time is shown in comparison, and the rise time of this embodiment is shorter than that of the conventional example, and when the power supply voltage Vdd = 2 V, the improvement is 63%. I was able to. The graph of FIG. 10 shows the fall delay time in comparison.

In the graph of FIG. 11, the high-level signal voltage is compared. In this embodiment, the signal voltage is higher than that of the conventional example.
38V could be raised.

[0062]

As described above, according to the present invention,
Since the threshold value of the transistor of the pass transistor logic circuit is lower than the threshold value of the transistor of the CMOS logic circuit and the effective threshold value of the transistor of the pass transistor logic circuit is kept low, the noise margin can be increased. . In addition, since the output of the transistor of the pass transistor logic circuit quickly reaches the threshold value of the input, the delay time generated between the transistors can be reduced as compared with the conventional circuit, and Moves faster.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 shows each signal in the circuit of FIG. 1;
(A) shows the gate input of the transistor 4, (b) shows the source input of the transistor 5, and (c) shows the input of the last transistor.

FIG. 3 is a circuit diagram illustrating the configuration of each buffer circuit in the circuit of FIG. 1;

FIG. 4 is a cross-sectional view illustrating an NMOS transistor.

FIG. 5 is a sectional view showing a native transistor.

FIG. 6 is a circuit diagram showing a semiconductor device used for confirming the effect of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a buffer circuit in the circuit of FIG. 6;

FIG. 8 is a graph showing power consumption in the circuit of FIG. 6;

FIG. 9 is a graph showing a rise delay time in the circuit of FIG. 6;

FIG. 10 is a graph showing a fall delay time in the graph of FIG. 6;

FIG. 11 is a graph showing a high-level signal voltage in the graph of FIG. 6;

FIG. 12 is a circuit diagram illustrating a conventional semiconductor integrated circuit;

FIG. 13 shows signals in the circuit of FIG. 12;
(A) shows the gate input of the transistor 101,
(B) shows the source input of the transistor 102,
(C) shows the input of the last transistor

[Explanation of symbols]

 Reference Signs List 1 pass transistor logic circuit 2 buffer circuit 3 buffer circuit 4, 5, 6 NMOS transistor 11 input transistor 12 first buffer circuit 13 second buffer circuit 14 transistor

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Shigenori Imai 22-22, Nagaikecho, Abeno-ku, Osaka City, Osaka Inside Sharp Corporation (72) Inventor Toshinori Omi 22-22, Nagaikecho, Abeno-ku, Osaka-shi, Osaka Incorporated (72) Inventor Akio Kitade 22-22 Nagaikecho, Abeno-ku, Osaka City, Osaka Within Sharp Corporation (72) Inventor Kazuo Taki 4-6 Oreimachi, Tarumizu-ku, Kobe, Hyogo Prefecture

Claims (6)

[Claims] 1. A semiconductor device comprising: a MOS transistor;
In a semiconductor integrated circuit in which a CMOS logic circuit and a pass transistor circuit are mixed, the threshold value of the transistor of the pass transistor logic circuit is lower than the threshold value of the transistor of the CMOS logic circuit within a range where the off-leak current of the transistor does not matter. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein a buffer circuit or a gate circuit composed of a CMOS logic circuit is connected to an input / output side of the pass transistor logic circuit. 3. The semiconductor integrated circuit according to claim 2, wherein the buffer circuit or the gate circuit includes means for cutting off a signal path of the pass transistor logic circuit when the pass transistor logic circuit is not operating. 4. The semiconductor integrated circuit according to claim 2, wherein the threshold value of the NMOS transistor of the first-stage buffer circuit or gate circuit disposed at the output stage of the pass transistor logic circuit is set to another CMOS logic circuit. Semiconductor integrated circuit whose threshold value is lower than the threshold value. 5. The semiconductor integrated circuit according to claim 1, wherein the threshold values of the first and last transistors of the pass transistor logic circuit are set to be equal to those of the transistors of the CMOS logic circuit. A semiconductor integrated circuit in which the threshold value of each transistor from the second stage of the transistor logic circuit to the stage immediately before the last stage is lower than the threshold value of the transistor of the CMOS logic circuit. 6. The manufacturing method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the threshold value of the transistor of the pass transistor logic circuit is set by not performing ion implantation for controlling the threshold value. A method of manufacturing a semiconductor integrated circuit, wherein a threshold value of a transistor of a CMOS logic circuit is set by ion implantation for controlling the threshold value.