JPH10222982A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a power consumption by reducing a charge/discharge current for the gate capacity of a transistor for bit line pull-up for constituting a write recovery circuit in a semiconductor storage for transmission by making complementary write data. SOLUTION: When the potential of a bit line BL is VCC and the potential of the bit line/BL is 0[V] at the time of write recovery, only a pMOS transistor 8 is driven out of pMOS transistors 7 and 8 and a write recovery is performed. Then, when the potential of the bit line BL is 0[V] and the potential of the bit line/BL is VCC, only the pMOS transistor 7 out of the pMOS transistors 7 and 8 is driven for write recovery.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device which complements and transmits externally applied write data.

2. Description of the Related Art Low-power semiconductor memory devices are needed to extend the battery life of portable equipment and to keep heat generation within the allowable range of plastic packages even when the circuit scale is increased. Is increasing.

[0003]

2. Description of the Related Art FIG.
Access memory (hereinafter referred to as static RAM)
FIG. 6 is a circuit diagram showing a main part of one example. In FIG. 6, reference numeral 1 denotes a memory cell, 1A and 1B denote data input / output nodes of the memory cell 1, and BL and / BL denote bit lines.

[0004] Reference numeral 2 denotes a pMOS transistor having a gate width of, for example, 7 μm which forms a load element of the bit line BL. The source is connected to a VCC power supply line 4 for supplying a power supply voltage VCC, and the drain is connected to the bit line BL. It is connected to the.

The reference numeral 3 designates a pM which makes the gate width of the load element of the bit line / BL the same as that of the pMOS transistor 2.
The OS transistor has a source connected to the VCC power supply line 4 and a drain connected to the bit line / BL.

Reference numeral 5 denotes a write recovery circuit,
Numeral 6 denotes an inverter for inverting a write recovery signal WR for controlling a write recovery operation. The write recovery signal WR has a write recovery period of a high logic level (hereinafter referred to as H level) and a period other than write recovery. Is set to a low logic level (hereinafter, referred to as L level).

Reference numeral 7 denotes a bit line pull-up pMOS transistor having a gate width of, for example, 18 μm provided corresponding to the bit line BL. The source is connected to the VCC power supply line 4 and the drain is connected. It is connected to the bit line BL, and is configured so that ON (ON) and OFF (OFF) are controlled by the output of the inverter 6.

Reference numeral 8 denotes a bit line pull-up pMOS transistor identical to the pMOS transistor 7 provided corresponding to the bit line / BL. The source is connected to the VCC power supply line 4, and the drain is a bit. Line / B
L and is configured to be turned on and off by the output of the inverter 6.

The static RAM constructed as described above
Since the power supply voltage VCC is supplied to the bit lines BL and / BL via the pMOS transistors 2 and 3 at the time of the read cycle, for example, when the memory cell 1 is selected, , One of the bit lines BL and / BL is maintained at the power supply voltage VCC, and the other potential is changed to the power supply voltage VC.
The voltage slightly drops from C, and a minute voltage difference between the bit lines BL and / BL generated at this time is amplified by a sense amplifier (not shown).

On the other hand, in a write cycle, for example, when the memory cell 1 is selected, the memory cell 1
Bit lines BL, / BL according to write data for
Is maintained at the power supply voltage VCC,
The other potential is set to the ground voltage 0 [V], and writing to the memory cell 1 is performed.

FIG. 7 is a waveform diagram for explaining the operation of the write / recovery circuit 5. The potential of the bit lines BL and / BL when the operation cycle changes from write cycle to read cycle A to read cycle B is shown. A change and write recovery signal WR is shown.

Here, the operation cycle is the read cycle A
In the read cycle A, the bit line BL is set to the power supply voltage VCC, and the bit line / BL is set to a voltage slightly lower than the power supply voltage VCC. At time B, for example, the bit line / BL is connected to the power supply voltage V
When the bit line BL is set to the voltage CC and slightly lowered from the power supply voltage VCC, the bit line / BL needs to be raised to the power supply voltage VCC in the read cycle B. This is performed by the pMOS transistor 3 which is the load element of the bit line / BL, and this is sufficient.

However, when the operation cycle shifts from the write cycle to the read cycle A, in the write cycle, for example, the bit line / BL is maintained at the power supply voltage VCC and the bit line BL is set to the ground voltage 0 [ V], and in the read cycle A, for example, the bit line BL is set to the power supply voltage VCC, and
If bit line / BL is set to a voltage slightly lower than power supply voltage VCC, it is necessary to raise bit line BL from 0 [V] to power supply voltage VCC during read cycle A.

This is referred to as pM which is a load element of the bit line BL.
In the case of using the OS transistor 2, the bit line BL cannot be raised to the power supply voltage VCC at high speed as shown by a two-dot chain line X, for example, due to its current driving capability, and the operation cycle becomes longer. If not, the bit line BL, /
A small voltage difference due to read data cannot be generated between the BLs, and the speed cannot be increased.

Therefore, in this static RAM, when shifting from a write cycle to a read cycle, the write recovery signal WR is set to H level with a predetermined period at the head of the read cycle as a write recovery period, and the output of the inverter 6 is set to L level. When the level and the pMOS transistors 7 and 8 are set to ON and the bit line BL is set to 0 [V], the bit line B is supplied via the pMOS transistor 7 having a gate width larger than that of the pMOS transistor 2.
L, the potential of the bit line BL is rapidly raised to the power supply voltage VCC. When the bit line / BL is set to 0 [V], the pMOS transistor 8 having a gate width larger than that of the pMOS transistor 3 is turned on. The bit line / BL is charged via the bit line and the potential of the bit line / BL is rapidly increased to the power supply voltage VCC.

[0016]

However, in this static RAM, at the time of write recovery, a bit line (bit line / B in the example of FIG.
L), a pMOS transistor for pulling up a bit line, that is, a pMOS transistor that does not need to perform a pull-up operation (pMOS transistor in the example of FIG. 7).
Even in the case of a pMOS transistor that drives even the MOS transistor 8) and does not need to perform the pull-up operation, the gate capacitance is discharged at the time of write recovery, and thereafter, when the write recovery period ends, the gate capacitance is discharged. Will be charged.

Here, the pMOS transistors 7 and 8 for pulling up the bit lines constituting the write recovery circuit 5
Since a large gate width is formed, a large amount of current flows during charging and discharging, which has been one of the causes of increasing power consumption.

Some static RAMs perform input / output of a plurality of bits of data in parallel. In such a static RAM, a plurality of data input buffers and a plurality of data input buffers are provided in correspondence with write data having a plurality of bits. , A plurality of write data line pairs are provided. In the conventional static RAM, these plurality of data input buffers are configured so that activation and inactivation are uniformly controlled by one write control signal. It had been.

In such a static RAM, when x + y data input buffers are provided, for example, of the stored x + y bit data, the upper x bit data is not changed, and the lower y bit is not changed. If you want to change only the data of
It is necessary to read the bit data, rewrite the lower n bits with the ALU, and then write the x + y bit data again.

In this example, if only the lower y bits can be written, there is no need to drive a write data line pair corresponding to a bit that does not need to be rewritten. Power consumption can be reduced.

In view of the above, the present invention can reduce power consumption by reducing the charge / discharge current for the gate capacitance of the bit line pull-up transistor constituting the write recovery circuit. It is a first object of the present invention to provide a semiconductor memory device in which power consumption can be reduced by reducing charge / discharge current for a write data line pair. This is the purpose of 2.

[0022]

According to a first aspect of the present invention, there is provided a semiconductor memory device according to the first aspect, in which a memory cell is connected, and at the time of a write cycle, one of potentials according to write data. A bit line pair including first and second bit lines, a first load element connected between a power supply line for supplying a positive power supply voltage and the first bit line;
In a semiconductor memory device having a second load element connected between the power supply line and a second bit line, a current input terminal is connected to the power supply line, and a current output terminal is connected to the first bit line. A connected first bit line pull-up transistor, a second bit line pull-up transistor having a current input terminal connected to the power supply line, and a current output terminal connected to the second bit line. During write recovery, of the first and second bit line pull-up transistors,
A write recovery circuit including a bit line pull-up transistor driving circuit that drives only the bit line pull-up transistor connected to the bit line whose potential is lowered is provided.

According to the first aspect of the present invention, in the first aspect, at the time of write recovery, the gate capacitance of the bit line pull-up transistor connected to the bit line whose potential has been lowered for write recovery operation, and Charge / discharge of the gate capacitance of some or all of the transistors constituting the bit line pull-up transistor drive circuit is performed.

However, the transistors constituting the bit line pull-up transistor drive circuit can have gate widths smaller than the gate widths of the first and second bit line pull-up transistors. The charge / discharge current for the gate capacitance can be reduced as compared with the case where both the second bit line pull-up transistors are driven.

According to a second aspect of the present invention, there is provided a semiconductor memory device according to the first aspect, wherein the transistor drive circuit for pulling up a bit line comprises a first data line including a first bit line. By processing the potential of the transmission path, the potential of the second data transmission path including the second bit line, and the write recovery signal for controlling the write recovery operation, the first and second bit line pulls are processed. It is configured to drive an up transistor.

According to a third aspect of the present invention, in the semiconductor memory device according to the second aspect, the transistor drive circuit for pulling up the bit line includes a potential of the second data transmission path, NAND processing the recovery signal with the first NAND circuit for driving the first bit line pull-up transistor, the first data transmission path potential, and the write recovery signal, Second
And a second NAND circuit for driving the bit line pull-up transistor.

According to a fourth aspect of the present invention, in the semiconductor memory device according to the fourth aspect, in the second aspect, the transistor drive circuit for pulling up the bit line has a source connected to the power supply line and a drain connected to the power supply line. A first p-channel insulated gate field effect transistor connected to the first output node and having a gate to which a write recovery signal is applied; a drain connected to the first output node; and a source connected to the first data transmission line. A first n-channel insulated gate field effect transistor having a gate applied with a write recovery signal, a source connected to a power supply line, a drain connected to a second output node, and a gate connected to a gate. A second p-channel insulated gate field effect transistor to which a write recovery signal is applied; a drain connected to the second output node; and a second data transmission connected to the source. And a second n-channel insulated gate field effect transistor having a gate to which a write recovery signal is applied, wherein the first and second output nodes have first and second output nodes according to the voltage of the first and second output nodes. It is configured to drive a bit line pull-up transistor.

In a fifth aspect of the present invention, a semiconductor memory device according to the fifth aspect is provided with first, second,... Provided corresponding to n bits (however, an integer of 2 or more) of write data. An n-th data input buffer and first, second,... Driven by these first, second,.
.. in the semiconductor memory device having the n-th write data line pair, the first, second,..., N-th data input buffers are respectively controlled by the first, second,. The activity and the inactivity are controlled.

According to the fifth aspect of the present invention, when changing data of an arbitrary bit out of the stored n-bit data, only an arbitrary data input buffer is activated and an arbitrary write data is changed. By driving only the line pairs, any bit data can be rewritten. Therefore, once the n bit data is read, the ALU is used to change the arbitrary bit data, and then the n bit data is written again. There is no need to perform the operation of doing so.

In the present invention, the sixth invention (semiconductor memory device according to claim 6) is a semiconductor device according to the fifth invention, wherein the i-th semiconductor memory device is provided.
When the data input buffer of i = 1, 2,... n) is activated in a write cycle, the data input buffer constitutes the i-th write data line pair according to the applied write data. Is maintained at H level, the other write data line forming the i-th write data line pair is at L level, and the write data line is inactive.
One and the other write data lines constituting the i-th write data line pair are configured to be maintained at the H level.

According to a seventh aspect of the present invention, in the semiconductor memory device according to the seventh aspect, in the sixth aspect, the i-th data input buffer comprises a first inverter for inverting applied write data and , One end is connected to the first inverter,
The first switch element, which is turned on when the i-th write control signal and the data transfer signal are at the active level and turned off when the data transfer signal is at the inactive level, and the input terminal of the second inverter are connected to the second switch. Connected to the other end of the first switch element, the first input terminal of the first two-input NOR circuit is connected to the output terminal of the second inverter, and the first two-input N
An output terminal of the OR circuit is connected to an input terminal of a second inverter, a first latch circuit to which a data line reset signal is applied to a second input terminal of a first two-input NOR circuit, and one end connected to the first latch. A third inverter connected to the output terminal of the third inverter and one end connected to the third inverter, and turned on when the i-th write control signal and the data transfer signal are at the active level, and the data transfer signal is inactive. A second switch element that is turned off in the case of a level and an input terminal of a fourth inverter are connected to the other end of the second switch element, and a first input of a second two-input NOR circuit having two inputs is connected. The input terminal is connected to the output terminal of the fourth inverter, and the second two-input NO
Connecting the output of the R circuit to the input of the fourth inverter;
And a second latch circuit to which a data line reset signal is applied to a second input terminal of the second two-input NOR circuit.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment to a third embodiment of the present invention will be described with reference to FIGS. 1 to 5, taking an example in which the present invention is applied to a static RAM.

FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention. In the first embodiment of the present invention, a conventional static RAM shown in FIG. 6 is provided. A write recovery circuit 15 having a circuit configuration different from that of the write recovery circuit 5 is provided, and the other configuration is the same as that of the conventional static RAM shown in FIG.

The write recovery circuit 15 provided in the first embodiment of the present invention is different from the write recovery circuit 5 shown in FIG.
, A bit line pull-up transistor drive circuit 1 comprising two NAND circuits
6 and the other configuration is the same as that of the write recovery circuit 5 shown in FIG.

In the bit line pull-up transistor drive circuit 16, WD and / WD are write data line pairs driven complementarily by a data input buffer for taking in externally applied write data, and WD is via a write amplifier. Is a write data line connected to the bit line BL, and / WD is a write data line connected to the bit line / BL via a write amplifier.

Numeral 17 denotes a NAND operation of the write recovery signal WR and the potential of the write data line / WD to perform pM
A NAND circuit for driving the OS transistor 7;
8, 19 are pMOS transistors, and 20, 21 are nMO transistors.
It is an S transistor.

The pMOS transistor 18 has a source connected to the VCC power supply line 4, a drain connected to the output node 22, and a gate connected to the write recovery signal WR.
Is applied, and ON / OFF is controlled by the write recovery signal WR. The output node 22 is connected to the gate of the pMOS transistor 7.

The pMOS transistor 19 has a source connected to the VCC power supply line 4, a drain connected to the output node 22, a gate connected to the write data line / WD, and turned on by the potential of the write data line / WD. Off is controlled.

The nMOS transistor 20 has a drain connected to the output node 22, a gate to which a write recovery signal WR is applied, and a write recovery signal WR.
Is controlled to turn on and off.

The drain of the nMOS transistor 21 is connected to the source of the nMOS transistor 20.
The source is connected to the ground line, and the gate is the write data line /
WD and is configured to be turned on and off by the potential of the write data line / WD.

Reference numeral 23 denotes a write recovery signal WR
And the potential of the write data line WD by NAND processing
A NAND circuit for driving the MOS transistor 8;
24 and 25 are pMOS transistors, 26 and 27 are nM
OS transistor.

The pMOS transistor 24 has a source connected to the VCC power supply line 4, a drain connected to the output node 28, and a gate connected to the write recovery signal WR.
Is applied, and ON / OFF is controlled by the write recovery signal WR. The output node 28 is connected to the gate of the pMOS transistor 8.

The pMOS transistor 25 has a source connected to the VCC power supply line 4, a drain connected to the output node 28, a gate connected to the write data line WD, and turned on / off by the potential of the write data line WD. It is configured to be controlled.

The nMOS transistor 26 has a drain connected to the output node 28, a write recovery signal WR applied to the gate, and a write recovery signal WR.
Is controlled to turn on and off.

The drain of the nMOS transistor 27 is connected to the source of the nMOS transistor 26,
The source is connected to the ground line, and the gate is connected to the write data line W
D, and is turned on by the potential of the write data line WD,
Off is controlled.

In the first embodiment of the present invention configured as described above, the write recovery signal WR = 0 [V] in the write cycle.

As a result, in the NAND circuit 17,
pMOS transistor 18 = ON, nMOS transistor 20 = OFF, potential of output node 22 = VCC, NA
In the ND circuit 23, the pMOS transistor 24 =
ON, nMOS transistor 26 = OFF, potential of output node 28 = VCC, pMOS transistor 7 =
OFF, pMOS transistor 8 = OFF.

On the other hand, at the time of write recovery,
The write recovery signal WR is set to VCC, and in the NAND circuit 17, the pMOS transistor 18 = OF
F, nMOS transistor 20 = ON, NAND circuit 2
3, pMOS transistor 24 = OFF, n
MOS transistor 26 is turned on.

As a result, when the operation cycle shifts from the write cycle to the read cycle, at the time of the write cycle, the potential of the bit line BL is set to VCC and the potential of the bit line / BL is set to 0 [V], that is, When the potential of the write data line WD is set to VCC and the potential of the write data line / WD is set to 0 [V], at the time of write recovery,
In the NAND circuit 17, the pMOS transistor 1
9 = ON, nMOS transistor 21 = OFF, NAN
In the D circuit 23, the pMOS transistor 25 = O
The FF and the nMOS transistor 27 are turned on.

Therefore, the potential of the output node 22 of the NAND circuit 17 becomes VCC, the potential of the output node 28 of the NAND circuit 23 becomes 0 [V], and the pMOS transistor 7
= OFF is maintained and the pMOS transistor 8
= ON, and the bit line / BL at 0 [V] is pulled up during the write cycle.

When the write recovery period ends, the write recovery signal WR is set to 0 [V], and NA
In the ND circuit 17, the pMOS transistor 18 =
ON, nMOS transistor 21 = OFF, potential of output node 22 = VCC, pMOS transistor 7 =
While maintaining the off state, in the NAND circuit 23,
The pMOS transistor 24 = ON, the nMOS transistor 26 = OFF, the potential of the output node 28 = VCC, and the pMOS transistor 8 = OFF.

On the other hand, in the write cycle, the potential of the bit line BL = 0 [V] and the potential of the bit line / BL = V
CC, that is, the potential of the write data line WD =
When 0 [V] and the potential of the write data line / WD are set to VCC, the pMOS transistor 19 is turned off and the nMO
In the S circuit 21 = ON and the NAND circuit 23, the pMOS transistor 25 = ON and the nMOS transistor 27 = OFF.

As a result, the potential of the output node 22 of the NAND circuit 17 becomes 0 [V], the potential of the output node 28 of the NAND circuit 23 becomes VCC, and the pMOS transistor 8 becomes
OFF is maintained and the pMOS transistor 7 =
It turns ON, and the bit line BL at 0 [V] is pulled up during the write cycle.

When the write recovery period ends, the write recovery signal WR is set to 0 [V], and NA
In the ND circuit 17, the pMOS transistor 19 =
ON, nMOS transistor 21 = OFF, potential of output node 22 = VCC, pMOS transistor 7 =
ON and at the same time, in the NAND circuit 23, pM
OS transistor 24 = ON, nMOS transistor 2
6 = OFF, the potential of the output node 28 = VCC, p
MOS transistor 8 = OFF is maintained.

As described above, in the first embodiment of the present invention, at the time of write recovery, the potential of the bit line BL = VC
C, when the potential of the bit line / BL is set to 0 [V], the gate voltage of the pMOS transistor 7 is maintained at VCC, and the gate voltage of the pMOS transistor 8 is changed from VCC → 0 [V] → VCC. In this case, of the pMOS transistors 7 and 8, only the gate capacitance of the pMOS transistor 8 is charged and discharged, and only the pMOS transistor 8 is driven to perform write recovery.

On the other hand, the potential of the bit line BL = 0
[V], when the potential of the bit line / BL is set to VCC, the gate voltage of the pMOS transistor 8 is set to VCC.
While changing the gate voltage of the pMOS transistor 7 from VCC → 0 [V] → VCC,
Of the transistors 7 and 8, only the gate capacitance of the pMOS transistor 7 is charged and discharged, and the pMOS transistor 7
Drive only to perform write recovery.

Incidentally, when the bit line / BL is write-recovered from 0 [V], the pMOS transistors 18, 19 and 24 and the nMOS transistors 20, 2
When it is necessary to charge / discharge the gate capacitances of 1 and 26 and write-recover the bit line BL from 0 [V],
It is necessary to charge and discharge the gate capacitances of the pMOS transistors 18, 24, 25 and the nMOS transistors 20, 26, 27.

However, the pMOS transistors 18, 1
9, 24, and the total gate width of the nMOS transistors 20, 21, 26 is smaller than the gate width of the pMOS transistor 8, and the pMOS transistors 18, 24, 2
5 and nMOS transistors 20, 26, 27 so that the total gate width is smaller than the gate width of pMOS transistor 7.
9, 24, 25 and nMOS transistors 20, 21,
It is possible to configure 26,27.

Therefore, according to the first embodiment of the present invention, the pMOS transistor 7 serving as the bit line pull-up transistor constituting the write recovery circuit 15,
The power consumption can be reduced by reducing the charge / discharge current for the gate capacitance of No. 8.

Second Embodiment FIG. 2 FIG. 2 is a circuit diagram showing a main part of a second embodiment of the present invention. The second embodiment of the present invention includes a light provided in the first embodiment of the present invention. A write recovery circuit 31 having a circuit configuration different from that of the recovery circuit 15 is provided, and the other configuration is the same as that of the first embodiment of the present invention.

The write recovery circuit 31 provided in the second embodiment of the present invention has a different circuit configuration from the bit line pull-up transistor drive circuit 16 constituting the write recovery circuit 15 provided in the first embodiment of the present invention. A bit line pull-up transistor drive circuit 32 is provided, and the other configuration is the same as that of the bit line pull-up transistor drive circuit 16.

In the bit line pull-up transistor drive circuit 32, 33 is a pMOS transistor provided corresponding to the pMOS transistor 7, and 34 is pM
NMOS provided corresponding to OS transistor 7
A transistor, 35 is a pMOS transistor provided corresponding to the pMOS transistor 8, and 36 is a pMO transistor.
This is an nMOS transistor provided corresponding to the S transistor 8.

The pMOS transistor 33 has a source connected to the VCC power supply line 4, a drain connected to the output node 37, and a gate connected to the write recovery signal WR.
And ON / OFF is controlled by the write recovery signal WR. The output node 37 is connected to the gate of the pMOS transistor 7.

The nMOS transistor 34 has a drain connected to the output node 37, a source connected to the write data line WD, and a gate connected to the write recovery signal W.
R is applied.

Therefore, this nMOS transistor 3
4 is the potential of the write data line WD = 0 [V],
ON when the recovery signal WR = VCC, or when the write recovery signal WR = 0 [V], or the potential of the write data line WD = VCC and the write recovery signal WR = V
In the case of CC, it is turned off.

The pMOS transistor 35 has a source connected to the VCC power supply line 4, a drain connected to the output node 38, a gate supplied with a write recovery signal WR, and turned on / off by the write recovery signal WR. It is configured to be controlled. The output node 38 is connected to the gate of the pMOS transistor 8.

The nMOS transistor 36 is configured such that the drain is connected to the output node 38, the source is connected to the write data line / WD, and the write recovery signal WR is applied to the gate.

Therefore, this nMOS transistor 3
6 is ON when the potential of the write data line / WD = 0 [V] and the write recovery signal WR = VCC,
When the recovery signal WR = 0 [V] or when the potential of the write data line / WD = VCC, the write recovery signal WR
In the case of = VCC, it is turned off.

In the second embodiment of the present invention configured as described above, the write recovery signal WR = 0 [V] in the write cycle.

As a result, during the write cycle, pMO
S transistor 33 = ON, nMOS transistor 34
= OFF, pMOS transistor 35 = ON, nMOS
Transistor 36 = OFF, potential of output node 37 = V
CC, the potential of the output node 38 = VCC, the pMOS transistor 7 = OFF, and the pMOS transistor 8 = OFF.

On the other hand, at the time of write recovery,
The write recovery signal WR is set to VCC, the pMOS transistor 33 is turned off, and the pMOS transistor 35 is turned off.
It turns off.

As a result, in the write cycle, the potential of the bit line BL = VCC and the potential of the bit line / BL = 0
[V], that is, when the potential of the write data line WD = VCC and the potential of the write data line / WD = 0 [V], at the time of write recovery, the nMOS transistor 34 =
OFF, nMOS transistor 36 = ON.

Therefore, the potential of output node 37 = VC
C and the potential of the output node 38 = 0
[V], the pMOS transistor 7 = OFF is maintained, and the pMOS transistor 8 = ON,
In the write cycle, the bit line / BL which was at 0 [V]
Is pulled up.

When the write recovery period ends, the write recovery signal WR is set to 0 [V], and pM
The OS transistor 33 = ON, the potential of the output node 37 = VCC, the pMOS transistor 7 = OFF is maintained, the pMOS transistor 35 = ON, the potential of the output node 38 = VCC, and the pMOS transistor 8 = OFF.

On the other hand, in the write cycle, the potential of bit line BL = 0 [V] and the potential of bit line / BL = V
CC, that is, when the potential of the write data line WD is set to 0 [V] and the potential of the write data line / WD is set to VCC,
At the time of write recovery, nMOS transistor 34 = O
N, nMOS transistor 36 = OFF.

Therefore, the potential of output node 38 = VC
C and the potential of the output node 37 = 0
[V], the pMOS transistor 8 = OFF is maintained, and the pMOS transistor 7 = ON,
At the time of the write cycle, the bit line BL at 0 [V] is pulled up.

Thereafter, when the write recovery period ends, the write recovery signal WR is set to 0 [V], and pM
OS transistor 33 = ON, potential of output node 37 = VCC, pMOS transistor 7 = OFF, pMOS transistor 35 = ON, potential of output node 38 = VCC, pMOS transistor 8 =
OFF is maintained.

As described above, in the second embodiment of the present invention, at the time of write recovery, the potential of the bit line BL = VC
C, when the potential of the bit line / BL is set to 0 [V], the gate voltage of the pMOS transistor 7 is maintained at VCC, and the gate voltage of the pMOS transistor 8 is changed from VCC → 0 [V] → VCC. In this case, of the pMOS transistors 7 and 8, only the gate capacitance of the pMOS transistor 8 is charged and discharged, and only the pMOS transistor 8 is driven to perform write recovery.

On the other hand, the potential of the bit line BL = 0
[V], when the potential of the bit line / BL is set to VCC, the gate voltage of the pMOS transistor 8 is set to VCC.
While changing the gate voltage of the pMOS transistor 7 from VCC → 0 [V] → VCC,
Of the transistors 7 and 8, only the gate capacitance of the pMOS transistor 7 is charged and discharged, and the pMOS transistor 7
Drive only to perform write recovery.

Here, at the time of write recovery, pMO
S transistors 33 and 35 and nMOS transistor 3
It is necessary to charge and discharge the gate capacitances of 4, 36,
The total gate width of the OS transistors 33 and 35 and the nMOS transistors 34 and 36 is pMOS transistor 7,
8 can be made smaller than each gate width.

For example, as described above, when the gate widths of the pMOS transistors 7 and 8 are set to, for example, 18 μm, the gate widths of the pMOS transistors 33 and 35 and the nMOS transistors 34 and 36 are set to, for example, 2 μm. be able to.

Therefore, according to the second embodiment of the present invention, the pMOS transistor 7 serving as the bit line pull-up transistor constituting the write recovery circuit 31,
The power consumption can be reduced by reducing the charge / discharge current for the gate capacitance of No. 8 and the configuration of the write recovery circuit can be simplified.

Third Embodiment FIG. 3 to FIG. 5 FIG. 3 is a circuit diagram showing a main part of a third embodiment of the present invention. In the third embodiment of the present invention, a maximum of 16-bit data is input. The configuration is such that output can be performed in parallel.

In FIG. 3, 40-1, 40-2, 40-16
Respectively correspond to write data DI via an external data line.
N1, DIN2, and DIN16 are external terminals to which write data DIN3, DIN4,.
4 to which the external terminals 5 are applied.
The illustration of 0-15 is omitted.

Further, 41-1, 41-2, 41-16
Are external terminals to which write control signals / WRC1, / WRC2, / WRC16 are applied via external write control signal lines, respectively, and write control signals / WRC3, / W
RC4,... / External terminal 41 to which WRC15 is applied
-3, 41-4,..., 41-15 are not shown.

Also, 42-1, 42-2, 42-16
Are write data DIN1, DIN2, DI
, DIN3, DIN4,..., DIN
Data input buffer 42 provided corresponding to 15
-3, 42-4,..., 42-15 are not shown.

Further, WD1 and / WD1 are write data line pairs driven by the data input buffer 42-1;
2, / WD2 is a write data line pair driven by the data input buffer 42-2, and WD16, / WD16 are write data line pairs driven by the data input buffer 42-16, and the data input buffers 42-3, 42 −
WD3, WD3, WD4, / WD4,... WD1
5, / WD15 is not shown.

FIG. 4 is a circuit diagram showing the structure of the data input buffer 42-1.
42-3,... 42-16 have the same configuration.

In FIG. 4, reference numeral 44 denotes a write control signal / WRC1.
An inverter 45 inverts the data transfer signal DLT and the output of the inverter 44.
An AND circuit 46 is a NAND circuit that performs NAND processing on the data line reset signal / DLR and the output of the inverter 44.

Reference numeral 47 denotes an inverter for inverting the write data DIN1, reference numeral 48 denotes an inverter for inverting the output of the inverter 47, and reference numeral 49 denotes on / off controlled by the output of the NAND circuit 45 to control the transfer of the output of the inverter 47. pMOS transistor, 50 is a NAND circuit 45
Is a pMOS transistor whose on and off are controlled by the output of the inverter 48, and controls the transfer of the output of the inverter 48.

Reference numeral 51 denotes a latch circuit for latching the output of the inverter 47 input via the pMOS transistor 49; 52, an inverter; and 53, a NOR for NOR processing the output of the inverter 52 and the output of the NAND circuit 46. A circuit 54 is an inverter for inverting the output of the latch circuit 51, and 55 is an inverter for inverting the output of the inverter 54 and driving the write data line WD1.

Reference numeral 56 denotes a latch circuit for latching the output of the inverter 48 input through the pMOS transistor 50, 57 denotes an inverter, and 58 denotes a NOR for NOR-processing the output of the inverter 57 and the output of the NAND circuit 46. A circuit 59 for inverting the output of the latch circuit 56; and 60 an inverter for inverting the output of the inverter 59 and driving the write data line / WD.

FIG. 5 is a waveform diagram for explaining the operation of data input buffer 42-1. Write control signal / W
RC1 = L level, ie, data input buffer 4
2-1 is activated and write data DIN1 is input.

In this case, the output of the inverter 44 = H
Level, and the NAND circuit 45 operates as an inverter for the data transfer signal DLT.
Circuit 46 is set to operate as an inverter in response to data line reset signal / DLR.

Here, in the write cycle, first, the data line reset signal / DLR = H level, the data transfer signal DLT = H level, the output of the NAND circuit 45 = L level, and the pMOS transistor 49 =
ON, pMOS transistor 50 = ON.

In this case, the output of NAND circuit 46 becomes L level, NOR circuit 53 operates as an inverter with respect to the output of inverter 52, and NOR circuit 58 operates as an inverter with respect to the output of inverter 57. It is set to operate as.

Here, for example, the write data DIN1 =
In the case of the H level, the output of the inverter 47 becomes L level, the output of the inverter 52 becomes H level, the output of the inverter 54 becomes L level, the output of the inverter 55 becomes H level, and the potential of the write data line WD1 becomes H level. Output of inverter 48 = H level, output of inverter 57 = L
Level, the output of the inverter 59 = H level, the output of the inverter 60 = L level, and the potential of the write data line / WD1 = L level.

Thereafter, the data transfer signal DLT =
L level, the output of the NAND circuit 45 = H level,
Since the pMOS transistor 49 is turned off and the pMOS transistor 50 is turned off, the latch circuits 51 and 56 perform a latch operation, and the output of the latch circuit 51 is maintained at the H level and the output of the latch circuit 56 is maintained at the L level.

Thereafter, the data line reset signal / D
LR = L level, output of NAND circuit 46 = H level, output of NOR circuit 58 = L level, inverter 5
7, the output of the inverter 59 is reset to the L level, the output of the inverter 60 is reset to the H level, and the potential of the write data line / WD1 is reset to the H level.

On the other hand, the write data DIN1 = L
Level, the output of the inverter 47 = H level,
The output of the inverter 52 = L level, the output of the inverter 54 = H level, the output of the inverter 55 = L level, the potential of the write data line WD1 = L level, the output of the inverter 48 = L level, and the output of the inverter 57 =
The H level, the output of the inverter 59 = L level, the output of the inverter 60 = H level, and the potential of the write data line / WD1 = H level.

Thereafter, the data transfer signal DLT =
L level, the output of the NAND circuit 45 = H level,
Since the pMOS transistor 49 is turned off and the pMOS transistor 50 is turned off, the latch circuits 51 and 56 perform a latch operation, and the output of the latch circuit 51 is kept at L level and the output of the latch circuit 56 is kept at H level.

Thereafter, the data line reset signal / D
LR = L level, output of NAND circuit 46 = H level, output of NOR circuit 53 = L level, inverter 5
2 is reset to the H level, the output of the inverter 54 is set to the L level, the output of the inverter 55 is set to the H level, and the potential of the write data line WD1 is reset to the H level.

On the other hand, in the write cycle, when the data input buffer 42-1 is inactivated and the write data DIN1 is not input, the write control signal / WRC1 = H level and the output of the inverter 44 = L level , The output of the NAND circuit 45 becomes H level, and pMO
S transistor 49 = OFF, pMOS transistor 5
0 = OFF.

In this case, the output of the NAND circuit 46 is H level, the output of the NOR circuit 53 is L level, the output of the inverter 52 is H level, the output of the inverter 54 is L level, and the output of the inverter 55 is H Level
When the potential of the write data line WD1 becomes H level,
The output of the NOR circuit 58 becomes L level, the output of the inverter 57 becomes H level, the output of the inverter 59 becomes L level, and the output of the inverter 60 becomes H level.
The potential of WD1 becomes H level.

As described above, in the third embodiment of the present invention, the data input buffers 42-1, 42-2,...
42-16 are write control signals / WRC1,
/ WRC2... / WRC16 can individually control activation and deactivation.
42-16, only an arbitrary data input buffer can be activated.

Therefore, even when it is necessary to rewrite any bit of the 16-bit data, the 16-bit data is read once, the ALU is rewritten with any bit, and then the 16-bit data is rewritten. A write operation for an arbitrary bit can be performed by driving a write data line pair corresponding to an arbitrary bit without requiring an operation of writing.

Therefore, according to the third embodiment of the present invention, write data line pairs WD1, / WD1, WD2, / W
D2... WD16 and / WD16 can reduce power consumption by reducing the charge / discharge current.

[0108]

According to the first aspect of the present invention, according to the semiconductor memory device of the first aspect, at the time of write recovery, of the first and second bit line pull-up transistors,
Since only the bit line pull-up transistor connected to the bit line whose potential is lowered is configured to be driven, the gate capacity of the bit line pull-up transistor constituting the write recovery circuit is charged and discharged. Power consumption can be reduced by reducing the current.

In the present invention, the second and third inventions (Claim 2,
According to the third aspect of the present invention, the same effect as that of the first aspect can be obtained, and the bit line pull-up transistor drive circuit directly uses the potentials of the first and second data transmission paths. Therefore, there is no need to provide a latch circuit for latching the potentials of the first and second data transmission paths reflecting the write data supplied from the outside, thereby simplifying the circuit configuration. can do.

According to the fourth aspect of the present invention, the transistor drive circuit for pulling up the bit line uses the potentials of the first and second data transmission paths as they are. It is not necessary to provide a latch circuit for latching the potentials of the first and second data transmission paths reflecting the write data supplied from the outside, and the circuit configuration is changed to the third invention. Therefore, the power consumption can be reduced and the circuit configuration can be simplified as compared with the third invention.

According to the fifth, sixth and seventh aspects of the present invention (semiconductor memory devices of claims 5, 6 and 7), only an arbitrary data input buffer is activated and an arbitrary write data line is activated. By driving only the pair, it is possible to rewrite any bit data of the n-bit data, read the n-bit data once, change the arbitrary bit data with the ALU, and then Since it is not necessary to perform the operation of writing bit data, power consumption can be reduced by reducing the charge / discharge current for the write data line pair.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a main part of a third embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating a configuration of a data input buffer included in a third embodiment of the present invention.

FIG. 5 is a waveform chart for explaining an operation of a data input buffer provided in a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of a conventional static RAM.

FIG. 7 is a waveform chart for explaining the operation of the write recovery circuit provided in the conventional static RAM shown in FIG.

[Explanation of symbols]

 2, 3 pMOS transistors forming bit line load elements 7, 8 pMOS transistors for pulling up bit line WR write recovery signal WD, / WD write data line BL, / BL bit line

Claims (7)

[Claims] A memory cell is connected to supply a positive power supply voltage and a bit line pair including first and second bit lines whose potential is lowered in accordance with write data during a write cycle. A semiconductor device comprising: a first load element connected between a power supply line to be connected and the first bit line; and a second load element connected between the power supply line and the second bit line. In the storage device, a first bit line pull-up transistor having a current input terminal connected to the power supply line, a current output terminal connected to the first bit line, and a current input terminal connected to the power supply line And a second bit line pull-up transistor having a current output terminal connected to the second bit line, and a potential of the first and second bit line pull-up transistors during write recovery. Has been lowered A semiconductor memory device comprising a write recovery circuit including a bit line pull-up transistor driving circuit that drives only a bit line pull-up transistor connected to a bit line. 2. The transistor drive circuit for pulling up a bit line, comprising: a potential of a first data transmission path including the first bit line; and a potential of a second data transmission path including the second bit line. And a write recovery signal for controlling a write recovery operation to drive the first and second bit line pull-up transistors. 13. The semiconductor memory device according to claim 1. 3. The bit line pull-up transistor drive circuit performs a NAND process on the potential of the second data transmission path and the write recovery signal to turn on the first bit line pull-up transistor. The first NA to drive
A second ND circuit that performs NAND processing on the ND circuit, the potential of the first data transmission path, and the write recovery signal to drive the second bit line pull-up transistor
3. The semiconductor memory device according to claim 2, further comprising an AND circuit. 4. The first bit line pull-up transistor drive circuit having a source connected to the power supply line, a drain connected to a first output node, and a gate to which the write recovery signal is applied. a p-channel insulated gate field effect transistor having a drain connected to the first output node, a source applied with the potential of the first data transmission path, and a gate applied with the write recovery signal; An n-channel insulated gate field effect transistor having a source connected to the power supply line, a drain connected to the second output node, and a gate to which the write recovery signal is applied; A field effect transistor and a drain are connected to the second output node, a source is applied with the potential of the second data transmission line, and a gate is connected to the gate of the second data transmission line. And a second n-channel insulated gate field-effect transistor to which a recovery signal is applied. The first and second bit line pull-up transistors are activated by the voltages of the first and second output nodes. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is configured to be driven. 5. First, second,..., N-th data input buffers provided corresponding to n-bit (here, an integer of 2 or more) write data, and first, second,. A first, second,..., N-th write data line pair driven by an n-th data input buffer, wherein the first, second,. A semiconductor memory device characterized in that activation and deactivation are controlled by first, second,..., N-th write control signals, respectively. 6. The i-th (where i = 1, 2,..., N)
When the data input buffer is activated in a write cycle, the data input buffer according to the given write data
One of the write data lines forming the i-th write data line pair is maintained at a high logic level, and the other write data line forming the i-th write data line pair is set to a low logic level, and the inactive state is set. In the case where
6. The semiconductor memory device according to claim 5, wherein one of said write data line pairs and said other write data line are maintained at a high logic level. 7. The i-th data input buffer includes: a first inverter for inverting the applied write data;
One end is connected to the first inverter, and is turned on when the i-th write control signal and the data transfer signal are at an active level, and turned off when the data transfer signal is at an inactive level. A switch element and an input terminal of a second inverter are connected to the other end of the first switch element, and a first input terminal of a first two-input NOR circuit is connected to an output terminal of the second inverter. , The first two
A first latch circuit that connects an output terminal of the input NOR circuit to an input terminal of the second inverter, and a data line reset signal is applied to a second input terminal of the first two-input NOR circuit; Is connected to the third inverter connected to the output terminal of the first inverter, and one end is connected to the third inverter, and is turned on when the i-th write control signal and the data transfer signal are at the active level. A second switch element that is turned off when the data transfer signal is at an inactive level, and an input terminal of a fourth inverter connected to the other end of the second switch element;
The first input terminal of the two-input NOR circuit is connected to the output terminal of the fourth inverter, the output terminal of the second two-input NOR circuit is connected to the input terminal of the fourth inverter, 7. The semiconductor memory device according to claim 6, further comprising a second latch circuit to which said data line reset signal is applied at a second input terminal of said two-input NOR circuit.