JPH1022206A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form the highest-density pattern without misalignment by forming a resist on a substructure having a light emitting layer, emitting an electromagnetic wave thereto, and sensitizing the resist through a luminescent light generating from the light emitting layer. SOLUTION: An insulation layer 12 and a wiring layer 13 are formed on a base substrate 11, and a light emitting layer 14 containing a phosphor is formed on the wiring layer 13 at the same pattern as the wiring layer 13. Then an interlayer insulation layer 15 is formed of a material having a high transmittance against an emitted light A and a luminescent light B, on the light emitting layer 14, and a positive resist 16 which is sensitized only by the light B is formed thereon. The light A is allowed to arrive at the layer 14 through the resist 16 and layer 15, and the light B whose wavelength is longer than that of the light A is excited and radiated from the layer 14, so that only the resist just beneath the layer 14 is sensitized selectively and it is developed so as to remove a resist in an area which is sensitized by the light B. Thus a resist pattern can be formed in a self-aligning manner against the layer 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device for forming a resist pattern and a method for manufacturing the same.

[0002]

2. Description of the Related Art In order to improve the degree of integration of large-scale integrated circuits, it goes without saying that it is important to reduce the minimum processing size in a lithography process, but it is also important to improve the alignment accuracy. This is because it is necessary to allow a margin for design in anticipation of misalignment. For example, when the upper and lower wiring layers are connected via a contact hole,
In order to prevent the contact hole from dropping from the underlying wiring, it is necessary to provide a margin according to the underlying wiring pattern. Since it is necessary to provide a margin for such alignment, it becomes difficult to arrange the patterns of the underlying wiring in the closest density.

On the other hand, as a method of forming an upper pattern in a self-aligned manner with respect to a base pattern, for example, Japanese Patent Laid-Open No.
There is a method described in JP-A-124722. In this method, a resist sensitive to secondary X-rays is applied to a metal wiring structure formed on a ceramics substrate, and the secondary X-rays emitted from the substrate when the resist is irradiated with X-rays from above the resist are applied to a metal wiring. In this case, the resist opening is formed in a self-aligned manner only on the metal wiring.

[0004]

The above-mentioned method has been devised for forming a wiring layer of a ceramic package, and this method is directly used for a semiconductor integrated circuit device having a contact pattern of an arbitrary shape. It is not possible. This is because in a semiconductor integrated circuit device, it is necessary to form a contact hole at an arbitrary position in an interlayer insulating layer covering a lower wiring pattern. An object of the present invention is to provide a semiconductor device and a method of manufacturing the same,
It is an object of the present invention to solve the problem of misalignment and to form a densest pattern.

[0005]

According to a method of manufacturing a semiconductor device of the present invention, a resist is formed on a lower structure having a light-emitting layer, and the resist is formed by luminescence light from the light-emitting layer generated by irradiation with an electromagnetic wave. Is exposed.

As the above-mentioned electromagnetic waves, light such as ultraviolet rays and far ultraviolet rays, electron beams, X-rays and the like can be used. Since the resist is sensitized by luminescence light from the light emitting layer generated by irradiating the electromagnetic wave, for example, if a wiring layer having the same line width as this light emitting layer is formed under the light emitting layer, the light emitting layer, that is, the wiring layer Thus, a resist pattern can be formed in a self-aligned manner. For example, the light emitting layer and the wiring layer are formed in the same pattern, and an electromagnetic wave such as light is irradiated through a mask having an opening pattern, and the width of the irradiation region of the electromagnetic wave is wider than the line width of the light emitting layer (wiring layer). By doing so, only the resist at the intersection of the irradiation area and the light emitting layer (wiring layer) can be selectively exposed. Therefore, a resist opening pattern can be formed in a self-aligned manner with respect to the light emitting layer (wiring layer). If, for example, the interlayer insulating layer is etched using the resist pattern thus obtained, a contact hole can be formed in a self-aligned manner with respect to the wiring layer.

A method for manufacturing a semiconductor device according to the present invention comprises:
A resist is formed on a conductive layer and a lower structure having a light emitting layer on the conductive layer, and the resist is exposed to luminescence light from the light emitting layer generated by applying an electric field to the conductive layer.

The resist is sensitized by luminescence light from the light emitting layer generated by applying an electric field to the conductive layer. For example, if the conductive layer is used as a wiring layer and is patterned to have the same line width as the light emitting layer, That is, a resist pattern can be formed in a self-aligned manner with respect to the pattern of the wiring layer. For example, if a light-emitting layer having a certain length is formed on a conductive layer and the conductive layer and the light-emitting layer are patterned to have a certain width, a light-emitting layer having the same width as the wiring layer and a certain length is formed. . If the resist is exposed to luminescence light from the light emitting layer formed in this way, an opening pattern of the resist can be formed in a self-aligned manner with respect to the light emitting layer. If, for example, the interlayer insulating layer is etched using the resist pattern thus obtained, a contact hole can be formed in a self-aligned manner with respect to the wiring layer.

A semiconductor device according to the present invention has a phosphor-containing light emitting layer formed on a main surface side of a semiconductor substrate. Since the light emitting layer is formed on the main surface side of the semiconductor substrate, the same operation and effect as described above can be obtained by applying the above manufacturing method.

The light emitting layer may be a thin film containing a phosphor, or a layer obtained by injecting a phosphor. As described above, according to the semiconductor device and the method for manufacturing the semiconductor device, it is possible to solve the problem of misalignment and to form the most dense pattern.

[0011]

FIG. 1 shows a first embodiment of the present invention. In FIG. 1A, reference numeral 11 denotes a base substrate made of a semiconductor substrate or the like, 12 denotes an insulating layer, and 13 denotes a wiring layer. 14 is a phosphor (ZnS, ZnO, C
use of the substance to produce a luminescent phenomenon of aWO ₄ or the like. ), And is formed on the wiring layer 13 in the same pattern as the wiring layer 13. Reference numeral 15 denotes an interlayer insulating layer, which is formed using a material having a high transmittance to the irradiation light A and the luminescence light B, such as CVD silicon oxide. Reference numeral 16 denotes a positive resist formed on the interlayer insulating layer 15.

Reference numeral 17 denotes a mask (17a is a light transmitting portion, 17b
Denotes a light shielding portion, and the light transmitting portion 17a has an opening pattern. As shown in the figure, the width of the opening pattern of the irradiation light A projected on the resist 17 is wider than the pattern width of the light emitting layer 14 and the wiring layer 13. Although the drawing is shown as the same-size exposure for convenience, it is actually a reduced exposure using a reduced projection exposure apparatus.

The irradiation light A passing through the photomask reaches the light emitting layer 14 through the resist 16 and the interlayer insulating layer 15,
Luminescent light B having a wavelength longer than the wavelength of the irradiation light excited by the irradiation light A is emitted from the light emitting layer 14. Here, by using a resist that is sensitive only to the luminescence light B, only the resist 16 immediately above the light emitting layer 14 is selectively exposed. That is, only the region where the irradiation region of the irradiation light A intersects with the region where the light emitting layer 14 is formed is selectively exposed.

When the resist 16 is developed after the step of FIG. 1A is completed, the resist is removed from the light emitting layer 14 only in the area exposed to the luminescent light B, and the resist 16 is removed.
As shown in (b), a resist pattern 16a is formed in a self-aligned manner with respect to the wiring layer 13 and the light emitting layer 14.
When the interlayer insulating layer 15 is anisotropically etched using the resist pattern 16a as a mask, a contact hole 15a is formed in a self-aligned manner with respect to the wiring layer 13 and the light emitting layer 14, as shown in FIG. You. At this time, the light emitting layer 14 may be removed at the same time.

In order to form the resist pattern 16a in a self-aligned manner with respect to the light emitting layer 14, only the resist directly above the light emitting layer 14 needs to be exposed, so that the upper surface of the light emitting layer 14 and the interlayer insulating layer 15 Is desirably flat.

The light-emitting layer may be formed as a phosphor-containing thin film, or may be formed by injecting a phosphor. FIG. 2 shows a forming method in this case. First, a conductive layer 22a made of polysilicon or the like is formed on an underlying substrate 21, and a phosphor is directly injected into the conductive layer 22a so that the upper part of the conductive layer 22a is
3a (a). Then, the conductive layer 22a and the light emitting layer 2
3a is selectively removed using the same mask to remove conductive layer 2a.
2 and the pattern of the light emitting layer 23 are formed, and the interlayer insulating layer 24 is formed.
And a resist 25 may be formed (b).

FIG. 3 shows a second embodiment of the present invention. Since the basic principle of this embodiment is the same as that of the first embodiment, items that can be easily analogized from the first embodiment will be referred to the first embodiment, and description thereof will be omitted.

In FIG. 3A, 31 is a base substrate made of a semiconductor substrate, 32 is an element isolation layer, 33 is a gate insulating layer, 34 is a gate electrode, 35 is an insulating layer covering the gate electrode, and 36 is a diffusion layer. , 37 are plug electrodes. Reference numeral 38 denotes a light emitting layer containing a phosphor, which is formed on the plug electrode 37 in the same pattern as the plug electrode 37.
Reference numeral 39 denotes an interlayer insulating layer, and reference numeral 40 denotes a positive resist formed on the interlayer insulating layer 39. 41 is a mask (41a
Denotes a light transmitting portion, 41b denotes a light shielding portion), and the light transmitting portion 41
a is an opening pattern. As shown in the figure, the width of the opening pattern of the irradiation light A projected on the resist 40 is wider than the pattern width of the light emitting layer 38 and the plug electrode 37.

The basic steps in FIGS. 3A to 3C are the same as those in the first embodiment shown in FIG. First, the irradiation light A
Is applied, only the area where the irradiation area intersects with the area where the light emitting layer 38 is formed is selectively exposed to light (a). When the resist 40 is developed, the resist is removed from the light emitting layer 38 only in a region exposed by the luminescence light B, and a resist pattern 40a is formed in a self-aligned manner with respect to the plug electrode 37 and the light emitting layer 38 (b).
When the interlayer insulating layer 39 and the light emitting layer 38 are anisotropically etched using the resist pattern 41a as a mask, contact holes are formed in a self-aligned manner with respect to the plug electrode 37 and the light emitting layer 38. Finally, a wiring layer 42 is formed and connected to the plug electrode 37 through the contact hole (c).

In the example shown in FIG. 3, the light emitting layer 38 is formed on the plug electrode 37, but the plug electrode 37 itself may contain a phosphor. In each of the above embodiments, the electromagnetic wave such as light applied to the light emitting layer includes K
In addition to the rF excimer laser, an i-ray, an ArF excimer laser, an X-ray, an electron beam, or the like can be used.

FIG. 4 shows a third embodiment of the present invention. In the first and second embodiments, the luminescence light is generated from the light emitting layer by an electromagnetic wave such as light. However, in the present embodiment, the luminescence light is generated from the light emitting layer by utilizing the electroluminescence phenomenon. Things. Since the configuration and the like are similar to those of the first embodiment, items that can be easily analogized from the first embodiment will be referred to the first embodiment, and description thereof will be omitted.

In FIG. 4A, reference numeral 51 denotes a base substrate formed of a semiconductor substrate or the like, 52 denotes a wiring layer, and 53 denotes a light emitting layer containing a phosphor. An interlayer insulating layer 54 is formed using a material having a high transmittance to the luminescence light C such as CVD silicon oxide. 55
Is a positive resist formed on the interlayer insulating layer 54.

When a pulsed AC electric field is applied to the wiring layer 52, a current flows in the wiring layer 52, and luminescence light C is emitted from the light emitting layer 53 by an electroluminescence phenomenon. The resist 55 immediately above the light emitting layer 53 is exposed to the light emitting layer 53 in a self-aligned manner by the luminescence light C.

When the resist 55 is developed after the step of FIG. 4A is completed, the resist is removed from the light emitting layer 53 only in a region exposed by the luminescence light C.
As shown in (b), a resist pattern 55a is formed in self-alignment with the light emitting layer 53. When the interlayer insulating layer 54 is anisotropically etched using the resist pattern 55a as a mask, a contact hole 54a is formed in a self-aligned manner with respect to the light emitting layer 53, as shown in FIG. At this time, the light emitting layer 53 may be removed at the same time.

If the light emitting layer 53 and the wiring layer 52 are patterned to have the same line width, a resist pattern 55a can be formed in a self-aligned manner with respect to the pattern of the light emitting layer 53, that is, the wiring layer 52. . FIG. 5 shows an example of this case.

First, as shown in FIG.
A light emitting layer 53a having a certain length is formed on 2a, and a resist pattern 56 having a certain line width is formed on the conductive layer 52a and the light emitting layer 53a. This resist pattern 5
When the conductive layer 52a and the light-emitting layer 53a are patterned using 6, the wiring layer 52 and the light-emitting layer 53 having the same line width as the wiring layer 52 are formed as shown in FIG. Thereafter, through the process shown in FIG. 4, the contact hole 54 is self-aligned with the light emitting layer 53, that is, the wiring layer 52.
a can be formed. In this manner, if the pattern of the light emitting layer 53 is patterned in advance so as to be the pattern of the contact hole 54a, a self-aligned pattern can be formed without using a mask as in the first and second embodiments. is there.

In the example shown in FIG. 4, a current flows between both ends of the wiring layer 52. However, the wiring layer 52 may be irradiated with microwaves. In each of the above embodiments, an example using a positive resist has been described. However, similar effects can be obtained by using a negative resist.

[0028]

According to the first aspect of the present invention, since the resist is exposed to luminescence light from the light emitting layer generated by irradiating an electromagnetic wave, for example, a wiring layer having the same line width as the light emitting layer is formed below the light emitting layer. By doing so, a resist pattern can be formed in a self-aligned manner with respect to the light emitting layer, that is, the wiring layer.

According to the second aspect of the present invention, the resist is exposed to light by the luminescence light from the light emitting layer generated by applying an electric field to the conductive layer. If the pattern is formed in advance, a resist pattern can be formed in a self-aligned manner with respect to the light emitting layer, that is, the wiring layer.

According to the third aspect of the present invention, since the light emitting layer is formed on the main surface side of the semiconductor substrate, if the resist is exposed to luminescence light from the light emitting layer, the resist is self-aligned with the light emitting layer. It is possible to form a resist pattern on the substrate.

As described above, according to the first to third aspects of the present invention, it is possible to solve the problem of misalignment and to form the most dense pattern. Therefore, when applied to a semiconductor integrated circuit, it is possible to greatly improve the degree of integration.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a first embodiment of the present invention.

FIG. 2 is a diagram showing another example of the first embodiment of the present invention.

FIG. 3 is a diagram showing an example of a second embodiment of the present invention.

FIG. 4 is a diagram showing an example of a third embodiment of the present invention.

FIG. 5 is a diagram showing an example of a third embodiment of the present invention.

[Explanation of symbols]

 14, 23, 38, 53 luminescent layer 52 conductive layer 16a, 40a, 55a resist pattern

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device, comprising forming a resist on a lower structure having a light emitting layer, and exposing the resist with luminescence light from the light emitting layer generated by irradiating an electromagnetic wave. 2. A resist is formed on a lower structure having a conductive layer and a light emitting layer on the conductive layer, and the resist is exposed to luminescence light from the light emitting layer generated by applying an electric field to the conductive layer. A method of manufacturing a semiconductor device. 3. A semiconductor device comprising a phosphor-containing light-emitting layer formed on a main surface side of a semiconductor substrate.