JPH10214803A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve stable cleaning with high cleanness without corroding the surface of an electrically conductive material film and further without generating any scratch by carrying out ultrasonic cleaning, using a cleaning liquid to which a ultrasonic wave is applied, prior to physical cleaning. SOLUTION: A film of a wiring material 12 is formed. Then, the wiring material 12 is polished and planarized by metal CMP and the wiring material is left only on a wiring pattern and in contact holes to form buried wiring. Then, before brush-scrub physical cleaning, foreign matters or grains causing scratches are washed away by a physically non-contact method. For the purpose, megasonic cleaning, for cleaning the wafer surface with a flow of pure water to which high frequency oscillation is applied, is used. Thus, cleaning of very high cleanness over the whole surface of the wafer is realized without generating any scratch in the surface of the wiring material 12, so that highly reliable semiconductor devices are produced with high yield.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device characterized by a cleaning step.

[0002]

2. Description of the Related Art The degree of integration of LSIs, including DRAMs and MPUs, is increasing year by year, and accordingly, design rules are shrinking, and wiring is becoming more multilayered. With the progress of multilayer wiring, a CMP (Chemical Mechanical Polishing) technique for flattening an interlayer insulating film has been introduced in a 0.35 μm logic LSI in order to secure a focus margin of an exposure machine. Chemical mechanical polishing (CM
P) is a chemical etching action by a chemical component contained in the abrasive, a mechanical polishing action inherent to the abrasive,
This is a polishing method in which polishing is performed by utilizing the above. CMP techniques used in LSI manufacturing processes include BPSG and SiO ₂ deposited on device steps such as transistors and wiring.
Planarization CMP to flatten the device steps by polishing the insulating film such as SiO2, and insulating film such as SiO ₂ or poly in the hole or trench formed on the device.
A recess CM for forming a buried element isolation, trench capacitor, contact plug or damascene wiring by burying a metal film such as Si, Al, Cu, W or the like and polishing a deposited film deposited in a portion other than a hole or a trench portion;
There is P. Either technique has a feature that can realize global flatness as compared with the conventionally used SOG flattening technique or etch-back flattening technique.

Under these circumstances, the production of LSIs up to the 0.25 μm rule can be handled by the CMP technique for flattening the interlayer insulating film and the conventional wiring forming technique,
After the μm rule, it is considered that burying wiring by dual damascene using metal CMP technology is indispensable for the formation of multi-layer wiring due to factors such as the limitation of the wiring material etching technology and the securing of electromigration resistance.

A method of forming a buried wiring by dual damascene using metal CMP will be described below with reference to FIGS.

In FIG. 26, reference numeral 1 denotes a p-type semiconductor substrate;
Is an n-type well, 3 is a high-concentration p ⁺ -type source electrode, 4 is a high-concentration p ⁺ -type drain electrode, and 5 is a gate electrode. Around the source electrode 3 and the drain electrode 4 to improve the breakdown voltage of the transistor Low-concentration p ^- type electric field relaxation regions 3 ', 4'
Is provided. Reference numeral 6 denotes a selective oxidation region for element isolation.

Next, as shown in FIG. 27, after NSG (non-doped glass) 7 is formed by CVD or TEOS, the NSG 7 is polished and flattened by CMP. C here
MP is a polishing cloth obtained by laminating a foam cloth such as IC-1000 generally used when polishing an interlayer insulating film by CMP, a nonwoven cloth cloth, and SC-1 using fumed silica. Is performed using the silica-based slurry. Next, a p-SiN (silicon nitride film formed by a plasma CVD method) 8 is formed, followed by p-SN.
An iO (silicon oxide film formed by a plasma CVD method) 9 is formed.

Next, as shown in FIG. 28, a wiring pattern 10 is formed on the p-SiO 9 by resist patterning and dry etching. During dry etching, p-SiN
By using 8 as an etching stopper, the wiring pattern 10 can be formed stably. Next, a contact pattern 11 is formed by resist patterning and dry etching.

[0008] Next, as shown in FIG.
Is formed. Various methods are conceivable as a method for forming the wiring material 12 here, but from the viewpoint of improving manufacturing cost, reliability, and element characteristics, a sputter reflow method of a metal material based on Al or Cu is effective. It is. Before performing film formation by the above-mentioned sputter reflow, Ti
By forming a barrier metal such as / TiN, reliability is improved and reflow characteristics are improved, which is effective.

[0009] Next, as shown in FIG.
The P material is polished and the wiring material 12 is polished and flattened to form a buried wiring 13. The above is the method of forming the embedded wiring by dual damascene. In a similar manner, FIG.
As shown in FIG. 32, a second-layer wiring 13 'and a third-layer wiring 13 "can be formed, and the wiring can be further multilayered.

[0010]

As described above, although polishing by CMP is useful as a means for flattening, there are also points to be improved. One of them is the problem of post-CMP cleaning. Since the CMP process itself is a polishing process for processing the wafer surface with an abrasive material called slurry,
Abrasive grains of the slurry, chips generated in the polishing process, and products adhere to the surface of the wafer after the MP, and these must be washed and removed. Wiring material is Al or Cu
Since a metal material based on chromium is used, chemical cleaning using an acid or alkali has a problem of corrosion and is difficult to employ. Sufficient cleanliness cannot be obtained only by washing with pure water. In scrub cleaning, which is a physical cleaning using pure water and PVA sponge or mohair brush, since the wiring material is a soft metal material, foreign matter adhering to the wafer surface triggers the reliability such as electromigration on the wiring material surface. Fine scratches called scratches, which are problematic, occur.

Apart from this, a cleaning method using, for example, field ion water having low metal etching property has also been proposed (H. Aoki, et. Al., 1994 VLSI Technical Dig., P. 79 (19)
94)), the fact is that this method cannot sufficiently remove the abrasive grains attached to the wafer surface.

It is an object of the present invention to provide a process which can stably clean the surface of a conductive material film with high cleanliness without corrosion and without scratching after forming the conductive material film. An object of the present invention is to provide a method for manufacturing a semiconductor device.

[0013]

A method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a conductive material on a substrate, polishing the conductive material film, and polishing the conductive material film. Cleaning the cleaned surface, wherein, as the cleaning step, ultrasonic cleaning with a cleaning liquid to which ultrasonic waves have been applied is performed prior to the physical cleaning.

According to the present invention, prior to physical cleaning,
By cleaning the polished surface of the conductive material film using a cleaning liquid to which ultrasonic waves have been applied, chips generated by polishing and abrasive grains of slurry can be effectively removed. This makes it possible to clean the conductive material film forming the wirings, electrodes, and the like in a state where scratches are not generated or in an extremely small state, and with high cleanliness. According to the method for manufacturing a semiconductor device of the present invention, it is possible to provide a semiconductor device having a conductive material member which is extremely flat, has no scratch, and is excellent in reliability.

In the present invention, the conductive material is generally used in the semiconductor industry as a wiring material or an electrode material.

Specific examples include Al, Au, Cr, and the like used as wiring metal, barrier metal, adhesion metal, contact metal, buffer metal, and the like.
Mo, Pt, Ti, poly-Silicon, or alloys thereof, or ITO (Indi) used as a transparent electrode
um Tin Oxide).

These conductive materials can be formed by sputtering, vacuum deposition, CVD (Chemical Vapor Dep.
osition), but is not limited thereto. The method of polishing the conductive material film can be appropriately selected according to the characteristics and application of the film, but a chemical mechanical polishing (CMP) is preferably used. As an example of chemical mechanical polishing (CMP),
It is conceivable that a reaction product generated by a chemical reaction between the chemical component contained in the polishing material and the surface of the sample to be polished is mechanically polished and removed using the polishing material and a polishing cloth. C
In the MP process, a sample to be polished is mounted on a rotatable polishing head, and then the surface of the sample to be polished is pressed against a rotating platen (polishing platen) to perform polishing. A pad (polishing cloth) is attached to the surface of the platen, and the polishing proceeds by the slurry (abrasive) attached to the pad.

As a polishing cloth, a Rodale Supreme
As a continuous foam suede type cloth such as RN or Fujimi Corporation's SurfinIV-1 and slurry, colloidal silica with good primary and secondary particle diameter of 100 nm or less of abrasive grains such as Fujimi Corporation's PLANERLITE-5102 etc. XJFW-809 or Rodale XJFW-809
Alumina slurry such as 9 can be suitably used.

In the present invention, the ultrasonic cleaning is preferably performed by rotating an object to be cleaned at 1000 to 2500 rpm and spraying pure water to which ultrasonic waves have been applied from a oscillating nozzle. The frequency of the applied ultrasonic wave is
Considering the damage to the object to be cleaned, the frequency is preferably 800 kHz or more, and optimally, a frequency of 1 MHz to 3 MHz can be adopted.

In the present invention, physical cleaning refers to general physical cleaning used in comparison with chemical cleaning. Specific examples include brush scrub, high pressure jet (Jet) cleaning, and the like. The brush scrub usually rotates an object to be cleaned, and supplies a cleaning liquid (pure water, a surfactant, or the like) thereto. At the same time, by moving the brush on the object to be cleaned while rotating, the adhered particles on the object to be cleaned are physically removed. Typical brush materials include mohair, sponge, nylon, and goat hair. Mohair brush and sponge brush (for example, PVA (polyvinyl alcohol))
A sponge brush) is suitable. The high-pressure Jet cleaning method is a cleaning method in which pure water pressurized to about 50 to 100 kgf / cm ² by a pump is sprayed onto the surface of the object to be cleaned through a nozzle tip. In this cleaning method, the object to be cleaned is rotated, and the jet nozzle is swung to perform the cleaning.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multi-layer wiring process for a semiconductor device and a manufacturing process for a reflection type liquid crystal display device will be described as typical embodiments of the present invention. In the following description of the process, a semiconductor substrate is used, but the substrate is not necessarily limited to the semiconductor substrate, and the SOI (Si
(Licon On Insulator) Substrates and transparent substrates can also be used. The multilayer wiring process can be applied to a manufacturing process of a memory element such as a DRAM and a logic element such as an MPU and an ASIC. In the following description, the switching elements of the active matrix substrate constituting the liquid crystal display device are all of the MOSFET type, but may be of the diode type, bipolar transistor type or TFT type.
The reflective liquid crystal display device is effective as a display device for a home television, a projector, a head mounted display, a video conference system, an airplane panel, and the like. [First Embodiment] FIGS. 1 to 7 are explanatory views of a multi-layer wiring manufacturing process of a semiconductor device according to the present invention. In FIG. 1, 1 is a p-type semiconductor substrate, 2 is an n-type well, 3 is a high-concentration p ⁺ -type source electrode, 4 is a high-concentration p ⁺ -type drain electrode,
Is a gate electrode. Around the source electrode 3 and the drain electrode 4, low-concentration p ⁻ -type electric field relaxation regions 3 ′ and 4 ′ for improving the withstand voltage of the transistor are provided. By the way, the offset amount of the electric field relaxation regions 3 'and 4' is set to 0.
5-2.0 μm is preferred. Reference numeral 6 denotes a selective oxidation region for element isolation.

Next, as shown in FIG. 2, after NSG (non-doped glass) 7 is formed by CVD or TEOS, this NSG 7 is polished and flattened by CMP. Here, the NSG7 CMP includes a foam cloth such as IC-1000 (manufactured by Rodale) commonly used for CMP of the interlayer insulating film,
Polishing cloth laminated with non-woven cloth, and SC-1 (Ca) using fumed silica or colloidal silica
It is preferable to use a silica-based slurry such as bot Corporation.
Next, a p-SiN (plasma silicon nitride film) 8 is formed, followed by a p-SiO (plasma silicon oxide film) 9.
Is formed. Since p-SiN8 is used as an etching stopper when patterning p-SiO9,
The thickness of p-SiO9 is 500 mm or more, and the thickness of p-SiO9 is Al
Since the thickness of the wiring is determined, a film thickness that is equal to or greater than the thickness of the Al wiring required as a device is required.

Next, as shown in FIG. 3, an Al wiring pattern 10 is patterned by resist patterning and dry etching of p-SiO9. The dry etching conditions used here are such that the etching gas is CF ₄ / CHF.
₃ = 50 ccm / 10 ccm, total pressure 1000 m
Torr and power were set to 750W. P-Si at this time
The selectivity with N8 is p-SiO etch rate / p-SiN
The etch rate was 2.2. Subsequently, a contact pattern 11 is formed by resist patterning and dry etching. Here, since the interlayer film to be subjected to the contact etching is a laminate of different films of p-SiN8 and NSG7, dry etching is performed in two stages, and etching in the first stage for etching p-SiN8 is performed. The condition is CF ₄ / CHF ₃ = 100 ccm / 20 c
cm, a total pressure of 1700 mtorr, and a power of 750 W. The second stage etching conditions for etching the NSG 7 and the gate oxide film are as follows: CF ₄ / CHF ₃ = 50 ccm /
10 ccm, total pressure 1000 mtorr, power 750
Etching was performed with W.

Next, as shown in FIG. 4, a wiring material 12 is formed. Generally, the wiring material 12 is AlSi, AlC
Metal materials such as u and AlSiCu are used, and as a film forming method thereof, a sputter reflow technique is used.
The embedding of the contact hole 11 is effective for improving the reliability of the device. When performing this sputter reflow, by providing a Ti / TiN barrier metal as a base, the contact resistance is reduced, and the reflow characteristics of the wiring material such as AlSi are improved.
1 can be easily embedded. Contact hole 1
As an embedding method, it is also effective to use selective CVD of tungsten. Next, the wiring material 12 is polished and flattened by metal CMP, and the buried wiring 13 is formed while leaving the wiring material only in the wiring pattern 10 and the contact hole 11 (FIG. 5).

In this case, the polishing cloth used was SurfinIV-1 manufactured by Fujimi Corporation, the slurry used was PLANERLITE-5102 manufactured by Fujimi Corporation, and the CMP apparatus was EPO-1 manufactured by Ebara Corporation.
Polishing was performed using No. 14. Specifically, the polishing conditions were as follows: the load of the top ring was 300 gf (weight gram) / cm ² , the rotation speed of the top ring was 49 rpm, the rotation speed of the turntable was 50 rpm, and the backside pressure was 100 gf / cm.
cm ² , dressing, nylon brush rotation speed 51
In-situ dressing (dressing for simultaneous polishing and dressing) with a rpm of 42 gf / cm ² and a slurry flow rate of 100 ml / min. Under the above conditions, S
As a result of polishing AlSi having an i content of 1 wt%, a polishing rate of 3000 was obtained without generating scratches in the polishing process.
Å / min and in-plane uniformity σ / polishing rate ≦ 5% were obtained.

FIG. 8 shows SE on the Al surface immediately after metal CMP.
An M photograph is shown. FIG. 9 is an enlarged SEM photograph of FIG. A
It can be seen that many abrasive grains 21 remain on the surface 20.
The average density of the residual abrasive grains 21 on the Al surface 20 was about 200 / μm ² . In addition to the residual abrasive grains 21, 0.3 μm
Thousands of foreign substances over m are left on a 6-inch wafer.
In the cleaning process after metal CMP, the above-mentioned abrasive grains and foreign substances must be removed without generating scratches.

When scrub cleaning with a PVA brush, which is generally used, is applied to cleaning of the Al surface after metal CMP, a large number of scratches 22 shown in the optical micrograph of FIG. 10 were generated. This is considered to be a scratch generated by a relatively large foreign substance or agglomerated abrasive grains on the Al surface before cleaning, which was triggered. Therefore, it is necessary to remove foreign substances or abrasive grains that cause scratches by a physically non-contact method before performing brush scrub cleaning for physically rubbing off.

The present inventor used megasonic cleaning in which the wafer surface was cleaned with running pure water with high-frequency vibration. Megasonic pure water condition is 6m in diameter
The pure water with a flow rate of 1 liter / min from the tip of the nozzle of mφ is supplied with a vibrator provided in the nozzle at a frequency of 1.5M.
Hz vibration was applied at a power of 48 W. It was found that the cleaning effect of the abrasive grains on the Al surface by the megasonic cleaning depends on the number of rotations of the wafer during cleaning as shown in FIG. Note that 0 mm, 30 mm, and 60 mm shown in FIG. 11 indicate the distances of the measurement points from the center of the wafer.
As is clear from FIG. 11, the rotation speed of the wafer during megasonic cleaning is 1500 rpm or more, more preferably 200 rpm.
It is desirable to set it to 0 rpm or more. FIG. 33 is an explanatory diagram showing the configuration of the cleaning device. As shown in FIG. 33, the nozzle for discharging the cleaning liquid is movable on the wafer.

Next, the dependence of the cleaning effect of the abrasive grains on the Al surface on the vibration frequency of the cleaning water was examined. FIG. 15 shows the results.
Here, the measurement was performed while the frequency of the wafer was changed while the rotation speed of the wafer at the time of cleaning was 2000 rpm, the scan speed of the cleaning water nozzle was 10 mm / sec, and the number of scans of the nozzle was 20 times. From the figure, the frequency put on the washing water is 800 kHz.
From the point of z, it is understood that the effect of removing abrasive grains attached to the Al surface appears, and that there is a very large cleaning effect in a region where the frequency is on the order of MHz.

Generally, cleaning using a low frequency of about several tens of kHz to about 400 kHz removes foreign matter having a size of several μm to several tens μm by applying a strong shock wave to the substrate surface by liquid cavitation due to liquid resonance. However, there is a problem that the impact due to the liquid cavitation damages the fine pattern, and the cleaning is not used in semiconductor processes of 4 mega DRAM or later. Also in the study of the present inventors, there was a problem that the patterned Al was peeled off at 80 kHz and 400 kHz cleaning. On the other hand, at a high frequency of 800 kHz or more, no damage to the pattern was observed.

Considering the above cleaning effect and pattern damage, 800 kHz is used for cleaning the abrasive grains adhered to the Al surface.
It is effective to use the above high frequency. And it is understood that it is more preferable to set the frequency in the range of 1 MHz to 3 MHz.

Next, the Al surface was cleaned at a frequency of 1.5 MHz, a wafer rotation speed of 2000 rpm, a nozzle scan speed of 10 mm / sec, and a nozzle scan frequency of 20 times. As a result, the abrasive grains on the Al surface could be removed to 30 grains / μm ² or less. FIG.
2 shows an SEM photograph of the Al surface washed under the above conditions.
20 'is an Al surface and 21' is an abrasive grain. 0.3μ
Foreign matters of m or more could be removed to about several tens on a 6-inch wafer. Fig. 13 shows a foreign substance inspection system IS-327 manufactured by Hitachi.
0 shows the results of measuring foreign substances of 0.3 μm or more according to 0. In addition,
During the megasonic cleaning, the back surface of the wafer is always kept in a wet state by a pure water shower.

Next, brush scrub cleaning was performed simultaneously on the Al surface subjected to megasonic cleaning with a pencil-type PVA sponge and on the back surface of the wafer with a roll-type PVA sponge.
The cleaning conditions were as follows: the Al surface had a pressing force of a pencil-type PVA sponge of 1 mm, a sponge rotation speed of 60 rpm, a wafer rotation speed of 100 rpm, a pencil-type PVA sponge scan speed of 10 mm / sec, and a scan frequency of three times. The PVA sponge pressing amount was 1 mm, the rotation number of the roll sponge was 100 rpm, and the cleaning time was 60 seconds. Further, after scrub cleaning, megasonic cleaning was performed again. The cleaning conditions are all the same as the above-mentioned megasonic cleaning conditions, except that the number of nozzle scans is three. Then, the wafer rotation speed is set to 30
Spin drying was performed for seconds. A of the result of the above cleaning
FIG. 14 shows an SEM photograph of the l surface. Reference numeral 20 "denotes an Al surface. It can be seen that abrasive grains and foreign matters have been removed cleanly.

Next, as shown in FIG. 6, the second layer p-
After laminating SiN 8 'and the second layer p-SiO 9', FIG.
The second layer embedded wiring 13 'was formed in the same manner as in the dual damascene described with reference to FIGS. Figure 7 with the same technique
As shown in FIG. 7, a third-layer buried wiring 13 ″ was formed.
It is needless to say that the same dual damascene can further form the embedded wiring of the fourth and subsequent layers. Further, as a material of the embedded wiring of each layer, a highly conductive material such as Ag, Au, Pt, Cr, Cu, etc. can be used.

In this embodiment, in the cleaning after metal CMP in the dual damascene process, the surface of the wafer on which the buried wiring is formed and the metal is exposed is first subjected to ultrasonic cleaning after polishing is completed, and then the PVA sponge or mohair brush is used. And then spin drying was performed after megasonic (ultrasonic) cleaning. But,
The point of the present invention is to perform ultrasonic cleaning prior to physical cleaning, and the present invention is not limited to the embodiment shown here.

When the scrub cleaning is performed a plurality of times with a plurality of different cleaning units, the cleaning effect is further improved.
By employing the above cleaning sequence, cleaning with extremely high cleanliness is realized over the entire surface of the wafer without generating scratches on the surface of the wiring material, and a highly reliable semiconductor device can be provided with high yield.

[Second Embodiment] An example in which the present invention is applied to a manufacturing process of an active matrix substrate of a reflection type liquid crystal display device will be described with reference to FIGS.

In FIG. 16, reference numeral 1 denotes a p-type semiconductor substrate;
Is n-type well, 3 is high concentration p⁺Type source electrode, 4 is highly concentrated
Degree p⁺The drain electrode 5 and the gate electrode 5 are gate electrodes. Source
Around the electrode 3 and the drain electrode 4, the resistance of the transistor
Low concentration p to increase pressure ^-Type electric field relaxation region 3 ',
4 'is provided. By the way, this electric field relaxation region
The offset amount of 3 ', 4' is preferably 0.5 to 2.0 μm.
It is. Reference numeral 6 denotes a selective oxidation region for element isolation.

Next, as shown in FIG. 17, after NSG (non-doped glass) 7 is formed by CVD or TEOS, the NSG 7 is polished and flattened by CMP. Here, the NSG7 CMP is performed by using a polishing cloth obtained by laminating a foam cloth such as an IC-1000 generally used for the CMP of an interlayer insulating film, a nonwoven cloth cloth, and a SC cloth using fumed silica or colloidal silica. It is preferable to use a silica-based slurry such as 1. Next, a p-SiN (plasma silicon nitride film) 8 is formed, and subsequently, a p-SiO (plasma silicon oxide film) 9 is formed. p-SiN8 is pS
Since iO9 is used as an etching stopper when patterning, the thickness should be 500 mm or more, and p-Si
Since the thickness of O9 determines the thickness of the Al wiring, the thickness of the O9 needs to be greater than the thickness of the Al wiring required as a device.

Next, as shown in FIG.
The Al wiring pattern 10 is patterned by resist patterning and dry etching. The dry etching conditions used here are such that the etching gas is CF ₄ / CH
F ₃ = 50 ccm / 10 ccm and the total pressure is 1000
mtorr and power were set to 750W. PS at this time
The selectivity with iN8 is p-SiO etch rate / p-Si
The N etch rate was 2.2. Subsequently, a contact pattern 11 is formed by resist patterning and dry etching. Here, since the interlayer film to be subjected to the contact etching is a laminate of different films of p-SiN8 and NSG7, dry etching is performed in two stages, and etching in the first stage for etching p-SiN8 is performed. The condition is CF ₄ / CHF ₃ = 100 ccm / 20
ccm, total pressure 1700 mtorr, power 750 W, and the etching condition of the second stage for etching the NSG 7 and the gate oxide film is CF ₄ / CHF ₃ = 50 ccm.
/ 10 ccm, total pressure 1000 mtorr, power 75
Etching was performed at 0 W.

Next, as shown in FIG. 19, a wiring material 12 is formed.

Next, the wiring material 12 is polished and flattened by metal CMP, and the wiring pattern 10 and the contact hole 11 are polished.
The buried wiring 13 is formed by leaving the wiring material only in the substrate (FIG. 20). The method of forming the embedded wiring 13 described above is the same as in the first embodiment.

After polishing by CMP, as shown in FIG. 21, a p-SiO30 film is formed, and then a light shielding layer 31 is formed.
Is formed. As a material of the light shielding layer 31, Ti, Mo, A
It is effective to use metal materials such as 1, W, Ag, Pt, and Cr. The light shielding layer 31 is patterned.

Next, as shown in FIG.
3 is formed to a thickness of 1000 ° or more, p-SiO 33 is patterned using the light-shielding layer 31 as an etching stopper, and then a capacitance film 34 is formed. A high dielectric material such as p-SiN or Ta ₂ O ₅ is effective as a material for the capacitance film 34.

Next, as shown in FIG.
-Pattern SiO30, and set reflective electrode material 35 to p
-Deposit a film thicker than the thickness of SiO33. As a material for the reflective electrode, a conductive material having high reflectivity in the visible light region, such as Al, Ag, Pt, and Cr, is suitable. Here A
1 was used.

Next, as shown in FIG.
5 is polished and flattened by CMP. The polishing amount is p-
Polishing is performed until SiO33 is exposed on the wafer surface. Here, the reflective electrode 36 was formed by Al metal CMP. The conditions of Al metal CMP and post-polishing cleaning are:
The conditions at the time of forming the buried wiring 13 are conformed.

Next, as shown in FIG.
Is formed. As a material, a dielectric material having a high refractive index such as ZnS or TiO ₂ is used.
4 is formed. Also, p-SiO / p-SiN /
As in the case of TiO ₂ , it is more effective to stack layers each having a thickness of １ ／ of the wavelength of the light in ascending order of the refractive index.

The feature of this embodiment is that when the reflective electrode 36 is formed by dual damascene, in cleaning after metal CMP, the wafer surface is first subjected to megasonic cleaning after polishing is completed, and then physical cleaning is performed. . By adopting such a cleaning sequence, a reflective electrode 36 having a clean surface without scratches is realized, and high brightness,
A high definition reflective liquid crystal display device can be provided.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is an explanatory diagram of a first embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 3 is an explanatory view of a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is an explanatory diagram of the first embodiment of the method for manufacturing a semiconductor device according to the present invention;

FIG. 5 is an explanatory diagram of the first embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is an explanatory diagram of the first embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is an explanatory diagram of the first embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is an SEM photograph of an Al surface after metal CMP.

FIG. 9 is an enlarged photograph of FIG. 8;

FIG. 10 is an optical micrograph of a scratch on an Al surface.

FIG. 11 is a diagram showing the results of an experiment on the effect of megasonic cleaning on the wafer rotation speed.

FIG. 12 is a SEM photograph of an Al surface after megasonic cleaning.

FIG. 13 shows a measurement result of a foreign substance having a size of 0.3 μm or more after megasonic cleaning.

FIG. 14 shows SE on the Al surface after cleaning according to the first embodiment.
It is an M photograph.

FIG. 15 is a graph showing the frequency dependence of the cleaning power of a cleaning liquid to which ultrasonic waves have been applied.

FIG. 16 is an explanatory diagram of a method of manufacturing a reflection type liquid crystal display device according to the present invention.

FIG. 17 is an explanatory diagram of a method for manufacturing a reflective liquid crystal display device according to the present invention.

FIG. 18 is an explanatory diagram of the method for manufacturing the reflective liquid crystal display device according to the present invention.

FIG. 19 is an explanatory diagram of a method for manufacturing a reflective liquid crystal display device according to the present invention.

FIG. 20 is an explanatory diagram of a method for manufacturing a reflective liquid crystal display device according to the present invention.

FIG. 21 is an explanatory diagram of a method for manufacturing a reflective liquid crystal display device according to the present invention.

FIG. 22 is an explanatory diagram of the method for manufacturing the reflective liquid crystal display device according to the present invention.

FIG. 23 is an explanatory diagram of the method for manufacturing the reflective liquid crystal display device according to the present invention.

FIG. 24 is an explanatory diagram of a method for manufacturing a reflective liquid crystal display device according to the present invention.

FIG. 25 is an explanatory diagram of the method for manufacturing the reflective liquid crystal display device according to the present invention.

FIG. 26 is an explanatory diagram of a method for manufacturing a semiconductor device according to a conventional example.

FIG. 27 is an explanatory diagram of a method of manufacturing a semiconductor device according to a conventional example.

FIG. 28 is an explanatory diagram of a method for manufacturing a semiconductor device according to a conventional example.

FIG. 29 is an explanatory diagram of a method of manufacturing a semiconductor device according to a conventional example.

FIG. 30 is an explanatory diagram of a method for manufacturing a semiconductor device according to a conventional example.

FIG. 31 is an explanatory diagram of a method for manufacturing a semiconductor device according to a conventional example.

FIG. 32 is an explanatory diagram of a method for manufacturing a semiconductor device according to a conventional example.

FIG. 33 is an explanatory diagram showing a configuration of a cleaning device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 p-type semiconductor substrate 2 n-type well 3 source electrode 4 drain electrode 5 gate electrode 6 selective oxidation region 7 NSG 8 p-SiN 9 p-SiO 10 wiring pattern 11 contact pattern 12 wiring material 13 buried wiring 8 ′, 8 ″ p -SiN 9 ', 9 "p-SiO 13', 13" buried wiring 3 ', 4' electric field relaxation region 20 Al surface 21 abrasive grains 22 scratch 20 ', 20 "Al surface 21' abrasive grains 30 p-SiO 31 light shielding Film 33 p-SiO 34 capacitance film 35 reflective electrode material 36 reflective electrode 37 reflection increasing film

Claims (10)

[Claims] A step of forming a conductive material on a substrate;
A method of manufacturing a semiconductor device, comprising: a step of polishing the conductive material film; and a step of cleaning the polished surface of the conductive material film. A method for manufacturing a semiconductor device, comprising: performing ultrasonic cleaning with a cleaning solution to which a pressure is applied. 2. The polishing step is a CMP (Chemical Mec.) Process.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the method is performed using hanical polishing. 3. The method according to claim 1, wherein the ultrasonic cleaning is performed in a frequency range of 800 kHz or more. 4. The method according to claim 3, wherein the frequency range is 1 MHz to 3 MHz. 5. The method according to claim 1, wherein the ultrasonic cleaning is performed by ejecting the cleaning liquid from a nozzle. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the ultrasonic cleaning is performed by rotating the substrate on which the polished surface is disposed at 1000 to 2500 rpm. 7. The method according to claim 1, wherein the physical cleaning is selected from brush scrubbing and high-pressure jet cleaning. 8. The method according to claim 7, wherein the brush scrub is performed using a mohair brush or a sponge brush. 9. The method according to claim 8, wherein the sponge is made of PVA (polyvinyl alcohol). 10. The method according to claim 1, wherein ultrasonic cleaning is performed again after the physical cleaning.