JPH1021218A - Product sum arithmetic method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make configuration simple, compact and economically advantageous by providing two kinds of storing means and plural selecting means for guiding to the storing means. SOLUTION: A multiplier Q(x) is inputted from a high-order device through a gate circuit 27. When the term of the highest degree of Q(x) is inputted, the term is multiplied by the respective terms of multipliers held is FF circuits 251, 252,... by multiplier circuits 281, 282,.... Then the multiplying results of the multiplier circuits 281, 282,... are stored in FF circuits 261, 262,... respectively through adder circuits 291, 292,... (which become through because a value to add is 0 at first) and selectors 301, 302,.... Next the term of the next degree of Q(x) is inputted. By repeating operation like this, the multiplied results are successively shifter. This operation is repeated until it reaches the constant term of Q(x). Then the multiplier becomes the term of sum in the next recurrence formula calculation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an RS (Re
The present invention relates to a product-sum operation method suitable for use in a decoding system for ed-Solomon) codes and the like.

[0002]

2. Description of the Related Art As is well known, BCH (Bose-Chaudhuri)
RS code, which is a type of Hocquenghem code, is often generated from a binary (implemented by an exclusive-OR circuit) expanded field that matches the hardware, and is widely used as an error correction method that is resistant to burst errors and the like. Are known. FIG. 5 shows the overall configuration of a decoding system that decodes such an RS code using the Euclidean algorithm.

This decoding system comprises an input terminal 11 to which a received word (RS code) is supplied, and a syndrome S
(X) calculation circuit 12, error evaluation polynomial ω (x) calculation circuit 13 using Euclidean division, error location polynomial σ (x) calculation circuit 14 using product-sum operation, Chien search circuit 15, delay It comprises a circuit 16, a correction execution circuit 17, and an output terminal 18 for extracting a decoded output from the correction execution circuit 17, and each operation is basically performed in a Galois field.

The Euclidean algorithm is described in "Coding Theory" by Shokodo, Miyagawa, Iwatari, and Imai, and its description is omitted. However, the Euclidean algorithm is a method for calculating the greatest common divisor of two integers. is there. In the decoding system described above, this method is applied to a polynomial to extract a common factor between X ^2t and the syndrome S (x), thereby obtaining an error evaluation polynomial (Error Evolutor Polynomial) and an error location polynomial (Error Locator). Polynomial).

[0005] This derivation procedure is simple, and is realized by recursively repeating division, order check, and register exchange until an end condition is satisfied. Here, t is the correction capability, and the information redundancy is added by 2t. That is,

[0006]

(Equation 1) L _i (x) is sequentially obtained so as to satisfy the following. The actual calculation is

[0007]

(Equation 2) I is sequentially incremented, and the process ends when the dimension of L _i (x) becomes t or less. Then, L _i (x) at this time becomes the error evaluation polynomial ω (x). At the same time, in the product-sum operation,

[0008]

(Equation 3) The following expression is calculated. In this case, when it is determined that the dimension of L _i (x) has become equal to or smaller than t, r _i (x) at the time when the increment of i is terminated becomes the error locator polynomial σ (x). The change in this equation is

[0009]

(Equation 4) Becomes That is, r _i-1 (x) is a term of the sum in the equation (5) from the term of the multiplier in the equation (4), and r _i (x) is a multiplier in the equation (5) from the term of the result in the equation (4). And r _i-2 (x) is discarded.

FIG. 6 shows a conventional product-sum operation circuit for performing the above product-sum operation. In FIG.
D (Delay) type FF (Flip Flo) arranged in three rows
p) A plurality of FF circuits 191, 192,... constituting the top row in the circuits 19, 20, 21 have r _i−1 among the polynomial operations expressed by the above equation (3). (X)
Is held.

Further, in FIG. 6, a plurality of FF circuits 211 and 212 constituting the lowest row, the ......, r _i-2
(X) is held. The plurality of FF circuits 201, 202,... Constituting the central row function as registers for temporarily holding the operation results in order to perform the operation for each degree in multiplication between polynomials.

First, all the contents of the FF circuits 201, 202,... Are cleared. Thereafter, when a term of the highest order of Q (x) is input, the term is multiplied by the multiplication circuit 221,
FF circuits 191, 192,.
Is multiplied by each term of the multiplier held in. The multiplication results of the multiplication circuits 221, 222,...
Are stored in the F circuits 201, 202,... Respectively.

Next, when a term of the next order of Q (x) is input, the term is multiplied by the multiplication circuits 221 and 22 in the same manner as described above.
Are multiplied by the terms of the multipliers held in the FF circuits 191, 192,. Then
This time, the multiplication results of the multiplication circuits 221, 222,... Are respectively added to the previous multiplication results stored in the FF circuits 201, 202,. . Then, each of the adding circuits 231,
The addition results of 232,...
2,... Respectively.

By repeating such an operation, the result of the first multiplication is sequentially shifted rightward in the figure. This corresponds to the fact that Q (x) is sequentially input from higher order terms. Finally, when a constant term of Q (x) is input, the term is multiplied by multiplication circuits 221, 222,.
Are multiplied by each term of the multiplier held in 1,192,....

In this case, each of the multiplication circuits 221, 222,...
Are passed through addition circuits 231, 232,..., And then added by the addition circuits 241, 242,... To the respective terms of the sum held in the FF circuits 211, 212,. You. Then, each of the adding circuits 241, 242,
.. Are stored in the FF circuits 191, 192,.

At this time, at the same time, the values of the FF circuits 191, 192,..., Which have been treated as multipliers, become sum items in the next operation step.
2, .... The above-described series of arithmetic operations shows one arithmetic operation of the ascetic expression, and this arithmetic operation of the ascetic expression is repeated until the Euclidean division processing is completed.

However, in the conventional product-sum operation circuit described above, since the operations are performed between polynomials, FF circuits of the number corresponding to the order must be provided for three columns as shown in FIG. However, there arises a problem that the scale of the hardware becomes large, which causes an economic disadvantage.

[0018]

As described above, the conventional product-sum operation circuit has a problem that the scale of hardware tends to be large, which causes an economic disadvantage. The present invention has been made in view of the above circumstances, and has as its object to provide a very good product-sum operation method that can be simplified in size, reduced in size, and economically advantageous.

[0019]

A multiply-accumulate method according to the present invention multiplies a first polynomial by a second polynomial and adds the multiplication result to a third polynomial. It is intended for those who do.

A plurality of first storage means for respectively storing the terms of each degree of the first polynomial; a plurality of second storage means for respectively storing the terms of each degree of the third polynomial; Input means for inputting a polynomial of 2 for each degree, a plurality of multiplying means for multiplying a term of a predetermined degree input by the input means and each term stored in the plurality of first storage means, A plurality of adding means for adding the respective multiplication results obtained from the plurality of multiplying means and the respective terms stored in the second storage means; and a plurality of adding results obtained from the plurality of adding means and A plurality of selection means for selectively guiding each item stored in the first storage means to a plurality of second storage means.

Further, in the above method, the product-sum operation method may further comprise a plurality of first storage means in which each degree term of the first polynomial is stored in a shiftable manner, and a third polynomial. A plurality of second storage means in which terms of each degree are respectively shiftably stored, an input means for inputting a second polynomial for each degree, and a plurality of terms of a predetermined degree input by the input means. Multiplying means for sequentially multiplying each of the terms shifted by the first storage means, and adding means for respectively adding the multiplication result obtained from the multiplication means and each of the terms shifted by the second storage means. Selection means for selectively supplying the addition result obtained from the addition means and the output of the second storage means supplied to the multiplication means to the plurality of first and second storage means, respectively. It was done.

According to each of the above methods, each of them is 2
Since it can be realized only by providing the type of storage means, the configuration can be simplified, the size can be reduced, and it is economically advantageous.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, first, the sum term r _i−2 shown in the equation (3) is first used.
The case where (x) is 0 will be described. At this time, the term r _i-1 (x) of the multiplier in the equation is calculated by the FF circuits 251, 25
2,.... In addition, the FF circuits 261, 261
62,... Are all cleared.

In such a state, the multiplier Q (x) is inputted from the higher order through the gate circuit 27. First, Q
When the highest order term of (x) is input, the term is
By the multiplication circuits 281, 282,...
Are multiplied by the respective terms of the multiplier held in 1,252,.... Each of the multiplication circuits 281, 282,...
Are passed through the adder circuits 291, 292,... (Because the value to be added is 0 at first, so that the result is through) and the selectors 301, 302,.
1, 262,....

Next, when a term of the next order of Q (x) is input, the term is multiplied by the multiplication circuits 281 and 28 in the same manner as described above.
Are multiplied by the multipliers held by the FF circuits 251, 252,. Then
This time, the multiplication results of the respective multiplication circuits 281, 282,... Are respectively added to the previous multiplication results stored in the FF circuits 261, 262,. . Then, each adder circuit 291,
292,... Are output from selectors 301, 302,
Are stored again in the FF circuits 261, 262,.

By repeating such an operation, the result of the multiplication is sequentially shifted rightward in the figure. This corresponds to the fact that Q (x) is sequentially input from a higher-order term. As the order of Q (x) decreases, the immediately preceding operation result is increased by one order. This operation is repeated until Q (x) reaches a constant term. If the constant term is finally reached, the end of equation (1) is indicated in the asperm equation, in which case the multiplier becomes the sum term in the next asperm operation. Further, one operation result is the following multiplier.

That is, when a constant term of Q (x) is input, the term is multiplied by each of the multipliers held in the FF circuits 251, 252,. Multiplied by the term. In this case, the multiplication results of the multiplication circuits 281, 282,.
, FF circuits 261, 262,.
Are added to the values held in....

Thereafter, each of the adding circuits 291, 292,...
Are added to FF circuits 251 and 251 for storing multiplication coefficients.
52,... Respectively. At this time, the selectors 301, 302,...
The multiplier output from… is selected, and the FF circuit 261,
262,... By doing so, the two terms can be exchanged at one time, and the configuration can be simplified.

Next, a case will be described in which the calculation of the sum term r _i-2 (x) is included. Since the sum value was 0 as an initial value in the first assembler expression, F that stores the sum term
The arithmetic operation is started after clearing the F circuits 261, 262,..., But if there is a value in the sum term, the order of Q (x) becomes a problem. Therefore, multiplication between polynomials +
The addition will be described with an example. As an example of this,

[0030]

(Equation 5) For the calculation formula,

[0031]

(Equation 6) The calculation contents will be explained. Where Q _i (x),
L _i−1 (x) and L _i−2 (x) are orders of 2, 2, and 1, respectively. That is,

[0032]

(Equation 7) Is obtained. However, each term of the multiplication result of Q ¹ _ix and L _i-1 (x) and each term of the multiplication result of Q ² _ix ² and L _i-1 (x) are, for simplicity, It is shown as LQx ^n.
The calculation result of Q _i (x) · L _i-1 (x) also shows the coefficient of x as ｘ for simplicity. In the actual calculation, after the multiplication is performed from the high-order term of Q, addition or shift in the middle of the calculation is performed. That is, in the conventional product-sum operation means shown in FIG.

[0033]

(Equation 8) Are performed in the calculation order. However, WR (Working Resist
er) corresponds to the FF circuits 201, 202,...
Correspond to the FF circuits 211, 212,...

However, here, (1)
By performing the processing of (5) first in the step of (1), the register storing the sum term _Li-2 (x) can be deleted. That is, in FIG.

[0035]

(Equation 9) It can be.

The problem here is (1) 'WR ← L
In term of _{i-2 (x) · x} -2, in order to have a negative index is that it requires a lower order register. Also,
There is also a process that the exponent to be multiplied is bothersomely divided. However, paying attention to the fact that the operation result does not exceed the maximum order of the register, the upper part of the register is occupied by 0 because at least the multiplier does not fill up to the highest order of the register.

By utilizing this, the sum can be realized by making the sum part of the product-sum operation that should appear in the lower order circular and returning it to the highest order. That is, in FIG. 1, it can be realized by connecting the term of the highest order and the term of the lowest order (constant term) of the FF circuits 261, 262,... Alternatively, a large number of selectors are required to perform a shift in the reverse direction in terms of a circuit, so that the same operation can be performed even if the data is circulated to the right by the order-left shift number.

Next, FIG. 2 shows a second embodiment of the present invention. In the first embodiment shown in FIG.
The value of one order of Q (x) and FF circuits 251, 252,
The multiplier stored in… is multiplied at a time. However, such a method requires a multiplication circuit and an addition circuit for the degree, and the circuit scale increases as the correction capability increases. Become.

Therefore, in the second embodiment shown in FIG. 2, the multiplication circuit is shared and the multiplication with the polynomial is performed for each order, and the circuit scale is reduced by serial operation. However, since the operation time is increased by the serial operation, the method described in the first embodiment and the method described in the second embodiment may be selectively used depending on the purpose. Good.

First, the case where the sum term r _i-2 (x) shown in equation (3) is 0 will be described. At this time, the term r _i-1 (x) of the multiplier in the same equation is
, 31n,..., 31n. Also,
The contents of each of the FF circuits 321, 322,..., 32n are all cleared.

In such a state, the multiplier Q (x) is input from the higher order. First, when the highest order term of Q (x) is input, the term is sequentially multiplied by the multiplier 33 with each term of the multiplier held in the FF circuits 321, 322,. Is done. The multiplication result of the multiplication circuit 33 is sequentially stored in the FF circuits 321, 322,..., 32 n via the addition circuit 34 (initially, the value to be added is 0 so that the result is through) and the selector 36. Is done.

Next, when a term of the next order of Q (x) is input, the term is held in the FF circuits 311, 312,... Each term of the multiplier is multiplied sequentially. Then, the multiplication result of the multiplication circuit 33 is added to the FF by the addition circuit 34 this time.
, 32n are sequentially added to the previous multiplication results stored in the circuits 321, 322,..., 32n. Then, the addition circuit 34
Is added to the FF circuit 32 via the selector 36 again.
,..., 32n are sequentially stored.

In such a multiplication operation, the FF circuit 3
Since the multipliers stored in 11, 312,..., 31n must be held, each of the FF circuits 311, 312,.
The multipliers sequentially output from...
, Are returned to the FF circuits 311, 312,..., 31 n again and stored. For this reason, when the multiplier is turned by the order of the multiplier, the multiplier becomes the original FF circuits 311 and 31.
2,..., 31n. And then Q
The next order term of (x) will be input.

After this series of operations, before the next multiplication, the result of the multiplication is shifted by one to the right in the drawing. This corresponds to the fact that Q (x) is sequentially input from a higher-order term, and as the order of Q (x) decreases,
The result of the immediately preceding operation is increased by the first order. This operation is repeated until Q (x) reaches a constant term.
When the multiplication with the constant term is finally performed, the end of equation (1) is indicated. In that case, the multiplier becomes a sum term in the next assembling operation. Further, one operation result is the following multiplier.

That is, finally, when a constant term of Q (x) is input, the term is multiplied by the multiplication circuit 33 with each term of the multiplier held in the FF circuits 311, 312,. Multiplied sequentially. In this case, the multiplication result of the multiplication circuit 33 is added by the addition circuit 34 to the FF circuits 321, 322,
,..., 32n are sequentially added.

After that, the addition result of the addition circuit 34 is supplied to the FF circuits 311, 312,.
n. At this time, the selector 36
The multipliers sequentially output from the circuits 311, 312,..., 31n are selected, and the FF circuits 321, 322,.
n. By doing so, the two terms can be exchanged without any special operation, and the configuration can be simplified. Note that FIG.
(A) to (i) show changes in the contents of each register from the initial state when t = 4 under the above conditions.

Next, a case including the operation of the sum term r _i-2 (x) will be described. As described above, the calculation of Q _i (x) · L _i−1 (x) + L _i−2 (x) is realized by storing the term of L _i−2 (x) first. . Further, although the multiplication of x ⁻² is realized by making one turn by right shift or left shift in FIG. 3, in serial operation, FF circuits 311, 312,.
Are stopped, and the FF circuits 321, 322,.
By shifting the 32n multiplication coefficient, the start timing can be changed, and the operation corresponding to the multiplication of x ⁻² can be realized without extra time or an increase in circuits. FIGS. 4A to 4I show changes in the contents of the register when t = 4 under the above conditions.

In the above-described first and second embodiments, the register is configured by using the FF circuit. However, this is achieved by, for example, a CPU (Central Processing Unit).
), MPU (Multi Processing Unit) and RAM
(Random Access Memory), a multiplication circuit and an addition circuit. In this case, a shift register-like operation can be realized by moving the operation pointer. Naturally, the sum part of the multiply-accumulate operation can be realized by shifting the position of the pointer for operations such as x- ² multiplication and using the address space (modulo and remainder for address calculation) on the loop. It is. It should be noted that the present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the scope of the present invention.

[0049]

As described in detail above, according to the present invention,
It is possible to provide a very good sum-of-products calculation method that can be simplified in configuration, reduced in size, and economically advantageous.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a product-sum operation method according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the product-sum operation method according to the present invention.

FIG. 3 is a view for explaining the operation of the second embodiment;

FIG. 4 is a view for explaining the operation of the second embodiment;

FIG. 5 is a block diagram showing an entire RS code decoding system.

FIG. 6 is a block diagram showing a conventional product-sum operation circuit used in the system.

[Explanation of symbols]

 11: input terminal, 12: syndrome S (x) calculation circuit, 13: error evaluation polynomial ω (x) calculation circuit, 14: error location polynomial σ (x) calculation circuit, 15: Chien search circuit, 16: delay circuit, 17 correction execution circuit, 18 output terminal, 191, 192, FF circuit, 201, 202, FF circuit, 211, 212, FF circuit, 221, 222, multiplication circuit , 231,232,..., An addition circuit, 241,242,..., An addition circuit, 251,252,..., An FF circuit, 261,262,. ... Multiplication circuits 291,292,... Addition circuits 301,302,..., Selectors, 311-31n FF circuits, 321-32n FF circuits, 33 Multiplication circuits, 3 ... adder circuit, 35, 36 ... selector.

Claims (3)

[Claims] 1. A multiply-accumulate method for multiplying a first polynomial by a second polynomial and adding the multiplication result to a third polynomial, wherein each degree of the first polynomial is A plurality of first storage means for storing the terms of
A plurality of second storage means for respectively storing the terms of each degree of the third polynomial; input means for inputting the second polynomial for each degree; and a term of a predetermined degree inputted by the input means A plurality of multiplying means for respectively multiplying each of the terms stored in the plurality of first storing means, and a multiplication result obtained from each of the plurality of multiplying means and each of the terms stored in the second storing means. A plurality of adding means for respectively adding the terms, and selectively adding each of the addition results obtained from the plurality of adding means and each term stored in the plurality of first storage means to the plurality of second means. A product-sum operation method comprising: a plurality of selection means for leading to storage means. 2. The method according to claim 1, wherein the plurality of second storage units include the third storage unit.
And an output end of the storage means in which the term of the lowest degree of the polynomial is stored and an input end of the storage means in which the term of the highest degree of the third polynomial is stored. 2. The product-sum operation method according to claim 1, wherein 3. A multiply-accumulate method for multiplying a first polynomial by a second polynomial and adding the multiplication result to a third polynomial, wherein each degree of the first polynomial is Are stored in a shiftable manner.
Storage means, a plurality of second storage means in which terms of each degree of the third polynomial are respectively stored in a shiftable manner, input means for inputting the second polynomial for each degree, and input means Multiplying means for sequentially multiplying the term of the predetermined degree inputted by the above and each of the terms shifted by the plurality of first storing means; and a multiplication result obtained from the multiplying means and the second storing means. Adding means for respectively adding the shifted terms; and an addition result obtained from the adding means and an output of the second storage means, which is supplied to the multiplying means, are selectively used as the plurality of first and second signals. And a selection means for supplying the sum to the second storage means.