JPH10209874A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the A/D converter at a high gain almost without no noise with miniaturization by adopting an integration device of differential operation and the transmission null point technology and configuring an inverter with a current mirror circuit. SOLUTION: The A/D converter is provided with a subtractor 1, an integration circuit 2, an adder 7, a comparator 5 and a D/A converter 6. The integration circuit 2 is configured to be four stages, differential operation integration devices are adopted for pre-stage integration devices 20, 21, and single end integration devices are adopted for post-stage integration devices 22, 23. Moreover, an inverter 3 and a resistor 4 are provided to the integration devices 22, 23 to attain a shift of transmission null point. Furthermore, the inverter 3 is configured by a current mirror circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital converter for converting an analog signal into a digital signal, and more particularly to an analog-to-digital converter for performing digital conversion in a continuous system .DELTA..SIGMA.

[0002]

2. Description of the Related Art Conventionally, this kind of analog-digital converter has a configuration as shown in FIG. That is,
A subtractor 100 is provided on the input side of the analog signal Ain, and a single-ended integrator 11 is provided on the output side of the subtractor 100.
0 are connected in multiple stages. The output side of each integrator 110 is connected to the adder 119, the comparator 120 is connected to the output side of the adder 119, and the output side of the comparator 120 is subtracted through the digital-analog converter 130. It is configured to be connected to the container 100. Thus, when the analog signal Ain is input to the group of integrators 110 via the subtractor 100, the group of integrators 110 functions as a low-pass filter, and outputs a low-frequency analog signal to the comparator 120. Then, the comparator 120 converts this analog signal into a digital signal Dout and outputs it. The digital signal Dout is output as an output signal, and is also input to the digital-to-analog converter 130 to be converted back to an analog signal. The subtracter 100 subtracts the analog signal from the input analog signal Ain. As described above, in the ΔΣ type analog-digital converter, since negative feedback is provided, the digital signal Dout which is stable with respect to the input analog signal Ain unless the phase of the signal turns around.
Can be obtained.

[0003]

However, in the above-described conventional analog-digital converter, since the integrator 110 operates in a single-ended manner, there are the following problems. In recent years, the size of the device has been reduced, and the power supply voltage has been reduced. In such a device, the analog-to-digital converter of the continuous ΔΣ method described above is often used. However, when the power supply voltage is low, the dynamic range of the operational amplifier 111 of the integrator 110 is reduced because the integrator 110 operates in a single end, and the characteristic of the analog-digital converter is correspondingly reduced. In the analog-to-digital converter of the ΔΣ system, since the oversampling is performed, the sampling rate needs to be reduced by a digital filter. For this reason, the analog-digital converter of the ΔΣ system is incorporated in the same IC chip as the digital filter. Therefore, if the integrator 110 of the analog-to-digital converter operates in a single-ended manner, digital noise enters from the IC substrate or power supply, deteriorating the characteristics of the analog-to-digital converter.

On the other hand, it is conceivable that the integrator 110 is replaced with an integrator 140 having a differential operation as shown in FIG. However, as shown in FIG. 13, the integrator 140 in the differential operation is an integrator 1 in which the capacitor and the resistor have a single-ended operation.
Twice as much as 10 is required. Therefore, if all the integrators 110 are replaced with the integrators 140 that operate differentially, the size of the analog-digital converter itself increases.

[0005] Further, using the technique of moving the transmission zero point, ΔΣ
It is conceivable to improve the characteristics of the analog-to-digital converter of the system. As shown in FIG. 14, the technique of moving the transmission zero point is to connect an inverter 150 and a resistor 160 to two integrators 110, invert the output waveform of the integrator 110 at the subsequent stage by the inverter 150, This is a technique of feeding back to the integrator 110 at the previous stage via the controller 160. In a discrete switched capacitor type analog-to-digital converter, this technique is often used because the polarity of a waveform can be easily inverted by changing a switch. However, in a continuous analog-to-digital converter, as shown in FIG.
An operational amplifier 151 and resistors 152 and 153 are required.
The circuit configuration becomes large. Further, in order to invert the polarity, a resistor 160 having a resistance value of an unrealistic magnitude of mega ohms is required. For this reason, continuous analog-to-digital converters do not employ the technique of moving the transmission zero.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and uses a differential operation integrator and a transmission zero point technique, and configures an inverter with a current mirror circuit, thereby achieving high gain and noise reduction. It is an object of the present invention to provide an analog-to-digital converter that is hardly available and can be reduced in size.

[0007]

In order to solve the above-mentioned problems, the present invention comprises a subtractor for subtracting an input analog signal from a feedback analog signal, and an integrator having three or more stages.
An integrator circuit that functions as a low-frequency pass filter for the analog signal from the subtractor, an adder that adds the integrator output of each stage, and a comparator that converts the analog signal output from the adder into a digital signal And a digital-to-analog converter that converts the digital signal from the comparator into an analog signal and outputs it as a feedback analog signal to the subtractor, among three or more stages of integrators. At least the first stage integrator is configured as a differential integrator, and the subsequent stages are configured as single-ended integrators. With this configuration, when an analog signal is input to the subtractor, the analog signal is subtracted from the feedback analog signal from the digital-analog converter, and the result is output to the integrator circuit. Then, the analog signal in the low frequency band passes through the integrator circuit due to the operation of the integrator circuit. At this time,
The noise that jumps into the analog signal from the subtraction unit is removed by the integrator of the differential operation. Also, due to the characteristics of the integrator, an analog signal is output from the integrator circuit unit to the comparison unit without being affected by the fluctuation of the power supply voltage. Then, in the comparing section, the analog signal from the integrator circuit section is converted into a digital signal. This digital signal is
The analog-to-analog conversion is performed by the digital-analog conversion unit, and the converted analog signal is output to the subtraction unit.

Further, in the above invention, an invertor and a resistor are connected in a loop to at least a pair of integrators of the single-ended operation, and an inverted voltage of a voltage output from the pair of integrators is provided. By inputting a feedback current that is proportional to the resistance value and inversely proportional to the resistance value of the resistor to the pair of integrators, the transmission zero point can be moved, thereby increasing the gain of the integrator circuit in a frequency band lower than the zero point. And the quantization noise generated in the comparison unit is reduced.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an analog-digital converter according to one embodiment of the present invention. The analog-digital converter is a subtractor 1
(Subtractor) and fourth-order integrator circuit 2 (integrator circuit)
, An adder 7 (addition unit), a comparator 5 (comparison unit), and a digital-analog converter 6 (digital-analog conversion unit).

The subtracter 1 is a device for subtracting the input analog signal Ain from the feedback analog signal A from the digital-analog converter 6, and is arranged at the forefront. The integrator circuit 2 functions as a low-pass filter for the analog signal Ain 'from the subtractor 1, and includes four stages of integrators 20 to 23, an inverter 3, and a resistor 4 connected in series. Have been. The adder 7 includes four integrators 20 to 23
Are connected to the outputs of the integrators 20 to 23, and the output is connected to the comparator 5. The comparator 5 is a device that converts a low-frequency analog signal that has passed through the integrator circuit 2 into a digital signal Dout, and its output side is connected to an output terminal 80 and an input terminal of the digital-analog converter 6. ing. The digital-analog converter 6 converts the digital signal Dout from the comparator 5 into a feedback analog signal A,
This is a device that inputs to the subtractor 1.

Here, the integrator circuit 2 which is a main part of this embodiment will be described in detail. As described above, in the analog-digital converter, the subtractor 1, the integrator circuit 2, the adder 7, the comparator 5, and the digital-analog converter 6 form a closed loop of the Δ６ system. Is determined by the resolution of the digital-analog converter 6, the noise floor is determined, has no frequency characteristics, and is flat. However, since there is an integrator circuit 2 having a frequency characteristic functioning as a low-pass filter in the closed loop, the characteristic becomes flat at a certain point without the inverse characteristic (high-pass characteristic). There is no. Those having such inverse characteristics are quantization errors. The quantization error occurs when the comparator 5 converts an analog signal into a digital signal Dout. Since the quantization error has the inverse characteristic, that is, the high-pass characteristic as described above, the noise floor has a noise floor higher than the resolution of the digital output of the comparator 5 in the low band of the audio band. In other words, the noise floor is opposite to the gain of the integrator circuit 2, and as shown in FIGS. 2 and 3, the higher the order of the integrator circuit 2, the higher the gain of the integrator circuit 2,
The noise floor of the digital signal Dout from the comparator 5 becomes lower. In this embodiment, focusing on this point, FIG.
As shown in the figure, the integrator circuit 2 has a fourth order, that is, integrators 20 to 2.
3, a high gain of the integrator circuit 2 and a low noise floor of the output of the comparator 5 are realized.

As described above, the output of the comparator 5 has a low noise floor by making the integrator circuit 2 of a quartic order, but all the integrators 20 to 2 constituting the integrator circuit 2 are formed.
3 for single-ended operation, this analog-
The operating characteristics of the analog-to-digital converter are degraded due to the influence of noise from the IC substrate in which the digital converter is incorporated, the noise of the integrator, particularly the first-stage integrator 20 itself, and the noise due to the fluctuation of the power supply voltage. Therefore, the integrator circuit 2 of this embodiment is configured as shown in FIG.
That is, the first-stage integrator 20 and the second-stage integrator 21, which determine the characteristics of the ΔΣ analog-to-digital converter, are integrators for differential operation, and the integrators 22, 23 at the subsequent stage are integrators for single-ended operation. And Specifically, the integrator 20
Operational Amplifier 20a (21a) Forming (Integrator 21)
Between the input terminal and the output terminal of the
c (21b, 21c) and the operational amplifier 20a (2
Resistors 20d and 20e (21d) were connected to the output terminal of 1a). As a result, in the integrators 20 and 21, positive-phase and negative-phase signals are input to the input terminals of the operational amplifiers 20a and 21a, and a signal representing the difference therebetween is output. For this reason, the noise of the same level that jumps into the two input terminals from the IC substrate is subtracted and does not appear in the output of the integrator 21. Also, the level of the output signal of the integrators 20 and 21 of the differential operation is twice as high as the output level of the integrator of the single-ended operation. It is advantageous. An integrator having such a differential operation is referred to as an integrator 2
It is conceivable that the present invention is applied to all of Nos. 0 to 23. However, in such a case, the capacitor and the resistance are doubled, and the analog-digital converter itself becomes large. Therefore, in this embodiment, only the integrators 20 and 21 are operated in a differential manner, thereby realizing the miniaturization of the analog-digital converter while removing noise and improving the S / N ratio.

The integrator circuit 2 is shown in FIGS.
The gain and quantization noise shown in (1) to (5)
23 are connected in four stages, the frequency characteristics of such integrators 20 to 23 have a slope even in the audio band, and the quantization noise level is high at the high frequency level in the band. Almost decided. Therefore, in this embodiment, a technique of moving the transmission zero point, which changes the frequency characteristics of the integrator to improve the characteristics of gain and quantization noise, is applied.
That is, as shown in FIG. 1, the inverter 3 and the resistor 4 were connected between the input terminal of the single-ended integrator 22 and the output terminal of the integrator 23. In this case, the transmission zero is a pole created by a closed loop of the inverter 3, the resistor 4, and the integrators 22, 23. Here, the movement of the pole will be described in detail with reference to FIG. In FIG. 14, two integrators 1
10 as integrators 22 and 23, inverter 150 and resistor 1
60 will be described as the inverter 3 and the resistor 4. Integrator 2
Reference numerals 2 and 23 denote integrators of single-end operation. The integrators 22 and 23 have a configuration in which a capacitor 22b is connected to an operational amplifier 22a.
The configuration is such that a capacitor 23b is connected to 3a.
These operational amplifiers 22 a and 23 a are connected via a resistor 24. At this time, unless the inverters 3 and the resistors 4 are connected to the integrators 22 and 23, the pole ωp of these integrators is 0 Hz. However, by providing the inverter 3 and the resistor 4, the pole ωp moves from 0 Hz. That is, assuming that the capacitances of the capacitors 22b and 23b are C1 and C2, the resistance values of the resistors 4 and 24 are R1 and R2, the frequency of the input voltage Vin is ω, and the imaginary number is j, the integrator 2
2, 23 are expressed by the following equation (1).
Is represented by the following equation (2). Here, s is “jω”.

(Equation 1) As a result, the gain of the integrator circuit 2 has the waveform shown in FIG. 5, and the quantization noise of the output of the comparator 5 has the waveform shown in FIG. That is, when the inverter 3 and the resistor 4 are not provided, the gain and the quantization noise become the broken lines shown in FIGS. That is, the pole ωp is 0 Hz. However, by providing the inverter 3 and the resistor 4 and applying the transmission zero point moving technique, the pole ωp moves by the value represented by the above equation (2). And
The broken line portion shown in FIG. 5 is transformed into a waveform A which is non-linear and shows a high gain, and the broken line portion shown in FIG. 6 is transformed into a waveform B which is non-linear and shows a low quantization noise. As a result, the gain of the integrator circuit 2 is improved in a frequency band lower than the pole ωp.
Also, without increasing the order of the integrator circuit 2, the comparator 5
Can be reduced.

In the inverter 3 and the resistor 4 provided to form the pole ωp as described above, the output of the integrator 23 is inverted, and a current of I = −Vout / R1 may flow through the integrator 22. However, it is necessary to prevent the structure of the inverter 3 from becoming large and the resistance value R1 of the resistor 4 from becoming unrealistic. Therefore, in the inverter 3 of this embodiment,
As shown in FIG. 4, the output from the integrator 23 is inverted, and the resistance value R1 of the resistor 4, which is actually a small resistance value, is artificially increased. Specifically, an inverter (field effect transistor) 30 in which a constant voltage is applied to the source and the gate and the drain are short-circuited is connected to the inverter 3.
And a current mirror circuit composed of an FET 31 having a gate connected to the gate of 30 and a constant voltage applied to the source. The drain of the FET 30 is connected to the output terminal of the integrator 23 via the resistor 4, and the FET 31 Is connected to the negative input terminal of the integrator 22.

FIG. 7 is a circuit diagram showing the operation principle of the inverter 3. The voltage V between the drain of the FET 30 and the resistor 4
0 is a DC voltage that hardly changes. Therefore, when the Vout shown in FIG. 14 is applied to the input side of the resistor 4, the FET 31 outputs a feedback current Iout represented by the following equation (3). Here, n1 is a current mirror coefficient.

(Equation 2) As is apparent from this equation, the feedback current Iout includes V0 /
n1 · R1 DC offset current is included, but -Vout
There is also a negative feedback current of magnitude / n1R1. FET
This feedback current input to 31 (-V0 / n1R1)
Is regarded as if the resistance value had flowed through the resistor 4 of n1 · R1. That is, although the actual resistance value of the resistor 4 is small R1, it can be simulated as if the resistor 4 has a very large resistance value n1 · R1.

Next, the operation of the analog-digital converter of this embodiment will be described. In FIG.
When the analog signal Ain is input to the subtractor 1, the analog signal Ain and the feedback analog signal A from the digital-analog converter 6 are subtracted, and output to the integrator circuit 2 as an analog signal Ain '. This analog signal Ain
Is filtered by the fourth-order integrator circuit 2, and a low-frequency signal is output from the integrator circuit 2 to the comparator 5 through the adder 7. Then, the signal input to the comparator 5 is converted into a digital signal Dout and output to the output terminal 80.
Further, the digital signal Dout from the comparator 5 is returned to the digital-analog converter 6, converted into a feedback analog signal A, and output to the subtractor 1. During the operation of such a closed loop, the gain characteristic of the integrator circuit 2 and the quantization noise characteristic of the comparator 5 become problematic. However, since the integrator circuit 2 has a quartic configuration of the integrators 20 to 23. , FIGS. 2 and 3
As shown in the above, these characteristics are considerably corrected in the low frequency band.

Further, since the first-stage integrator 20 and the second-stage integrator 21 of the integrator circuit 2 are integrators of differential operation, noise that enters the integrator 20 from the IC substrate is reduced by the integrator 20. 20 and 21. Further, even if the power supply voltage fluctuates, the outputs of the integrators 20 and 21 are not affected, and the S / N ratio is doubled.

As described above, the integrators 20 and 21 of differential operation are used.
The signal from which noise from the outside has been removed is output via integrators 22 and 23 of single-ended operation. These integrators 22 and 23 are provided with an inverter 3 and a resistor 4 to move the transmission zero point. As a result, the gain of the integrator circuit 2 is further improved in a frequency band lower than the pole ωp as shown in FIG. Further, the quantization noise generated when converting the signal from the integrator circuit 2 into the digital signal Dout is also shown in FIG.
As shown in FIG.

As described above, according to the analog-digital converter of this embodiment, the gain of the integrator circuit 2 can be increased, and the capability of removing quantization noise can be improved. In addition, since the inverter 3 is constituted by a current mirror circuit having a simple structure as shown in FIG. 4, the transmission zero point shift can be achieved with the resistor 4 having a small resistance value R1. The size of the converter can be reduced. Also, the integrators 20 to
23 are not used as integrators for differential operation,
Since the circuits 2 and 23 are single-ended, the circuit area can be reduced accordingly.

The present invention is not limited to the above-described embodiment, and various modifications and changes can be made within the scope of the present invention. In the above embodiment, the fourth-order integrator circuit 2 composed of the integrators 20 to 23 is applied as the integrator circuit unit. Of course, a circuit can be configured. For example, as shown in FIG. 8, the integrator circuit has a sixth-order configuration using six stages of integrators 20 to 26, and the integrators 22 and 23 and the integrators 25 and 2 of the single-ended operation.
6 and the inverter 3 and the resistor 4 respectively. Thus, by providing two sets of two integrators, inverters, and resistors, two poles ωp shown in FIGS. 5 and 6 can be formed. Further, the integrator circuit only needs to have at least the first-stage integrator performing a differential operation, and may have a configuration in which the integrators in the second and subsequent stages are single-ended. Alternatively, the integrators in the first to multiple stages may be operated in a differential manner, and the remaining integrators may be operated in a single-ended manner.

In the above embodiment, the inverter 3 is constituted by a P-channel current mirror circuit.
May be configured by an N-channel current mirror circuit, and a resistor 4 may be connected to the current mirror circuit. Further, in the above embodiment, the inverter 3 is constituted by only one current mirror circuit. However, as shown in FIG. 9, the P-channel current mirror circuit 3-1 is replaced with the N-channel current mirror circuit 3-2. And the P-channel current mirror circuit 3-3 may be sequentially connected. As a result, the feedback current Iout becomes a value represented by the following equation (4).

(Equation 3) That is, by connecting the current mirror circuits 3-1 to 3-3 as described above, the resistance value of the resistor 4 is apparently changed.
It can be as large as n1, n2, n3, R1. Therefore, by connecting the circuits indicated by broken lines in FIG. 9 in a plurality of stages, the feedback current can be made to have the magnitude shown in the following equation (5), and a larger apparent resistance value can be obtained. Further, as shown in FIG. 10, two P-channel current mirror circuits 3-1 and 3-3 can be connected in series to form a more accurate inverter.

(Equation 4) Further, in the above embodiment, the current mirror circuit is constituted by the field effect transistors 30 and 31, but may be constituted by bipolar transistors 30 'and 31' as shown in FIG. That is, a current mirror circuit is composed of a bipolar transistor 30 'in which a constant voltage is applied to the emitter and the base and collector are short-circuited, and a bipolar transistor in which the base is connected to the base of the bipolar transistor 30' and the constant voltage is applied to the emitter. 31
The collector of the bipolar transistor 30 ′ is connected to the output terminal of the integrator 23 via the resistor 4, and the collector of the bipolar transistor 31 ′ is connected to the negative input terminal of the integrator 22.

[0022]

As described above in detail, according to the analog-to-digital converter of the present invention, among the integrators of the integrator circuit section, at least the first-stage integrator is a differential-operation integrator. It is possible to improve the elimination of noise from the outside and to prevent the influence of the fluctuation of the power supply voltage. As a result, there is an effect that the operation characteristics of the analog-digital converter can be improved. Further, an inverter and a resistor are provided in a pair of integrators for single-ended operation,
Since the transmission zero point can be shifted, the gain of the integrator circuit can be improved, and the quantization noise can be reduced. As a result, the operating characteristics can be further improved. Further, by configuring the inverter with a current mirror circuit, the structure of the inverter can be simplified. Then, since a feedback current that is inversely proportional to the current mirror coefficient times the resistance value can be obtained, in practice, a small, small resistance value can be simulated as a large resistance value. The size of the converter can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an analog-digital converter according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a relationship between an order and a gain of an integrator circuit.

FIG. 3 is a diagram showing a relationship between an order of an integrator circuit and quantization noise.

FIG. 4 is a circuit diagram of an integrator circuit.

FIG. 5 is a diagram showing the relationship between the poles and the gain of the integrator circuit.

FIG. 6 is a diagram showing the relationship between poles and quantization noise.

FIG. 7 is a circuit diagram showing the operation of the inverter.

FIG. 8 is a circuit diagram showing a modified example of the integrator circuit.

FIG. 9 is a circuit diagram showing a first modification of the inverter.

FIG. 10 is a circuit diagram showing a second modification of the inverter.

FIG. 11 is a circuit diagram showing a third modification of the inverter.

FIG. 12 is a block diagram showing an analog-digital converter according to a conventional example.

FIG. 13 is a circuit diagram showing a state in which a plurality of stages of differential operation integrators are connected.

FIG. 14 is a circuit diagram for explaining a transmission zero point moving technique.

FIG. 15 is a circuit diagram showing a structure of a conventional inverter.

[Explanation of symbols]

1 ... subtractor, 2 ... integrator circuit, 3 ... inverter, 4 ... resistor, 5 ... comparator, 6 ...
Digital-analog converter, 7 ... adder.

Claims (5)

[Claims] An integrator circuit having a subtraction unit for subtracting an input analog signal from a feedback analog signal, and an integrator having three or more stages, and functioning as a low-frequency pass filter for the analog signal from the subtraction unit. , An adder that adds the integrator outputs of the respective stages, a comparator that converts an analog signal output from the adder into a digital signal, and converts the digital signal from the comparator into an analog signal; A digital-to-analog converter that outputs the feedback analog signal to the subtractor, wherein at least the first stage of the three or more stages of integrators performs differential operation integration. An analog-to-digital converter, wherein an integrator in a subsequent stage is an integrator of single-ended operation. 2. The analog-digital converter according to claim 1, wherein an inverter and a resistor are connected in a loop to at least a pair of integrators of the single-ended operation.
By inputting a feedback current proportional to the inversion voltage of the voltage output from the pair of integrators and inversely proportional to the resistance value of the resistor to the pair of integrators, transmission zero point movement is enabled. An analog to digital converter. 3. The analog-digital converter according to claim 2, wherein said inverter is constituted by a current mirror circuit capable of generating said feedback current inversely proportional to a current mirror coefficient times said resistance value. An analog-digital converter characterized by the above-mentioned. 4. The analog-to-digital converter according to claim 3, wherein said current mirror circuit is constituted by a field-effect transistor. 5. The analog-to-digital converter according to claim 3, wherein said current mirror circuit is constituted by a bipolar transistor.