JPH10209851A - Level shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the level shift circuit with a small number of components, a simple structure and a small through-current. SOLUTION: The level shift circuit 10 is configured with series connection of P channel transistors(TRs) 11, 12 and an N channel TR 13. Gates of the P-channel TRs 11, 12 and the N channel TR 13 are connected in common to form an input and the source and the drain of the P channel TR 12 and the N channel TR 13 are connected to form an output. When a signal with a logic level at which the N channel TR 13 is conductive is received, a voltage drop by a through-current going to flow through the N-channel TR 13 and an ON- resistance of the P channel TR 11 acts like a negative feedback to the P channel TR 12 so as to bring the P channel TR 12 close to an off-state thereby reducing the through-current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a level shift circuit, and more particularly to a level shift circuit serving as an interface between circuits operating at different power supply voltages.

[0002]

2. Description of the Related Art Conventionally, when connecting logic circuits having different power supply voltages, it is necessary to shift the level of a signal output from one of the logic circuits in accordance with the logic level of the receiving logic circuit. The level shift circuit is a circuit used for such a purpose, and a typical example is shown below.

FIG. 6 is a circuit diagram showing an example of a conventional level shift circuit. In this figure, the level shift circuit has two transistors T1 and T2, an inverter I1 which operates with the power supply voltage (3 volts) of the input side circuit, and two inverters which operate with the power supply voltage (6 volts) of the output side circuit. It is composed of inverters I2 and I3. The input terminal 1 is connected to the gate of the transistor T1 and the input of the inverter I1.
2 gates. The source of the transistor T1 is grounded, the drain is the output terminal 2, the inverter I2
And the output of the inverter I3. The source of the transistor T2 is grounded, and the drain is connected to the output of the inverter I2 and the input of the inverter I3. In this example, the input signal 3
, The high (H) level is 3 volts, the low (L) level is 0 volts, and the logic level of the output signal 4 is 6 volts for the high (H) level and 0 volts for the low (L) level.

Here, when the logic level of the input signal 3 is H, the transistor T1 is turned on, so that the inverter I
2 has a lower potential, which causes the inverter I2
Output potential rises. At this time, since the input potential of the inverter I3 rises, the function of lowering the potential of the output terminal 2 more reliably is achieved, and an L-level signal is output to the output terminal 2. Further, since the input potential of the inverter I1 is high, the output is 0 volt, and the transistor T2 is off.

Conversely, when the logic level of the input signal 3 becomes L, the transistor T1 is turned off, and the inverter I1 inverts the level to bring the output potential to 3 volts. Then
The transistor T2 is turned on to lower the input potential of the inverter I3. As a result, the potential of the output of the inverter I3 increases, and an H-level signal is output to the output terminal 2. At this time, since the input potential of the inverter I2 increases, the function of lowering the input potential of the inverter I3 more reliably is achieved. In this manner, the level shift circuit can convert the input signal 3 from the logic circuit having the power supply voltage of 3 volts into the output signal 4 having the logic level of H of 6 volts.

FIG. 7 is a circuit diagram showing another example of a conventional level shift circuit. In this figure, the level shift circuit 5 comprises only two transistors T3 and T4 connected in series to a 6 volt power supply. The gates of these transistors T3 and T4 are connected to each other to form an input terminal, and the drains are connected to each other to form an output terminal. The logic circuit 6 on the input side has the same configuration, and a power supply voltage of 3 volts is applied.

Here, when an H level signal is input to the input of the level shift circuit 5 via the logic circuit 6,
The transistor T3 turns off and the transistor T4 turns on. As a result, the potential of the output terminal drops to 0 volt, and an L level signal is output.

Next, when an L-level signal is input from the logic circuit 5, the transistor T3 is turned on, the transistor T4 is turned off, and the output terminal has an H potential of 6 volts. The level signal is output. In this way, the level shift circuit can transfer a signal from the logic circuit 6 having a power supply voltage of 3 volts to a logic circuit operating at a power supply voltage of 6 volts.

[0009]

However, the level shift circuit shown in FIG. 6 has a problem that the number of elements such as transistors and inverters is large. Therefore,
For example, in a circuit such as a decoder that requires a number of level shift circuits in one circuit, the area occupied by the level shift circuit becomes very large. On the other hand, in the level shift circuit shown in FIG. 7, since the number of elements is very small, the mounting area on the circuit board is small, and in the case of an IC, the degree of integration can be increased. However, when the input signal is at the H level, the transistor T
3 should be turned off, but there is a problem that it is not completely turned off. This is because even if a signal of H level (3 volts) is input to the gate of the transistor T3, there is a difference of -3 volts from the power supply voltage (6 volts) of the level shift circuit. Voltage between the two. Therefore, when the gate-source voltage is larger than the threshold voltage of the transistor T3, the transistor is not completely turned off, and a large through current constantly flows from the power supply line to the ground.
As a result, the current consumption increases, so that it cannot be used for a power-saving circuit.

[0010] The present invention has been made in view of the above points, and has as its object to provide a level shift circuit which consumes less power while reducing the number of circuit elements.

[0011]

According to the present invention, in a level shift circuit connected to an output side circuit operating at a voltage different from the power supply voltage of an input side circuit, a first transistor of a first conductivity type channel is provided. And the second transistor and the third transistor of the second conductivity type channel are connected in series, and the power supply voltage of the output side circuit is applied to both ends of the series connection. A level shift circuit having a configuration in which the gates of the three transistors are connected together to serve as an input, and the common connection point between the second transistor and the third transistor is used as an output. You.

According to the above configuration, by switching the logic level of the input signal, the first transistor and the second transistor are turned on and the third transistor is turned off from the logic state where the third transistor is turned off. And the second transistor is turned off, and the logic state is switched to the third transistor being turned on. At that time, the first transistor and the second transistor are turned off.
Transistors do not turn off completely. Therefore, the current flowing through the first transistor and the second transistor tends to flow as a through current via the third transistor. At this time, a voltage drop occurs in the second transistor due to the current and the on-resistance of the first transistor, which acts as a negative feedback to the second transistor, and turns off the second transistor as much as possible. Get closer. As a result, the first transistor and the second transistor are turned off, and as a result, a through current does not flow and a level shift circuit in which current consumption is significantly reduced is obtained.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a principle configuration of a level shift circuit according to the present invention. In FIG. 1, a level shift circuit 10 of the present invention is connected between a sending circuit 20 for sending a signal and a receiving circuit 30 for receiving the signal. The level shift circuit 10 is configured by connecting two P-channel transistors 11 and 12 and one N-channel transistor 13 in series. The gates of these transistors are connected together to form an input terminal of the level shift circuit 10, and a common connection point between the P-channel transistor 12 and the N-channel transistor 13 forms an output terminal of the level shift circuit 10. I have. The sending circuit 20 is configured by connecting one P-channel transistor 21 and one N-channel transistor 22 in series, and the power supply voltage is, for example, 3 volts here. On the other hand, the receiving circuit 30 is also formed by connecting one P-channel transistor 31 and one N-channel transistor 32 in series, and the power supply voltage is set to, for example, 6 volts, which is higher than that of the sending circuit 20. The power supply voltage applied to the level shift circuit 10 is
6 volts.

The two Ps constituting the level shift circuit 10
When W is the width of the P channel and L is the length of the P channel, the channel transistors 11 and 12 and the N channel transistor 13 determine the W / L ratio of the P channel transistor 11, that is, W / L, by the P channel transistor 12 And an element relatively smaller than the W / L of N-channel transistor 13 is used. Thereby, the on-resistance of the P-channel transistor 11 is made sufficiently larger than the on-resistance of the P-channel transistor 12 and the N-channel transistor 13, and the on-resistance of the P-channel transistor 12 and the N-channel transistor 13 is made as small as possible. .

Here, the operation of the level shift circuit 10 will be described. First, the L level (0
(Volts), the P-channel transistors 11 and 12 are turned on, and the N-channel transistor 13 is turned off. As a result, an H-level signal having a potential of 6 volts is output to the output terminal of the level shift circuit 10. At this time, the P-channel transistor 11 has its gate-source voltage V _gs
, The on-resistance is small.

Next, when an H level (3 volt) signal is input from the transmission side circuit 20, the N-channel transistor 13 is first turned on. On the other hand, the P-channel transistors 11 and 12 try to be turned off,
At this time, since these gate-source voltages V _gs are larger than the threshold voltage V _th , they are not completely turned off. Therefore, at this time, a through current tends to flow momentarily between the power supply line and the ground via the N-channel transistor 13 which is turned on. At this time, since the gate-source voltage V _gs of the P-channel transistor 11 is smaller than the threshold voltage V _th and the on-resistance is increased, the voltage drop due to the current and the on-resistance of the P-channel transistor 11 is reduced. P-channel transistor 1
1 occurs between the source and the drain. For this reason, the source-side potential of the P-channel transistor 12 becomes considerably lower than the power supply voltage due to the voltage drop, and as a result,
Since the gate-source voltage V _{gs of the} P-channel transistor 12 is also reduced, the P-channel transistor 12 can be brought closer to the off state as much as possible. As a result, almost no through current flows from the power supply line to the ground.

In this case, the P-channel transistor 11
Is acting as a negative feedback for the P-channel transistor 12. Also, since the on-resistance of the transistor is used instead of using a simple resistor for the negative feedback of the transistor, the on-resistance is large only at the timing when the negative feedback is required, and at the timing when the negative feedback is not required. The on-resistance of the transistor is small. Therefore, the time constant of the circuit is smaller than in the case where the resistance component is always present, so that the circuit operation can be sped up.

According to such a level shift circuit 10, a circuit operating at a certain power supply voltage and at a higher power supply voltage can be driven without a large through current. Moreover, it can be realized with a simple circuit having a small number of transistor elements.

Next, the embodiment of the present invention will be described with reference to DC-DC.
An example in which the present invention is applied to a converter device will be described. FIG. 2 is a block diagram showing an example of application to a DC-DC converter device. The DC-DC converter 40 has an input terminal 4
1 and an output terminal 42 for receiving a certain DC voltage, converting it to another DC voltage, and outputting it. This DC-
The DC converter 40 includes a charge pump voltage converter 43 that actually performs voltage conversion, a comparator 44 that generates a feedback error voltage, an oscillator 45 that generates an internal clock based on the error voltage from the comparator 44, and a comparator Oscillator 46 for generating a clock based on an error voltage from 44 and an external clock
And a two-phase clock generation circuit 47 for generating clocks having different rising and falling timings from the clocks generated by the oscillators 45 and 46.
And a level shifter 48 as a different voltage interface. As an external element to the DC-DC converter 40, a charge pump voltage converter 43
, A capacitor 50 connected to the output terminal 42, and two resistors 51 and 52 for dividing the output voltage and supplying the divided voltage to the non-inverting input of the comparator 44.
There is. Then, a reference voltage is applied to the inverting input of the comparator 44.

Here, it is assumed that a DC voltage of, for example, 3 volts is input to input terminal 41 and a DC voltage of, for example, 6 volts is output to output terminal 42. The level shifter 48 corresponds to the level shift circuit 10 of FIG. 1, and the level shifter 48 and the charge pump voltage converter 43 surrounded by a broken line.
Is a portion that operates with the output voltage (6 volts), and a portion where the other comparator 44, oscillators 45 and 46, and the two-phase clock generation circuit 47 operate with the input voltage (3 volts) supplied to the input terminal 41. is there.

In the two-phase clock generation circuit 47, 3
A clock having a peak value of volts is generated, and the clock is supplied to a portion operating with a power supply voltage of 6 volts. At this time, since the clock is supplied through the level shifter 48 having a small through current, the current consumption in the level shifter 48 can be suppressed, so that the D with high boosting efficiency can be obtained.
A C-DC converter device can be configured.

Next, a description will be given of a level shift circuit in which the logic levels H and L of the input side and the output side are different from each other. FIG. 3 is a diagram showing a level shift circuit using P-channel transistors connected in series. The level shift circuit 60 is configured by connecting two P-channel transistors 61 and 62 and one N-channel transistor 63 in series. The input side circuit of the level shift circuit 60 is configured by connecting one P-channel transistor 71 and one N-channel transistor 72 in series. Similarly, the output side circuit is configured by one P-channel transistor 71.
A channel transistor 81 and one N-channel transistor 82 are connected in series. The input side circuit is operated by the power supply voltages Va and Vb (where Va> Vb).
The H level of the signal supplied to V. is Va, and the L level is Vb. The level shift circuit 60 and its output side circuit are connected to power supply voltages Vc and Vd (where Vc> Vd, Vd ≧ Vb,
Vc ≧ Va), the H level of the signal supplied from the level shift circuit 60 is V
The c and L levels become Vd.

In such a configuration, first, when the input of the input side circuit is at the H level (= Va), the potential V1 at the output thereof becomes the L level (= Vb). Then, the P-channel transistors 61 and 62 are turned on and the N-channel transistor 63 is turned off, so that an H level (= Vc) signal appears at the output with almost no through current flowing through the level shift circuit 60. At this time, the gate-source voltage | V of P-channel transistor 61
_gs | so large, the ON resistance of the P-channel transistor 61 is in a small state.

Next, the input of the input side circuit is at L level (= V
In the case b), the output potential V1 is at the H level (= V
a). At this moment, the P-channel transistors 61 and 62 are not completely turned off because the gate-source voltage | V _gs | is larger than the threshold voltage | V _th |, and the N-channel transistor 63 is in the on state. become.
A momentary current flows through the level shift circuit 60 for a moment. At that time, the P-channel transistor 6
1 of the gate-source voltage | V _gs | because is smaller, is larger on-resistance of the P-channel transistor 61, therefore, the potential V2 between the P-channel transistors 61 and 62, the on-resistance and current Therefore, the voltage drop is considerably lower than the voltage Vc of the power supply. As a result, the gate-source voltage | V _gs | of the P-channel transistor 62 also decreases, the P-channel transistor 62 is almost off, and almost no through current flows through the level shift circuit 60.

When the level shift circuit 60 is integrated and manufactured, the substrate of the P-channel transistor 62 can be connected to the voltage Vc line to set the substrate potential to Vc. Further, the ON resistance of the P-channel transistor 61 is increased only when negative feedback is required, so that the circuit operation can be performed at a higher speed and the layout area can be reduced as compared with a case where this portion is made simple. Furthermore, the case where Vc ≧ Va has been described as the power supply voltage of the output side circuit, but the present invention is not necessarily limited to this, and the circuit can be used as it is in a circuit having a relationship of Vc ≦ Va.

FIG. 4 is a diagram showing a level shift circuit using N-channel transistors connected in series. This configuration example shows a case where a logic circuit that operates with a large voltage on the negative side is driven. That is, the level shift circuit 9
Numeral 0 is formed by connecting two N-channel transistors 91 and 92 and one P-channel transistor 93 in series. The input side circuit and output side circuit of the level shift circuit 90 have the same configuration as that of FIG. Therefore, the input side circuit is operated by the power supply voltages Va and Vb (where Va> Vb), and the level shift circuit 90 and the output side circuit are operated by the power supply voltages Vc and Vd.
(However, Vc> Vd, Va ≧ Vc, Vb ≧ Vd).

As described above, when driving the output side circuit operating at the voltage Vd (Vb ≧ Vd), V1 is at the L level (=
Vb), when the N-channel transistor 91 is turned off, a negative feedback is applied to the N-channel transistor 92 by its on-resistance, thereby acting to make the N-channel transistor 92 as close as possible to the off-state. As a result, the level shift circuit 9 having a small through current is provided.
0 can be configured.

When the level shift circuit 90 is manufactured, the substrate of the N-channel transistor 92 is supplied with the voltage V
The substrate potential can be set to Vd by connecting to the line d. Further, since the N-channel transistor 91 is used as an element having a large resistance value when negative feedback is required, it is more effective in terms of circuit operation and layout area than a simple resistor. Further, the case where Vb ≧ Vd is described as the power supply voltage of the output side circuit has been described, but the present invention is not necessarily limited to this and may be used in a circuit having the relationship of Vb ≦ Vd.

FIG. 5 is a diagram showing a level shift circuit using a series-connected P-channel transistor and a series-connected N-channel transistor. This configuration example shows a case in which a logic circuit that operates with a large voltage on both the positive and negative sides is driven. That is, the level shift circuit 100 includes two P-channel transistors 101 and 10
2 and two N-channel transistors 103 and 104
Are connected in series, and a connection point common to the P-channel transistor 102 and the N-channel transistor 103 is used as an output terminal. The input side circuit and output side circuit of the level shift circuit 100 are shown in FIG.
And the same configuration as that of FIG. Therefore, the input side circuit is operated by the power supply voltages Va and Vb (where Va> Vb), and the level shift circuit 100 and the output side circuit are operated by the power supply voltages Vc and Vd (where Vc> Vb).
d, Vc ≧ Va, Vb ≧ Vd).

According to this configuration, the P-channel transistors 101 and 102 or the N-channel transistor 1
When the transistors 03 and 104 are turned off, the P-channel transistor 101 and the N-channel transistor 104 exhibit a large on-resistance, apply a negative feedback to the P-channel transistor 102 and the N-channel transistor 103, and
And the N-channel transistor 103 approaches the off state. This makes it possible to apply to a wide range of power supply voltage logic circuits regardless of the positive voltage and the negative voltage.

The power supply voltage of the output side circuit is Vc
The case where ≧ Va, Vb ≧ Vd has been described. However, the present invention is not limited to this case. The present invention can also be used for a logic circuit having a relationship of Vc ≦ Va or Vb ≦ Vd. Similarly, the P-channel transistor 101 and the N-channel transistor 104 function as variable resistances whose on-resistance increases only at the timing when negative feedback is required. Therefore, the circuit operation and the layout area are smaller than when a simple resistance is used. It is effective in. Further, in the example of FIG. 5, the P-channel transistor 101 and the N-channel transistor 104 functioning as a variable resistor are formed one by one, but a plurality of these may be formed.

[0032]

As described above, in the present invention, the first and second P-channel or N-channel transistors and the third N-channel or P-channel transistor are connected in series to form the first transistor. , Second
The input is constituted by the common connection point of the gates of the third and third transistors, and the output is constituted by the common connection point of the second transistor and the third transistor. As a result, it is possible to configure a level shift circuit having a very simple structure, a small through current, and a low current consumption. Further, since the number of transistor elements used is small, the circuit area can be reduced.

Since the amount of through current in the level shift circuit can be adjusted by the size ratio of the transistors connected in series, even when the withstand voltage of the output side circuit needs to be reduced due to a problem such as the oxide film withstand voltage. This can be dealt with by adjusting the amount of through current.

Further, since the basic structure of the circuit is similar to the one-stage inverter, it can be easily applied to various application circuits, and there are few restrictions on use. Moreover, since the circuit configuration is simple, the operation is stable and optimization at the design stage can be easily performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a principle configuration of a level shift circuit of the present invention.

FIG. 2 is a block diagram showing an example of application to a DC-DC converter device.

FIG. 3 is a diagram showing a level shift circuit using P-channel transistors connected in series.

FIG. 4 is a diagram showing a level shift circuit using N-channel transistors connected in series.

FIG. 5 is a diagram showing a level shift circuit using P-channel transistors connected in series and N-channel transistors connected in series.

FIG. 6 is a circuit diagram showing an example of a conventional level shift circuit.

FIG. 7 is a circuit diagram showing another example of a conventional level shift circuit.

[Explanation of symbols]

10, a level shift circuit, 11, 12, a P-channel transistor, 13, a N-channel transistor,
20: sending side circuit, 30: receiving side circuit.

Claims (5)

[Claims] 1. A level shift circuit connected to an output side circuit operating at a voltage different from a power supply voltage of an input side circuit, wherein a first transistor and a second transistor of a first conductivity type channel and a second conductivity type are connected. The third transistor of the mold channel is connected in series, the power supply voltage of the output circuit is applied to both ends of the series connection, and the gates of the first, second and third transistors are connected together. A level shift circuit having a configuration in which a common connection point between the second transistor and the third transistor is used as an output, and a common connection point between the second transistor and the third transistor is used as an output. 2. The level shift circuit according to claim 1, wherein the first transistor has an ON resistance higher than the ON resistances of the second and third transistors. 3. When the width of a channel of the first transistor is W and the length of the channel is L, the W / L ratio of the first transistor is greater than the W / L ratio of the second and third transistors. 2. The level shift circuit according to claim 1, wherein said level shift circuit is formed relatively small. 4. A level shift circuit used for an interface between circuits operating at different power supply voltages, wherein: a first transistor group in which at least two P-channel or N-channel transistors are connected in series; A second transistor group in which at least two transistors are connected in series; an input formed by commonly connecting gates of all transistors in the first and second transistor groups; and a first transistor group And an output comprising a common connection point connecting the second transistor group and the second transistor group in series. 5. The transistor of the first and second transistor groups, wherein two transistors directly connected to the output have a channel width of W,
5. The level shift circuit according to claim 4, wherein when the length of the channel is L, the W / L ratio is formed relatively sufficiently larger than the W / L ratios of all the other transistors.