JPH10209827A - Rectangular wave duty shaping device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the rectangular wave duty shaping circuit that provides an output of a switching signal with the same duty ratio as that of an input signal. SOLUTION: The device is provided with a non-overlap circuit 22 which allows a period when a noninverting signal (inverting signal) is respectively at an H level to include a period when the inverting signal (noninverting signal) is at an L level and allows a period when the inverting signal (noninverting signal) is respectively at an H level to include a period when the noninverting signal (inverting signal) is at an L level, and a differential D/A converter, e.g., is switch-controlled by an output from the non-overlap circuit 22. A replica block that configures a duty ratio detection circuit 21 of the same circuit configuration and pattern layout as those of the non-overlap circuit 22 is inserted to a pre-stage of the non-overlap circuit 22 and an input signal of a prescribed duty ratio is given to the replica block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rectangular circuit which is used in a differential type current output digital-to-analog converter, and which constitutes a switching circuit operated by a normal signal and an inverted signal obtained from one rectangular wave input signal. The present invention relates to a wave duty shaping device.

[0002]

2. Description of the Related Art When a normal signal and an inverted signal are formed based on one rectangular wave input signal, for example, an inverter 11 as an inverting circuit is used as shown in FIG. However, when a rectangular wave signal as indicated by D in FIG. 5 is input by the inverter, the inverted output signal QN is delayed with respect to the non-inverted output signal indicated by Q, and the phases of both input and output signals are inverted. At the timing, periods of the same phase corresponding to the delay time overlap. That is, Q and QN are simultaneously high (H) or low (L).
A level period occurs.

For example, a circuit called a non-overlap circuit is used for a switching operation of a differential current type digital-to-analog converter (DAC). A non-overlap circuit is a circuit in which the relationship between two output signals, ie, a normal signal and an inverted signal obtained based on one input signal, is the inverted logic of the other signal in one logical value period of H or L level. This is a circuit that outputs a signal that includes the entire value period and that includes any inverted logical value period of the other signal in one of the opposite logical value periods.

In a DAC cell, when a current source is constituted by a MOS transistor, the current between the current source transistor and the switching element is changed so that the current is not changed by the fluctuation of the source-drain voltage (VDS) of the current source transistor. It is necessary to devise a method of minimizing the fluctuation in the potential of the intermediate portion, that is, the drain of the current source transistor.

FIG. 6A shows a basic circuit configuration of a unit cell block of a DAC using MOS transistors, which comprises a current source transistor 12 composed of P-type MOS transistors and an N-type MOS transistor. And a switching element 13 to be connected in series, and grounded via a terminating resistance element 14.

In such a circuit, a bias (BIAS) is supplied to the gate of the current source transistor 12, and a code (C) which is an input signal is supplied to the gate of the switching element 13.
ODE) is supplied, and when the switching element 13 cuts off the current, the drain voltage of the current source transistor 12 increases. Therefore, in terms of the drain-source voltage VDS of the current source transistor 12, the VDS is reduced.

Here, if the voltage drops to the unsaturated region of the transistor characteristic as shown in FIG. 1B, how flat the ids (drain
Even a transistor having a (source-to-source current) characteristic loses the constant current characteristic. Such a state affects the DAC output settling time, the fluctuation of the DAC power supply, and the like when the DAC cell is switched on.

Further, the fluctuation of the drain voltage of the current source transistor 12 is affected by the Miller capacitance of the current source transistor 12 so as to affect the constant current characteristics of other DAC cells as noise of the current source control bias. And the DAC output fluctuates.

As a technique for suppressing such potential fluctuation, a differential DAC circuit is generally used. FIG. 7 shows this differential type DAC circuit, in which a current from a current source transistor 12 is supplied to a switching element 13 on the output side.
And two current paths of the dummy switching element 131 are supplied. The switching element 13 on the output side and the switching element 131 on the dummy side
Is switched alternately by a normal signal and an inverted signal of one switching input signal.

By controlling in this way, a current path is always ensured, so that the current path is not interrupted, and the voltage between the current source transistor 12 and the switching element, ie, the current source transistor 12
Of the drain voltage can be suppressed.

However, actually, an inverted signal for switching, that is, the gate input C of the output switching element 13
Dummy switching element 131 which is an inverted signal of ODE
Requires an inverting circuit to generate the gate signal CODEN. However, as described above, due to the delay of the inverting circuit, an overlap period of the same logical value occurs between the normal signal and the inverted signal. The occurrence of such an overlap period results in a period in which both switches are simultaneously turned on or turned off instantaneously in the switching operation of the DAC.

The occurrence of the simultaneous OFF period is equivalent to the fact that there is no current path flowing as in the non-differential type circuit configuration. On the other hand, the occurrence of the simultaneous ON period means that the drain voltage instantaneously decreases, that is, the drain-source voltage VDS of the current source transistor 12 increases. However, in the static characteristics of the P-type MOS transistor, Is the movement of the operating state within the saturation region if the operation is performed in advance, and if the device has a flat ids characteristic in the saturation region, constant current characteristics can be secured.

Therefore, it is conceivable to use a non-overlap circuit as shown in FIG. 8 as a circuit for generating a normal signal and an inverted signal. In this circuit, the input signal D, the non-inverted signal Q, and the inverted signal QN are as shown in FIG. 9, and during the period in which the non-inverted signal Q and the inverted signal QN are at the H level, respectively, The L-level period is included, and the H-level period of the inverted signal QN and the non-inverted signal Q includes the L-level period of the non-inverted signal Q and the inverted signal QN, respectively. That is, if such a non-overlap circuit is used, the occurrence of the simultaneous off period can be avoided even if the simultaneous on period occurs.

Even if the duty of the input signal D of the non-overlap circuit is input at a ratio of 5: 5, for example, in order to generate an H level margin period before and after the non-overlapping output Q, for example, As for the ratio of the periods of H and L in the case of the force Q, the H level increases and the L level decreases. Conversely, in the inverted signal QN, the H level is reduced and the L level is expanded. Therefore, the ratio of the duty ratio of 5: 5 cannot be maintained for both the normal rotation signal Q and the inverted signal QN.

Further, since the delay in the R / F flip-flop and the intervening delay circuit changes with the fluctuation of various conditions such as process fluctuation and power supply voltage, the duty ratio of the normal signal Q and the inverted signal QN is changed. Changes accordingly. Such a shift in the duty ratio of the output signal with respect to the input signal affects the output characteristics as a glitch error when the arrangement of the DAC cells is performed by the weighting method.

Here, the DAC of the weighted arrangement and the DAC of the monotone increasing arrangement will be described. For example, a DAC having a 4-bit digital input means that an analog output of 16 gradations can be performed.

As shown in FIG. 10, 16 DAC cells which output a current for one gradation are arranged side by side, and each DAC cell is arranged.
The cell is switched via a decoder, and the sum of the current outputs for each gray scale obtained by this operation is set as a DAC output (DACOUT).
The DAC has a monotonically increasing arrangement.

On the other hand, the DAC of the weighting type arrangement is, as shown in FIG. 11, four DAC cells which output currents with weights corresponding to 1, 2, 4, and 8 gradations. Are arranged side by side, and the total of the individual output currents obtained by operating the switches is used as the output.

For example, when an analog output for five gradations is to be obtained, the switches of the DAC cells for one gradation and four gradations are turned on, and a current flows through these DAC cells. Further, for example, when the output is changed from three gradations to four gradations, the combination operation of turning on the switches of the DAC cells of one gradation and two gradations is changed to one gradation and two gradations at the next operation timing. Are turned off, and at the same time, the switches corresponding only to the DAC cells of four gradations are turned on.

At this time, the timing at which each DAC cell turns on and the timing at which it turns off must not overlap. Such an overlap in timing causes the on or off to occur at the same time.
As shown by, the output of 7 gradations which is the sum of 3 gradations and 4 gradations when turned on at the same time, and the output of 0 gradation appears instantaneously in the DAC output waveform when it is simultaneously turned off, and the output DACOUC
It affects T as a glitch error waveform.

Therefore, in order to prevent such a glitch error from occurring, the switching of each of the ON and OFF logic values of the input signal by switching must be performed at the same timing in the DAC. That is, it is necessary to set the duty ratio of the logical values H and L of the switching input signal to 5: 5 in all DACs.

[0022]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and in response to an input signal having a duty ratio of 5: 5, a switching signal having a duty ratio of 5: 5 is output. An object of the present invention is to provide a rectangular wave duty shaping device which can be effectively applied to a differential current type digital-to-analog converter.

[0023]

A rectangular wave duty shaping apparatus according to the present invention provides an inverted signal QN and an inverted signal QN during a high level period of a non-inverted signal Q and an inverted signal QN for positive-phase and negative-phase inputs. The L level period of the normal rotation signal Q is included, and the H level period of the inverted signal QN and the normal rotation signal Q includes the L level periods of the normal rotation signal Q and the inverted signal QN. Before the non-overlap circuit that outputs a signal, a duty ratio detection circuit composed of a replica block having the same circuit configuration and the same pattern layout as the non-overlap circuit is inserted and input to the replica block. An output signal having the same duty ratio as the signal to be output is obtained.

With respect to an external input signal having a specified duty ratio input to the non-overlap circuit, the shift characteristic of the duty ratio of the output signal of one specific phase possessed by the non-overlap circuit is as follows: Detected in the preceding replica block. In other words, for the subsequent non-overlap circuit, a prediction signal that takes into account the deviation of the duty ratio in the non-overlap circuit and the deviation of the duty ratio that is completely opposite to the external input signal is input to the non-overlap circuit. And the deviation of the duty ratio of the non-overlapping output signal of the non-overlap circuit is canceled, and the output of the non-overlap circuit compensates for the duty ratio of the external input signal.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a circuit configuration thereof, and a duty ratio detection circuit using a non-overlap circuit having the same configuration as that described in FIG.
21 is provided. The input D of the duty ratio detecting circuit 21 is a rectangular wave having a duty ratio of 5: 5 shown in FIG.
ODE is input, and the inverted output A from the duty ratio detection circuit 21 changes from H level to L level as shown in FIG.
A signal with a shifted duty ratio in a state where the timing of falling to the level is slightly delayed and the logic value period of the H level is extended is output.

The terminal A of such a duty ratio detecting circuit 21
The output signal from the portion is input to the non-overlap circuit 22. This non-overlap circuit 22 is an R / S type flip-flop composed of a combination of NAND circuits.
The input signal D, the non-inverted signal Q, and the inverted signal QN in this circuit are as shown in FIG.

In the non-overlap circuit 22, the output of the non-overlap signal Q and the output of the inverted signal QN are each at the H level, and the output of the inverted signal QN and the output of the normal signal Q are at the L level. Included and inverted signal Q
The high-level periods of the N and the non-inverted signal Q include the L-level periods of the non-inverted signal Q and the inverted signal QN, respectively.

Here, the duty ratio detection circuit 21 has exactly the same circuit configuration as the non-overlap circuit 22 and is composed of a replica block having the same pattern layout. Is supplied to the input of the non-overlap circuit 22.

As described above, the non-overlap circuit 22 has a certain duty ratio deviation from the input signal. Here, the deviation characteristic of the duty ratio is grasped by a duty ratio detection circuit 21 provided in advance, and a signal having a duty ratio opposite to the grasped deviation characteristic of the non-overlap circuit 22 is output to the non-overlap circuit. Supplied as input to 22. Accordingly, the duty ratios of the non-overlapping circuit 22 in the non-overlapping circuit 22 cancel each other, and the non-overlapping circuit 22 outputs the non-overlapping circuit Q with the duty ratio of the original input signal CODE. The ratio can be 5: 5. However, the value of the deviation of the duty ratio varies depending on the configuration of the non-overlap circuit and various conditions such as a process and a power supply voltage. Therefore, as described above, the duty ratio detection circuit 21 has exactly the same circuit configuration as the non-overlap circuit 22, and is composed of a replica block having the same pattern layout.

Using such a replica block,
The deviation of the duty ratio has the same characteristics as the non-overlap circuit 22 under various operating conditions, and the replica block and the non-overlap circuit are not affected by various variations such as transistor characteristics and power supply voltage. Affected the same. That is, the duty shift signal generated by the replica block always keeps a completely opposite ratio to that of the subsequent non-overlap circuit 22.
Cancels the deviation of the duty ratio, and always maintains the same ratio as the externally input CODE as shown in FIG.

For example, if the duty ratio of H and L is 5:
In the case where there is an external input of 5, a non-overlap circuit having an output duty ratio deviation of 6: 4 will be described as an example. The inverted output QN of a replica block constituting the duty ratio detection circuit 21 will be described. (A output) is 4:
It is a signal having a duty ratio of 6 and an inverted logical value of the input signal. Next, in the non-overlap circuit 22,
The non-overlap circuit 22 has a duty ratio shift of 6: 4, and the inverted output (Q in FIG. 1) of the non-overlap circuit 22 has a duty ratio of 5: 5 which offsets the shift of the replica block. Maintain the same ratio as the input CODE.

The non-overlapping circuit 22 outputs the non-inverted output (QN in FIG. 1) in accordance with the non-inverted logic of the input signal. Or the output contained in the QN output. That is, the output of the non-overlap circuit having the duty ratio of the input signal is obtained by relatively easy circuit design of the circuit / layout design in which two sets of non-overlap circuits having exactly the same configuration are arranged in series. Characteristics can be realized.

FIG. 3 shows a configuration of a differential current type digital-to-analog converter constructed using such a rectangular wave duty shaping device as a forward / reverse signal generating circuit, and is shown in FIG. The output Q having the same duty ratio as the input signal and the inverted signal QN of the non-overlap circuit 22 of such a circuit are the differential current type digital / analog converter 23 having the same configuration as shown in FIG. Supplied to

Specifically, the differential current type digital
In the analog converter, the current from the current source transistor 31 is branched to the dummy switching element 32 and the output switching element 33. The switching elements 32 and 33 are grounded via the terminating resistors 34 and 35, respectively, and the analog conversion output DACOUT is extracted from the connection between the terminating resistor 35 and the switching element 33.

That is, in such a differential current type digital / analog converter, the signal Q shown in FIG. 2 is supplied to the gate of the output side switching element 33 and turned on during the H level period. The switching element 33 is turned on. The dummy switching element 32 is connected to the signal Q in FIG.
Controlled by N. In this case, the output side switching element 33
Is a rectangular wave signal having the same duty ratio as the input signal CODE, and highly accurate digital-to-analog conversion is executed.

Here, the dummy switching element 32 is turned on so as to surely include the OFF period of the output switching element 33, and the current path is reliably secured. That is, there is no period during which the dummy-side switching element 32 and the output-side switching element 33 are simultaneously turned off, and there is a simultaneously-on state.

As described above, the occurrence of the simultaneous ON period means that the drain voltage instantaneously decreases, that is, the drain-source voltage VDS of the current source transistor 12 increases. In the static characteristics, if the operation is performed in the saturation region in advance, the operation state is moved within the range. If the ids characteristics are flat in the saturation region, constant current characteristics can be secured.

[0038]

As described above, the rectangular wave duty shaping device according to the present invention inputs the output from the replica block supplying the input signal to the non-overlap circuit,
A rectangular wave output with the same duty ratio as the input signal is obtained from this non-overlap circuit. In particular, the REBLICA block uses exactly the same circuit configuration and pattern layout as the subsequent non-overlap circuit. Based on such an easy-to-configure circuit design, it is possible to achieve output characteristics with an accurate input signal duty ratio.For example, as a control circuit for a differential current type digital / analog converter Can be applied effectively.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a rectangular wave duty shaping device according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram for explaining the operation of the rectangular wave duty shaping device.

FIG. 3 is a diagram showing an example of the configuration of a digital-to-analog converter configured using the rectangular wave duty shaping device.

FIG. 4 is a diagram showing an example of a conventional circuit for generating a normal signal and an inverted signal from one input signal.

FIG. 5 is a signal waveform diagram illustrating the operation of the circuit in FIG. 4;

FIG. 6 is a circuit diagram illustrating a unit cell block of a conventional digital / analog converter.

FIG. 7 is a circuit diagram illustrating a unit cell block of a differential current type digital-analog converter.

FIG. 8 is a circuit configuration diagram for explaining a conventional general non-overlap circuit.

FIG. 9 is a signal waveform diagram illustrating the non-overlap circuit.

FIG. 10 is a configuration diagram illustrating a monotonically increasing digital-to-analog converter.

FIG. 11 is a configuration diagram illustrating a weighted digital-to-analog converter.

FIG. 12 is a diagram illustrating an output waveform of a digital-to-analog converter using a general non-overlap circuit.

[Explanation of symbols]

21: Duty ratio detection circuit, 22: Non-overlap circuit.

Claims (2)

[Claims] 1. A high-level period of a normal signal Q and an inverted signal QN for a normal phase and a negative phase input includes a low level period of an inverted signal QN and a normal signal Q, respectively. A non-overlap circuit for outputting a signal including a low level period of the normal signal Q and the inverted signal QN during a high level period of the inverted signal QN and the normal signal Q; And a duty ratio detection circuit, which is inserted before the circuit and has a circuit configuration identical to that of the non-overlap circuit and has a replica block with the same pattern layout, comprises: 2. The rectangular wave duty shaping device according to claim 1, wherein an output signal from said non-overlap circuit is used as a switching signal of a differential digital-to-analog converter.