JPH10209713A - Laminated-type electronic component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress production of dispersion in a stray capacitance among an input terminal, an output terminal and ground in a laminated filter. SOLUTION: A ground conductor layer for a shield 7 is provided in a dielectric body of a laminated filter. Additional conductor layers 8, 9 are provided in a same plane as the ground conductor layer 7. The additional conductor layers 8, 9 are connected to an input terminal and an output terminal of the conductor layer and placed to obtain a stray capacitance with the ground conductor layer 7. Since the ground conductor layer 7 and the additional conductor layers 8, 9 are formed to be flush with at the same time, dispersion in the stray capacitance based on dispersion in a gap between both is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated electronic component suitable for use in a mobile communication device.

[0002]

2. Description of the Related Art It is known to use a multilayer filter for a band-pass filter, a low-pass filter and the like of a mobile communication device such as a mobile phone. In this laminated filter, a conductor layer for a strip line, a conductor layer for a coupling capacitor, and a ground conductor layer for shielding are buried in a dielectric, and an input terminal conductor layer, an output terminal conductor layer, and a ground terminal conductor are provided on the outer peripheral surface of the dielectric. And a layer.

[0003]

By the way, in the above-mentioned laminated filter, the floating between the input and output terminal conductor layers on the outer peripheral surface of the dielectric and the ground conductor layer inside the dielectric and the ground terminal conductor layer on the outer peripheral surface. The capacitance (stray capacitance) varies, making it difficult to obtain the desired filter characteristics. That is, since the ground conductor layer in the dielectric and the input and output terminal conductor layers on the outer peripheral surface of the dielectric are formed by different processes, the positional relationship between the two is kept constant, and the pattern of the terminal conductor layer is maintained. It was difficult to make the-constant, and the stray capacitance fluctuated. More specifically, when a conductive paste is applied to form a terminal conductor layer on the side surface of the dielectric, the conductive paste wraps around the top and bottom surfaces of the dielectric, and the amount of wrap around varies. As a result, variations in the stray capacitance occurred.

Accordingly, an object of the present invention is to provide a multilayer hand-held electronic component capable of reducing the variation in stray capacitance.

[0005]

In order to solve the above problems and to achieve the above object, the present invention provides an element forming conductor layer and a ground conductor layer at different thickness positions inside a dielectric, In a multilayer filter provided with an external signal terminal conductor layer connected to the element forming conductor layer and an external ground terminal conductor layer connected to the ground conductor layer on the outer peripheral surface of the dielectric, An additional conductor layer is provided at the same thickness direction position as the ground conductor layer of
The present invention relates to a multilayer electronic component, wherein the additional conductor layer is connected to the external signal terminal conductor layer. In addition, as shown in claim 2, the top surface, the bottom surface, and the first,
At least a ground conductor layer and a plurality of element forming conductor layers are provided at different thickness direction positions in a prismatic dielectric having second, third and fourth side surfaces, and the first conductor of the dielectric is provided. A first terminal conductor layer is provided on a side surface, and a second terminal conductive layer is provided on a second side surface of the dielectric opposite to the first side, and the third and fourth layers of the dielectric are provided. A ground terminal conductor layer is provided on at least one of the side surfaces, and at least one of the plurality of element formation conductor layers is connected to the first terminal conductor layer on the first side surface to form the plurality of element formation layers. At least one of the conductor layers is connected to the second terminal conductor layer on the second side surface, and the ground conductor layer is connected to the ground terminal conductor layer. The same thickness as the ground conductor layer in the body At least one additional conductor layer is provided at a predetermined position, and the additional conductor layer is disposed so as to have a predetermined interval with respect to the ground conductor layer, and based on the same printing step as the printing step of the ground conductor layer. A laminated electronic component may be formed and connected to the first terminal conductor layer. It is desirable that the width of the additional conductor layer be equal to or larger than the width of the first terminal conductor layer. It is desirable that the width of the additional conductor layer is not more than twice the width of the first terminal conductor layer. In addition, it is desirable to provide first and second additional conductor layers connected to the first and second terminal conductor layers. Further, as described in claims 6 and 7, it is preferable that the additional conductor layer is formed as described in claims 3 and 4. Also, as shown in claim 8,
The ground conductor layer can be the first and second ground conductor layers. Further, a configuration having a strip line conductor layer can be adopted as described in claims 9 to 12.
Further, as described in the thirteenth aspect, the first and second strip conductor layers can be inductively coupled to each other by omitting the inter-resonator coupling capacitance conductor layer. In addition, when the strip line conductor layer is provided, it is desirable to provide the first and second ground conductor layers.
In addition, a third strip line conductor layer can be provided. Further, as described in claims 16 and 17, it is desirable that the additional conductor layer is formed in the same manner as in claims 3 and 4.

[0006]

According to the present invention, the additional conductor layer is provided at the same position in the thickness direction as the ground conductor layer. Therefore, the stray capacitance between the external signal terminal conductor layer or the first terminal conductor layer or the first and second terminal conductor layers and the ground is mainly determined by the additional conductor layer.
Since the additional conductor layer is provided in the same step in the same thickness direction position as the ground conductor layer in the dielectric, it can be formed so that there is no pattern shift between the two. As a result, the variation in the stray capacitance during mass production is reduced, and the target filter characteristics can be easily obtained. For example, when a conductive paste is applied to the outer peripheral surface of the dielectric to form a terminal conductor layer, the conductive paste wraps around to the top and bottom surfaces of the dielectric, and even if the amount of wrap around varies. Since the magnitude of the stray capacitance is determined mainly based on the additional conductor layer, it is possible to suppress the variation due to the wraparound.

[0007]

First Embodiment Next, referring to FIG. 1 to FIG. 12, a VHF in a mobile communication device or the like according to a first embodiment of the present invention will be described.
A multilayer filter as a multilayer electronic component used at a frequency higher than the band will be described. The completed laminated filter 1 schematically shown in FIG. 1 has a rectangular parallelepiped ceramic dielectric 2 having a relative dielectric constant of 30 or more, an input terminal conductor layer 3 and an output terminal conductor layer 4 as external signal terminal conductor layers, and a pair. , And an inner conductor layer embedded in the dielectric 2. Note that the input and output terminal conductor layers 3,
Reference numeral 4 denotes a strip formed at the center of the pair of side surfaces on the short side of the dielectric 2, that is, the center of the first and second side surfaces, and a part thereof protrudes from the top surface and the bottom surface. The ground terminal conductor layers 5 and 6 are made of the dielectric 2
Are provided on the pair of side surfaces on the long side, ie, the third and fourth side surfaces, and a part thereof protrudes from the upper surface and the lower surface.

The multilayer filter 1 of this embodiment is formed so as to obtain an equivalent circuit shown in FIG. In FIG. 12, an input terminal T1 is connected to a first strip line L1 via an input coupling capacitor C1, and is capacitively coupled to the first strip line L1 by capacitors C7 and C8 and inductively coupled as indicated by M. 2 is connected to an output terminal T via a coupling capacitor C2.
Connected to 2. One end of each of the first and second strip lines L1 and L2 is connected to ground, and the other end is connected to ground via capacitors C3 and C4 for obtaining a wavelength shortening capacitance. The stray capacitance between the input terminal T1 and the ground is indicated by a broken line at C5, and the stray capacitance between the output terminal T2 and the ground is indicated by a broken line at C6. The input terminal T1, output terminal T2, and ground of FIG. 12 are the input terminal conductor layer 3, output terminal conductor layer 4, ground terminal conductor layer 5, and FIG.
Corresponds to 6.

In order to obtain the circuit shown in FIG. 12, a large number of conductor layers are buried in the dielectric 2 as shown in FIGS. As for the dielectric 2, a conductive paste (for example, silver paste) is applied to a ceramic green sheet (porcelain raw sheet) as shown in FIG.
11 are printed in a predetermined pattern shown in FIG. 11, these are laminated and fired. Although the green sheets are integrated after firing, the first, second, third, fourth, fifth, sixth, seventh, and eighth dielectric layers 2a are indicated by broken lines in FIG. 2 for convenience of explanation. , 2b, 2c, 2d, 2e, 2f, 2g,
It is shown divided into 2h. The inner conductor layer is formed of the first, second, third, fourth, fifth, sixth in the thickness direction of the dielectric 2.
And the seventh height position H1, H2, H3, H4, H5, H
6 and H7.

Next, the pattern of each layer will be described. FIG. 4 shows the surface of the dielectric 2, that is, the surface of the first dielectric layer 2a. A part of the input terminal conductor layer 3, the output terminal conductor layer 4, and the ground terminal conductor layers 5, 6 protrude from this surface. In addition,
Even when each of the conductor layers 3 to 6 is formed so as not to protrude from the surface, the effect of the present invention can be obtained.

FIG. 5 shows the first ground conductor layer 7 on the surface of the second dielectric layer 2b and the first and second additional conductor layers 8, 9 according to the present invention. The first ground conductor layer 7 is provided in order to obtain an internal shield function and a strip line function, and is formed in a wide area so as to connect the long sides of the pair of the second dielectric layers 2b. One end and the other end are exposed on the third and fourth side surfaces, and are connected to the ground conductor layers 5 and 6. The first and second additional conductor layers 8 and 9 project from the center of the pair of short sides (first and second side surfaces) of the second dielectric layer 2b toward the opposite side (side surface). They are formed and have one ends exposed on the first and second side faces and connected to the input and output terminal conductor layers 3,4.
Since the additional conductor layers 8 and 9 face the ground conductor layer 7 with a predetermined gap, a stray capacitance is obtained between the two. A ground conductor layer 7, first and second additional conductor layers 8,
No. 9 is formed by simultaneously printing a conductive paste on the same green sheet (porcelain raw sheet), so that there is almost no variation in the mutual positional relationship during mass production. For example, if the ground conductor layer 7 is shifted to the right in FIG. 5, the additional conductor layers 8 and 9 are also shifted to the right, so that the gap between the two does not change. Therefore, the variation of the stray capacitance of the input and output terminal conductor layers 3 and 4 with respect to the ground is reduced. In this embodiment, the width W1 of the terminal conductor layers 3 and 4 and the width W2 of the additional conductor layers 8 and 9 are the same. Also, the first and second terminal conductor layers 3 and 4 and the ground conductor layers 7 and 1
7 and the shortest distance connecting the ground conductor layers 5 and 6 are longer than the shortest distance connecting the additional conductor layers 8, 9, 18 and 19 and the ground conductor layers 7 and 17. In short, the additional conductor layer 8,
The capacitance between 9, 18, 19 and the ground conductor layers 7, 17 is larger than the capacitance between the terminal conductor layers 3, 4, the ground conductor layers 7, 17 and the ground terminal conductor layers 5, 6. The positions and sizes of the additional conductor layers 8, 9, 18, and 19 are determined.

A wavelength shortening conductor layer 1 connected to a ground terminal conductor layer 5 is provided on the surface of a third dielectric layer 2c shown in FIG.
0 is provided, one end of which is exposed on the third side surface and is connected to the first ground terminal conductor layer 5. This conductor layer 1
Since 0 is opposed to the leading ends of the stripline conductor layers 13 and 14 shown in FIG. 8, the wavelength shortening capacitors C3 and C4 of FIG. 12 are provided. The conductor layer 10 is divided into two conductor layers 10a and 10b as shown by a broken line in FIG.
The strip line conductor layers 13 and 14 may be opposed to each other.

On the surface of the fourth dielectric layer 2d shown in FIG. 7, capacitor conductor layers 11, 12 functioning as one electrode (element formation conductor layer) of the first and second coupling capacitors C1, C2. Is provided. One end of each of the capacitor conductor layers 11 and 12 is exposed on the first and second side surfaces.
The input and output terminals are connected to the conductor layers 3 and 4.

On the surface of a fifth dielectric layer 2e shown in FIG. 8, conductor layers 13 and 14 for first and second strip lines L1 and L2 as conductor layers for element formation are provided from one of the long sides to the other. Juxtaposed so as to extend toward Since the first and second stripline conductor layers 13 and 14 have areas overlapping the coupling capacitor conductor layers 11 and 12 in FIG.
1 between the strip line 2 and the conductor layers 13 and 14 for strip lines.
The capacitance corresponding to the coupling capacitors C1 and C2 shown in FIG. First and second stripline conductor layers 1
Numerals 3 and 14 constitute quarter-wave TEM mode resonators, which function equivalently as LC parallel resonance circuits and are inductively coupled to each other because they are close to each other. First and second conductor layers 13 for strip lines,
One end of 14 is exposed on the fourth side surface, is connected to the ground terminal conductor layer 6, and the other end is an open end.

A conductor layer 15 for first and second mutual coupling capacitors C7 and C8 is provided on the surface of the sixth dielectric layer 2f shown in FIG. The conductor layer 15 is a plan view of the first and second strip line conductor layers 1 of FIG.
The capacitors C7 and C8 shown in FIG. 12 are provided since they are arranged so as to overlap 3 and 14.

The wavelength shortening conductor layer 1 connected to the ground terminal conductor layer 5 is provided on the surface of the seventh conductor layer 2g shown in FIG.
6 are provided. Since the conductor layer 16 and the conductor layer 10 of FIG. 6 are opposed to areas near the open ends of the strip line conductor layers 13 and 14 of FIG. 8 via the dielectric layer, the conductor layers 10 and 16 of FIG. Wavelength shortening capacitor C3
, C4.

On the surface of the eighth dielectric layer 2h shown in FIG. 11, a second ground conductor layer 17, and third and fourth additional conductor layers 18, 19 for obtaining an internal shield function and a strip line function are provided. Is provided. The pattern of these conductor layers 17, 18, 19 in FIG.
8 and 9 are substantially the same. These conductor layers 17, 1
Reference numerals 8 and 19 are connected to the ground terminal conductor layers 5 and 6 and the input / output terminal conductor layers 3 and 4 similarly to the conductor layers 7 8 and 9 in FIG. Therefore, the additional conductor layers 18 and 19 in FIG. 11 have the same functions as the additional conductor layers 8 and 9 in FIG.

On the bottom surface of the dielectric 2, that is, on the back surface of the eighth dielectric layer 2h, portions of the input and output terminal conductor layers 3, 4 and the ground terminal conductor layers 5, 6 protrude, as in FIG. The input and output terminal conductor layers 3 and 4 and the ground terminal conductor layers 5 and 6 were baked by applying a conductor paste containing a metal having a higher melting point than the metal of the internal conductor layer to the outer peripheral surface of the dielectric 2. Things.

As is clear from the above description, in this embodiment, the additional conductor layers 7, 8 and 18 in which the stray capacitances C5 and C6 between the input and output terminal conductor layers 3 and 4 and the ground are formed in the same step. , 19 and the ground conductor layers 7 and 17, the input and output terminal conductor layers 3, 4 and the ground terminal conductor layers 5, 6 protrude from the front surface (upper surface) and back surface (bottom surface). Even if variations in the amount of wraparound and variations in the positions and widths of the terminal conductor layers 3, 4, 5, and 6 on the first to fourth side surfaces of the dielectric 2 occur, variations in the stray capacitances C5 and C6 are reduced. , It is possible to obtain desired filter characteristics.

[0020]

Second Embodiment Next, a laminated filter according to a second embodiment will be described with reference to FIG. FIG. 13 shows a pattern of the surface of the second dielectric layer 2b corresponding to FIG. 5 showing the first embodiment.
Are shown. In FIG. 13, portions common to FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted. The protruding portions (tip portions) of the additional conductor layers 8a and 9a in FIG. 13 have a width W2 wider than the width W1 of the input and output terminal conductor layers 3 and 4. In the multilayer filter of the second embodiment,
Those corresponding to the conductor layers 17, 18, 19 of the eighth dielectric layer 2h shown in FIG. 11 of the first embodiment are also modified similarly to FIG. It is desirable that the width W2 is set to be three times or less, more preferably twice or less, the width W1. W2
Is within such a range, the unnecessary increase of the stray capacitances C5 and C6 can be suppressed, and the dispersion of C5 and C6 can be reduced. The laminated filter according to the second embodiment includes:
Except that the additional conductor layers 8, 9, 18, and 19 of the first embodiment are broadly modified, they are configured the same as the multilayer filter of the first embodiment, so that they are the same as the multilayer filter of the first embodiment. In addition to the effect of the above, there is an effect that the stray capacitance can be further suppressed.

[0021]

Third Embodiment Next, a laminated filter according to a third embodiment will be described with reference to FIG. FIG. 14 shows a pattern of the surface of the second dielectric layer 2b corresponding to FIG.
In FIG. 14, portions common to FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 14, the ground conductor layer 7
Are provided with concave portions 7a and 7b, and a wide additional conductor layer 8 is provided here.
b and 9b are opposed to each other. Further, in the multilayer filter of the third embodiment, the filter corresponding to the conductor layers 17, 18, and 19 of the eighth dielectric layer 2h of the first embodiment shown in FIG. Have been. The multilayer filter according to the third embodiment includes the conductor layers 7, 8, 9,
The configuration is the same as that of the first embodiment except that the components 17, 18, and 19 are modified as shown in FIG. 14, so that in addition to having the same operation and effect as the first embodiment, the variation of the stray capacitance is reduced. It has the effect that it can be suppressed well.

[0022]

Fourth Embodiment Next, a multilayer filter according to a fourth embodiment will be described with reference to FIGS. However, in FIGS. 15 and 16, substantially the same parts as those in FIGS. 1 to 12 are denoted by the same reference numerals, and description thereof will be omitted. FIG. 15 is an exploded perspective view of the multilayer filter of the fourth embodiment. In FIG. 15, each conductor layer is shown with its thickness omitted.
It is also shown with dots to distinguish it from others.
The dielectric layers 2a, 2b, 2d, 2e, 2f, 2h of FIG.
Are the dielectric layers 2a, 2b, 2c, 2d, 2e, 2 in FIG.
f, 2h. First Embodiment and Fourth Embodiment
The difference of the fourth embodiment is that the second dielectric layer 2b of FIG. 2 showing the first embodiment is different from the second and third dielectric layers of FIG.
In the first embodiment, the point that the seventh dielectric layer 2g in FIG. 2 is combined with the sixth and seventh dielectric layers 2f and 2g in FIG. In the fourth embodiment, five waveform shortening conductor layers 10a, 10b, 10c, 16a, and 16b are provided, whereas the waveform shortening conductor layers 10 and 16 are provided on the independent dielectric layers 2c and 2g. 4th
And a point provided with the input and output coupling conductor layers 11 and 12 and the mutual coupling conductor layer 15 on the sixth dielectric layers 2d and 2f, and a third stripline conductor layer 30 is added, and the waveform for this is added. Except for the addition of the shortening conductor layer 10c and the provision of the trapping conductor layer 16c, the configuration of the first embodiment and the configuration of the fourth embodiment are substantially the same except for these. In the fourth embodiment, the ground terminal conductor layers 5, 6 are provided by applying a conductive paste to all of the third and fourth side surfaces of the dielectric, so that the top and bottom surfaces are provided. Not only does it go around the first and second side surfaces, but also slightly.

FIG. 16 is an equivalent circuit of the multilayer filter of FIG. 15, in which terminals T1 and T2 are the input and output terminal conductor layers 3,
4, the ground lines correspond to the ground terminal conductor layers 5, 6 and the inner ground conductor layers 7, 17, the strip lines L2, L2, L3 correspond to the conductor layers 13, 14, 30, and the capacitors C1, C2. Corresponds to the capacitance between the conductor layers 11, 12 and the conductor layers 13, 14, and the capacitors C7, C7
8 corresponds to the capacitance between the conductor layers 13, 14, 30 and the conductor layer 15, and the capacitors C3, C4, C10 are
a, 10b, 10c and the capacitance between the conductor layers 13, 14, 30;
6c, the capacitor C5 corresponds to the capacitance between the additional conductor layers 8, 18 and the ground conductor layers 7, 17, and the capacitor C6 corresponds to the additional conductor layers 9, 19 and the ground conductor layer 7, 17 corresponding to the capacity.

The same operation and effect as in the first embodiment can be obtained also in the laminated filter having three-stage strip lines shown in FIGS.

[0025]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The number, type, and the like of the filter-constituting circuit elements embedded in the dielectric 2 can be variously changed. (2) One or more of those selected from the additional conductor layers 9, 18, 19 can be omitted. (3) It can be configured so as not to have the mutual inductive coupling indicated by M in FIGS. Further, the coupling of the capacitors C7 and C8 may be omitted, and the strip lines L1, L2 or L1, L2, L3 may be coupled only by the mutual inductive coupling M. (4) In the embodiment, the strip line conductor layers 13, 1
4, 30 are arranged in a comb-line shape (comb shape), but are interdigital (integer).
(digital) configuration. Also,
The first stage of the input-stage strip line among the plurality of strip lines arranged in a comb line or interdigital
The present invention can also be applied to a configuration in which the one corresponding to the terminal conductor layer 3 is connected and the one corresponding to the second terminal conductor layer 4 is connected to the strip line at the output stage.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a multilayer filter according to a first embodiment of the present invention.

FIG. 2 is a reduced sectional view of a portion of the multilayer filter corresponding to line AA in FIG. 3;

FIG. 3 is an enlarged plan view showing an internal conductor layer of the multilayer filter of FIG. 1 by a dotted line.

FIG. 4 is a plan view of the multilayer filter of FIG. 1;

FIG. 5 is a plan view showing a surface of a second dielectric layer in FIG. 2;

FIG. 6 is a plan view showing a surface of a third dielectric layer in FIG. 2;

FIG. 7 is a plan view showing a surface of a fourth dielectric layer in FIG. 2;

FIG. 8 is a plan view showing a surface of a fifth dielectric layer in FIG. 2;

FIG. 9 is a plan view showing a surface of a sixth dielectric layer in FIG. 2;

FIG. 10 is a plan view showing a surface of a seventh dielectric layer in FIG. 2;

FIG. 11 is a plan view showing the surface of an eighth dielectric layer in FIG. 2;

FIG. 12 is an equivalent circuit diagram of the multilayer filter of FIG.

FIG. 13 is a plan view illustrating a surface of a second dielectric layer of the multilayer filter according to the second embodiment.

FIG. 14 is a plan view illustrating a surface of a second dielectric layer of the multilayer filter according to the third embodiment.

FIG. 15 is an exploded perspective view of a dielectric filter according to a fourth embodiment.

16 is an equivalent circuit diagram of the dielectric filter of FIG.

[Explanation of symbols]

 2 Dielectric 3 Input terminal conductor layer 4 Output terminal conductor layer 5, 6 Ground terminal conductor layer 7 Ground conductor layer 8, 9 Additional conductor layer

Claims (17)

[Claims] An external signal terminal conductor provided with an element forming conductor layer and a ground conductor layer at different thickness positions inside a dielectric, and connected to the element forming conductor layer on an outer peripheral surface of the dielectric. In a multilayer electronic component provided with a layer and an external ground terminal conductor layer connected to the ground conductor layer, an additional conductor layer is provided in the same thickness direction position as the ground conductor layer inside the dielectric, The laminated electronic component, wherein the additional conductor layer is connected to the external signal terminal conductor layer. 2. A top surface, a bottom surface, and first, second, third and fourth surfaces.
At least a ground conductor layer and a plurality of element forming conductor layers are provided at different positions in the thickness direction in a prismatic dielectric having a side surface of a first terminal conductor layer on the first side surface of the dielectric. Is provided, and a second terminal conductive layer is provided on a second side surface of the dielectric body facing the first side surface, and a ground terminal is provided on at least one of the third and fourth side surfaces of the dielectric body. A conductive layer is provided, and at least one of the plurality of element forming conductive layers is the first side surface of the first side.
And at least one of the plurality of element forming conductor layers is the second side surface of the second side.
And the ground conductor layer is connected to the ground terminal conductor layer, wherein at least one additional conductor is located at the same thickness direction position in the dielectric as the ground conductor layer. A layer is provided, and the additional conductor layer is disposed so as to have a predetermined distance from the ground conductor layer, and is formed based on the same printing step as the printing step of the ground conductor layer, and the first terminal A multilayer electronic component connected to a conductor layer. 3. The first terminal conductor layer is formed in a strip shape on the first side surface so as to extend from the top surface to the bottom surface, and the additional conductor layer is the same as the ground conductor layer. At a position in the thickness direction of the first conductive member extending from the first side surface toward the second side surface, wherein a width of a portion of the additional conductive layer facing the ground conductive layer is the first band-shaped portion. 3. The multilayer electronic component according to claim 2, wherein the width is set to be equal to or larger than the width of the terminal conductor layer. 4. The first terminal conductor layer is formed in a strip shape on the first side surface so as to extend from the upper surface toward the bottom surface, and the additional conductor layer is the same as the ground conductor layer. At a position in the thickness direction of the first conductive member extending from the first side surface toward the second side surface, wherein a width of a portion of the additional conductive layer facing the ground conductive layer is the first band-shaped portion. 4. The multilayer electronic component according to claim 2, wherein the width is set to twice or less the width of the terminal conductor layer. 5. A top surface, a bottom surface, first, second, third and fourth surfaces.
At least a ground conductor layer and a plurality of element forming conductor layers are provided at different positions in the thickness direction in a prismatic dielectric having a side surface of a first terminal conductor layer on the first side surface of the dielectric. Is provided, and a second terminal conductive layer is provided on a second side surface of the dielectric body facing the first side surface, and a ground terminal is provided on at least one of the third and fourth side surfaces of the dielectric body. A conductive layer is provided, and at least one of the plurality of element forming conductive layers is the first side surface of the first side.
And at least one of the plurality of element forming conductor layers is the second side surface of the second side.
And the ground conductor layer is connected to the ground terminal conductor layer, wherein the first and second conductors are located at the same thickness direction position in the dielectric as the ground conductor layer. The first and second additional conductor layers are arranged so as to have a predetermined distance from the ground conductor layer, and are based on the same printing step as the printing step of the ground conductor layer. A multilayer electronic component, which is formed and connected to the first and second terminal conductor layers, respectively. 6. The first and second terminal conductor layers are formed in a strip shape on the first and second side surfaces so as to extend from the upper surface toward the bottom surface. The conductor layer is formed so as to extend from the first side surface toward the second side surface at the same thickness direction position as the ground conductor layer, and the second additional conductor layer is the same as the ground conductor layer At a position in the thickness direction of the second side surface extending from the second side surface side to the first side surface side, and a width of a portion of the first and second additional conductor layers facing the ground conductor layer is the band shape. 6. The multilayer electronic component according to claim 5, wherein the width is set to be equal to or greater than the width of the first and second terminal conductor layers. 7. The first and second terminal conductor layers are formed in a strip shape on the first and second side surfaces so as to extend from the top surface to the bottom surface. The conductor layer is formed so as to extend from the first side surface toward the second side surface at the same thickness direction position as the ground conductor layer, and the second additional conductor layer is the same as the ground conductor layer At a position in the thickness direction of the second side surface extending from the second side surface side to the first side surface side, and a width of a portion of the first and second additional conductor layers facing the ground conductor layer is the band shape. 7. The multilayer electronic component according to claim 5, wherein the thickness is set to be twice or less of the first and second terminal conductor layers. 8. 8. The ground conductor layer includes: a first ground conductor layer disposed at a position in a thickness direction between an upper surface of the dielectric and the element forming conductor layer; a bottom surface of the dielectric and the element; A second ground conductor layer disposed at a position in the thickness direction between the second conductor layer and the formation conductor layer, and the additional conductor layer is provided at the same thickness direction position as the first and second ground conductor layers. The multilayer electronic component according to claim 1, 2, 3, 4, 5, 6, or 7. 9. The top, bottom, first, second, third and fourth surfaces.
At least the ground conductor layer and the first and second conductors are located at different positions in the thickness direction in the prismatic dielectric having
Are provided, a first and second input / output capacitance conductor layer, and an inter-resonator coupling capacitance conductor layer, and the first and second stripline conductor layers are connected to each other via a dielectric layer. The first input / output capacitance conductor layer faces the first strip line conductor layer via a dielectric layer, and the second input / output capacitance conductor layer faces the first strip line conductor layer via a dielectric layer. And the first and second strip line conductor layers face each other through a dielectric layer, and the first input / output capacitance Part of the conductor layer is the first layer.
The second input / output capacitor conductor layer is disposed so as to be exposed on a side surface thereof, and the second input / output capacitor conductor layer is disposed such that a part thereof is exposed on a second side surface opposite to the first side surface, and the ground conductor layer is disposed on the second side surface. A first input / output terminal conductor layer connected to the first input / output capacitance conductor layer is disposed on the first side surface so as to be partially exposed to at least one of the third and fourth side surfaces. A second input / output terminal conductor layer connected to the second input / output capacitance conductor layer is provided on the second side surface;
A ground terminal conductor layer is provided on at least one of the third and fourth side surfaces, and the ground terminal conductor layer is connected to the ground conductor layer and the first and second side surfaces are connected to the ground terminal conductor layer.
A laminated electronic component connected to one end of the strip line conductor layer, wherein the additional conductor layer is provided at the same thickness direction position as that of the dielectric where the ground conductor layer is provided; The conductor layer is disposed so as to have a predetermined distance from the ground conductor layer, is formed based on the same printing process as the printing process of the ground conductor layer, and is connected to the first input / output terminal conductor layer. A multilayer electronic component characterized by the following. 10. A prismatic dielectric having an upper surface, a bottom surface, and first, second, third and fourth side surfaces, at least in the thickness direction different positions in the thickness direction, and at least the first and second ground conductor layers. A strip line conductor layer, first and second input / output capacitance conductor layers, and an inter-resonator coupling capacitance conductor layer are provided, and the first and second strip line conductor layers are connected to each other via a dielectric layer; Layers, the first input / output capacitor conductor layer faces the first stripline conductor layer via a dielectric layer, and the second input / output capacitor conductor layer faces via a dielectric layer. Opposing the second strip line conductor layer, the inter-resonator coupling capacitance conductor layer opposing the first and second strip line conductor layers via a dielectric layer, and The layer is partially exposed on the first side surface And the second input / output capacitor conductor layer has a second portion which is partially opposed to the first side surface.
The ground conductor layer is disposed so as to be exposed on at least one of the third and fourth side surfaces, and the first conductor is disposed on the first side surface.
A first input / output terminal conductor layer connected to the input / output capacitance conductor layer is provided, and a second input / output terminal conductor layer connected to the second input / output capacitance conductor layer is provided on the second side surface. A ground terminal conductor layer is provided on at least one of the third and fourth side surfaces, the ground terminal conductor layer is connected to the ground conductor layer, and the first and second strip line conductor layers are provided. Wherein the first and second additional conductor layers are respectively provided at the same thickness direction position as the thickness direction position of the dielectric body where the ground conductor layer is provided, The first and second additional conductor layers are arranged so as to have a predetermined interval with respect to the ground conductor layer, and are formed based on the same printing step as the printing step of the ground conductor layer, respectively. Multilayer electronic component, characterized in that it is connected to the first and second input-output terminal conductor layer. 11. A prismatic dielectric having an upper surface, a bottom surface, and first, second, third, and fourth side surfaces, and at least a ground conductor layer and a first and a second conductive member are provided at different thickness directions in a prismatic dielectric. A stripline conductor layer, first and second input / output capacitance conductor layers, and an inter-resonator coupling capacitance conductor layer are provided, and the first and second stripline conductor layers are located at the same position in the thickness direction of the dielectric. Are arranged side by side so as to mutually inductively couple with each other, and respectively oppose the ground conductor layer via a dielectric layer, and the first input / output capacitance conductor layer is connected to the first strip line conductor layer via a dielectric layer. , The second input / output capacitance conductor layer faces the second strip line conductor layer via a dielectric layer, and the inter-resonator coupling capacitance conductor layer faces the first And the second
, The first input / output capacitance conductor layer is disposed such that a part thereof is exposed to the first side surface, and the second input / output capacitance conductor layer has a part thereof. The ground conductor layer is disposed so as to be exposed on a second side surface opposite to the first side surface, and the ground conductor layer is disposed so as to be partially exposed on at least one of the third and fourth side surfaces. A first input / output terminal conductor layer connected to the first input / output capacitor conductor layer on one side surface;
The second side connected to the second input / output capacitor conductor layer
And a ground terminal conductor layer is provided on at least one of the third and fourth side surfaces,
In the multilayer electronic component in which the ground terminal conductor layer is connected to the ground conductor layer and connected to one ends of the first and second stripline conductor layers, the ground conductor layer of the dielectric is provided. An additional conductor layer is provided at the same thickness direction position as the thickness direction position, and the additional conductor layer is arranged so as to have a predetermined interval with respect to the ground conductor layer, and a step of printing the ground conductor layer; A multilayer electronic component formed based on the same printing process and connected to the first input / output terminal conductor layer. 12. A prismatic dielectric having an upper surface, a bottom surface, and first, second, third, and fourth side surfaces, and at least a ground conductor layer and first and second dielectric layers located at different thickness-direction positions in a prismatic dielectric. A stripline conductor layer, first and second input / output capacitance conductor layers, and an inter-resonator coupling capacitance conductor layer are provided, and the first and second stripline conductor layers are located at the same position in the thickness direction of the dielectric. Are arranged side by side so as to mutually inductively couple and oppose the ground conductor layer via a dielectric layer, and the first input / output capacitance conductor layer is connected to the first stripline conductor layer via a dielectric layer. The second input / output capacitor conductor layer faces the second input / output capacitor conductor layer via a dielectric layer.
, The inter-resonator coupling capacitance conductor layer faces the first and second strip line conductor layers via a dielectric layer, and the first input / output capacitance conductor layer A part is arranged so as to be exposed on the first side surface, and the second input / output capacitor conductor layer is arranged so that a part thereof is exposed on a second side surface opposed to the first side surface; Part of the ground conductor layer is the third and fourth ground conductor layers.
A first input / output terminal conductor layer connected to the first input / output capacitance conductor layer is provided on the first side surface, and the second input / output terminal conductor layer is provided on the second side surface. A second input / output terminal conductor layer connected to the second input / output capacitor conductor layer; a ground terminal conductor layer provided on at least one of the third and fourth side surfaces; Is connected to the ground conductor layer and is connected to one end of the first and second stripline conductor layers, in the thickness direction in which the ground conductor layer of the dielectric is provided First and second additional conductor layers are provided at the same position in the thickness direction as the position, and the first and second additional conductor layers are arranged so as to have a predetermined distance from the ground conductor layer; Said Multilayer electronic component, characterized in that it is connected to and the first and second input-output terminal conductor layers are formed respectively on the basis of the printing process and the same printing process of the land conductor layer. 13. The structure according to claim 11, wherein said inter-resonator coupling capacitive conductor layer is omitted.
The laminated electronic component as described in the above. 14. The ground conductor layer is disposed at a first thickness direction position between an upper surface of the dielectric and the first and second strip conductor layers and the inter-resonator coupling capacitance conductor layer. A first ground conductor layer, a second ground plane disposed at a second thickness direction between the bottom surface of the dielectric, the first and second strip conductor layers, and the inter-resonator coupling capacitance conductor layer; 13. The ground conductor layer, wherein the additional conductor layer is provided at the same position in the thickness direction as the first and second ground conductor layers, respectively. Laminated electronic components. 15. The semiconductor device according to claim 9, wherein at least a third stripline conductor layer is arranged between the first and second stripline conductor layers.
The multilayer electronic component according to 0, 11, 11, 12, 13, or 14. 16. The first terminal conductor layer is formed in a strip shape on the first side surface so as to extend from the upper surface toward the bottom surface, and the additional conductor layer is the same as the ground conductor layer. At a position in the thickness direction of the first conductive member extending from the first side surface toward the second side surface, wherein a width of a portion of the additional conductive layer facing the ground conductive layer is the first band-shaped portion. The multilayer electronic component according to claim 9, wherein the width is set to be equal to or greater than the width of the terminal conductor layer. 17. The first terminal conductor layer is formed on the first side surface so as to extend in a belt shape from the top surface to the bottom surface, and the additional conductor layer is the same as the ground conductor layer. At a position in the thickness direction of the first conductive member extending from the first side surface toward the second side surface, wherein a width of a portion of the additional conductive layer facing the ground conductive layer is the first band-shaped portion. The multilayer electronic component according to claim 9, wherein the width is set to be equal to or less than twice the width of the terminal conductor layer.